rk_i2s.c revision 1.1.2.3
1 /* $NetBSD: rk_i2s.c,v 1.1.2.3 2020/01/21 10:39:59 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_i2s.c,v 1.1.2.3 2020/01/21 10:39:59 martin Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 38 #include <sys/audioio.h> 39 #include <dev/audio/audio_if.h> 40 #include <dev/audio/linear.h> 41 42 #include <dev/fdt/fdtvar.h> 43 #include <dev/fdt/syscon.h> 44 45 #define RK_I2S_FIFO_DEPTH 32 46 #define RK_I2S_SAMPLE_RATE 48000 47 48 #define I2S_TXCR 0x00 49 #define TXCR_RCNT __BITS(22,17) 50 #define TXCR_TCSR __BITS(16,15) 51 #define TXCR_HWT __BIT(14) 52 #define TXCR_SJM __BIT(12) 53 #define TXCR_FBM __BIT(11) 54 #define TXCR_IBM __BITS(10,9) 55 #define TXCR_PBM __BITS(8,7) 56 #define TXCR_TFS __BIT(5) 57 #define TXCR_VDW __BITS(4,0) 58 #define I2S_RXCR 0x04 59 #define RXCR_RCSR __BITS(16,15) 60 #define RXCR_HWT __BIT(14) 61 #define RXCR_SJM __BIT(12) 62 #define RXCR_FBM __BIT(11) 63 #define RXCR_IBM __BITS(10,9) 64 #define RXCR_PBM __BITS(8,7) 65 #define RXCR_TFS __BIT(5) 66 #define RXCR_VDW __BITS(4,0) 67 #define I2S_CKR 0x08 68 #define CKR_TRCM __BITS(29,28) 69 #define CKR_MSS __BIT(27) 70 #define CKR_CKP __BIT(26) 71 #define CKR_RLP __BIT(25) 72 #define CKR_TLP __BIT(24) 73 #define CKR_MDIV __BITS(23,16) 74 #define CKR_RSD __BITS(15,8) 75 #define CKR_TSD __BITS(7,0) 76 #define I2S_TXFIFOLR 0x0c 77 #define TXFIFOLR_TFL(n) __BITS((n) * 6 + 5, (n) * 6) 78 #define I2S_DMACR 0x10 79 #define DMACR_RDE __BIT(24) 80 #define DMACR_RDL __BITS(20,16) 81 #define DMACR_TDE __BIT(8) 82 #define DMACR_TDL __BITS(4,0) 83 #define I2S_INTCR 0x14 84 #define INTCR_RFT __BITS(24,20) 85 #define INTCR_RXOIC __BIT(18) 86 #define INTCR_RXOIE __BIT(17) 87 #define INTCR_RXFIE __BIT(16) 88 #define INTCR_TFT __BITS(8,4) 89 #define INTCR_TXUIC __BIT(2) 90 #define INTCR_TXUIE __BIT(1) 91 #define INTCR_TXEIE __BIT(0) 92 #define I2S_INTSR 0x18 93 #define INTSR_RXOI __BIT(17) 94 #define INTSR_RXFI __BIT(16) 95 #define INTSR_TXUI __BIT(1) 96 #define INTSR_TXEI __BIT(0) 97 #define I2S_XFER 0x1c 98 #define XFER_RXS __BIT(1) 99 #define XFER_TXS __BIT(0) 100 #define I2S_CLR 0x20 101 #define CLR_RXC __BIT(1) 102 #define CLR_TXC __BIT(0) 103 #define I2S_TXDR 0x24 104 #define I2S_RXDR 0x28 105 #define I2S_RXFIFOLR 0x2c 106 #define RXFIFOLR_RFL(n) __BITS((n) * 6 + 5, (n) * 6) 107 108 struct rk_i2s_config { 109 bus_size_t oe_reg; 110 u_int oe_mask; 111 u_int oe_val; 112 }; 113 114 static const struct rk_i2s_config rk3399_i2s_config = { 115 .oe_reg = 0x0e220, 116 .oe_mask = __BITS(13,11), 117 .oe_val = 0x7, 118 }; 119 120 static const struct of_compat_data compat_data[] = { 121 { "rockchip,rk3399-i2s", (uintptr_t)&rk3399_i2s_config }, 122 { NULL } 123 }; 124 125 struct rk_i2s_softc; 126 127 struct rk_i2s_chan { 128 uint32_t *ch_start; 129 uint32_t *ch_end; 130 uint32_t *ch_cur; 131 132 int ch_blksize; 133 int ch_resid; 134 135 void (*ch_intr)(void *); 136 void *ch_intrarg; 137 }; 138 139 struct rk_i2s_softc { 140 device_t sc_dev; 141 bus_space_tag_t sc_bst; 142 bus_space_handle_t sc_bsh; 143 int sc_phandle; 144 struct clk *sc_clk; 145 struct syscon *sc_grf; 146 const struct rk_i2s_config *sc_conf; 147 148 kmutex_t sc_lock; 149 kmutex_t sc_intr_lock; 150 151 struct audio_format sc_format; 152 153 struct rk_i2s_chan sc_pchan; 154 struct rk_i2s_chan sc_rchan; 155 156 u_int sc_active; 157 158 struct audio_dai_device sc_dai; 159 }; 160 161 #define RD4(sc, reg) \ 162 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 163 #define WR4(sc, reg, val) \ 164 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 165 166 static int 167 rk_i2s_query_format(void *priv, audio_format_query_t *afp) 168 { 169 struct rk_i2s_softc * const sc = priv; 170 171 return audio_query_format(&sc->sc_format, 1, afp); 172 } 173 174 static int 175 rk_i2s_set_format(void *priv, int setmode, 176 const audio_params_t *play, const audio_params_t *rec, 177 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 178 { 179 struct rk_i2s_softc * const sc = priv; 180 uint32_t ckr, txcr, rxcr; 181 182 ckr = RD4(sc, I2S_CKR); 183 if ((ckr & CKR_MSS) == 0) { 184 const u_int mclk_rate = clk_get_rate(sc->sc_clk); 185 const u_int bclk_rate = 2 * 32 * RK_I2S_SAMPLE_RATE; 186 const u_int bclk_div = mclk_rate / bclk_rate; 187 const u_int lrck_div = bclk_rate / RK_I2S_SAMPLE_RATE; 188 189 ckr &= ~CKR_MDIV; 190 ckr |= __SHIFTIN(bclk_div - 1, CKR_MDIV); 191 ckr &= ~CKR_TSD; 192 ckr |= __SHIFTIN(lrck_div - 1, CKR_TSD); 193 ckr &= ~CKR_RSD; 194 ckr |= __SHIFTIN(lrck_div - 1, CKR_RSD); 195 } 196 197 ckr &= ~CKR_TRCM; 198 ckr |= __SHIFTIN(0, CKR_TRCM); 199 WR4(sc, I2S_CKR, ckr); 200 201 if (play && (setmode & AUMODE_PLAY) != 0) { 202 if (play->channels & 1) 203 return EINVAL; 204 txcr = RD4(sc, I2S_TXCR); 205 txcr &= ~TXCR_VDW; 206 txcr |= __SHIFTIN(play->validbits - 1, TXCR_VDW); 207 txcr &= ~TXCR_TCSR; 208 txcr |= __SHIFTIN(play->channels / 2 - 1, TXCR_TCSR); 209 WR4(sc, I2S_TXCR, txcr); 210 } 211 212 if (rec && (setmode & AUMODE_RECORD) != 0) { 213 if (rec->channels & 1) 214 return EINVAL; 215 rxcr = RD4(sc, I2S_RXCR); 216 rxcr &= ~RXCR_VDW; 217 rxcr |= __SHIFTIN(rec->validbits - 1, RXCR_VDW); 218 rxcr &= ~RXCR_RCSR; 219 rxcr |= __SHIFTIN(rec->channels / 2 - 1, RXCR_RCSR); 220 WR4(sc, I2S_RXCR, rxcr); 221 } 222 223 return 0; 224 } 225 226 static int 227 rk_i2s_get_props(void *priv) 228 { 229 230 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 231 AUDIO_PROP_FULLDUPLEX; 232 } 233 234 static int 235 rk_i2s_round_blocksize(void *priv, int bs, int mode, 236 const audio_params_t *params) 237 { 238 bs &= ~3; 239 if (bs == 0) 240 bs = 4; 241 return bs; 242 } 243 244 static void * 245 rk_i2s_allocm(void *priv, int dir, size_t size) 246 { 247 return kmem_zalloc(size, KM_SLEEP); 248 } 249 250 static void 251 rk_i2s_freem(void *priv, void *addr, size_t size) 252 { 253 kmem_free(addr, size); 254 } 255 256 static int 257 rk_i2s_trigger_output(void *priv, void *start, void *end, int blksize, 258 void (*intr)(void *), void *intrarg, const audio_params_t *params) 259 { 260 struct rk_i2s_softc * const sc = priv; 261 struct rk_i2s_chan *ch = &sc->sc_pchan; 262 uint32_t val; 263 264 if (sc->sc_active == 0) { 265 val = RD4(sc, I2S_XFER); 266 val |= (XFER_TXS | XFER_RXS); 267 WR4(sc, I2S_XFER, val); 268 } 269 270 sc->sc_active |= XFER_TXS; 271 272 val = RD4(sc, I2S_INTCR); 273 val |= INTCR_TXEIE; 274 val &= ~INTCR_TFT; 275 val |= __SHIFTIN(RK_I2S_FIFO_DEPTH / 2, INTCR_TFT); 276 WR4(sc, I2S_INTCR, val); 277 278 ch->ch_intr = intr; 279 ch->ch_intrarg = intrarg; 280 ch->ch_start = ch->ch_cur = start; 281 ch->ch_end = end; 282 ch->ch_blksize = blksize; 283 ch->ch_resid = blksize; 284 285 return 0; 286 } 287 288 static int 289 rk_i2s_trigger_input(void *priv, void *start, void *end, int blksize, 290 void (*intr)(void *), void *intrarg, const audio_params_t *params) 291 { 292 return EIO; 293 } 294 295 static int 296 rk_i2s_halt_output(void *priv) 297 { 298 struct rk_i2s_softc * const sc = priv; 299 struct rk_i2s_chan *ch = &sc->sc_pchan; 300 uint32_t val; 301 302 sc->sc_active &= ~XFER_TXS; 303 if (sc->sc_active == 0) { 304 val = RD4(sc, I2S_XFER); 305 val &= ~(XFER_TXS|XFER_RXS); 306 WR4(sc, I2S_XFER, val); 307 } 308 309 val = RD4(sc, I2S_INTCR); 310 val &= ~INTCR_TXEIE; 311 WR4(sc, I2S_INTCR, val); 312 313 val = RD4(sc, I2S_CLR); 314 val |= CLR_TXC; 315 WR4(sc, I2S_CLR, val); 316 317 while ((RD4(sc, I2S_CLR) & CLR_TXC) != 0) 318 delay(1); 319 320 ch->ch_intr = NULL; 321 ch->ch_intrarg = NULL; 322 323 return 0; 324 } 325 326 static int 327 rk_i2s_halt_input(void *priv) 328 { 329 struct rk_i2s_softc * const sc = priv; 330 struct rk_i2s_chan *ch = &sc->sc_rchan; 331 uint32_t val; 332 333 sc->sc_active &= ~XFER_RXS; 334 if (sc->sc_active == 0) { 335 val = RD4(sc, I2S_XFER); 336 val &= ~(XFER_TXS|XFER_RXS); 337 WR4(sc, I2S_XFER, val); 338 } 339 340 val = RD4(sc, I2S_INTCR); 341 val &= ~INTCR_RXFIE; 342 WR4(sc, I2S_INTCR, val); 343 344 ch->ch_intr = NULL; 345 ch->ch_intrarg = NULL; 346 347 return 0; 348 } 349 350 static void 351 rk_i2s_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 352 { 353 struct rk_i2s_softc * const sc = priv; 354 355 *intr = &sc->sc_intr_lock; 356 *thread = &sc->sc_lock; 357 } 358 359 static const struct audio_hw_if rk_i2s_hw_if = { 360 .query_format = rk_i2s_query_format, 361 .set_format = rk_i2s_set_format, 362 .get_props = rk_i2s_get_props, 363 .round_blocksize = rk_i2s_round_blocksize, 364 .allocm = rk_i2s_allocm, 365 .freem = rk_i2s_freem, 366 .trigger_output = rk_i2s_trigger_output, 367 .trigger_input = rk_i2s_trigger_input, 368 .halt_output = rk_i2s_halt_output, 369 .halt_input = rk_i2s_halt_input, 370 .get_locks = rk_i2s_get_locks, 371 }; 372 373 static int 374 rk_i2s_intr(void *priv) 375 { 376 struct rk_i2s_softc * const sc = priv; 377 struct rk_i2s_chan * const pch = &sc->sc_pchan; 378 #if notyet 379 struct rk_i2s_chan * const rch = &sc->sc_rchan; 380 #endif 381 uint32_t sr, val; 382 int fifolr; 383 384 mutex_enter(&sc->sc_intr_lock); 385 386 sr = RD4(sc, I2S_INTSR); 387 388 if ((sr & INTSR_RXFI) != 0) { 389 #if notyet 390 val = RD4(sc, I2S_RXFIFOLR); 391 fifolr = __SHIFTOUT(val, RXFIFOLR_RFL(0)); 392 while (fifolr > 0) { 393 *rch->ch_data = RD4(sc, I2S_RXDR); 394 rch->ch_data++; 395 rch->ch_resid -= 4; 396 if (rch->ch_resid == 0) 397 rch->ch_intr(rch->ch_intrarg); 398 --fifolr; 399 } 400 #endif 401 } 402 403 if ((sr & INTSR_TXEI) != 0) { 404 val = RD4(sc, I2S_TXFIFOLR); 405 fifolr = __SHIFTOUT(val, TXFIFOLR_TFL(0)); 406 fifolr = uimin(fifolr, RK_I2S_FIFO_DEPTH); 407 while (fifolr < RK_I2S_FIFO_DEPTH - 1) { 408 WR4(sc, I2S_TXDR, *pch->ch_cur); 409 pch->ch_cur++; 410 if (pch->ch_cur == pch->ch_end) 411 pch->ch_cur = pch->ch_start; 412 pch->ch_resid -= 4; 413 if (pch->ch_resid == 0) { 414 pch->ch_intr(pch->ch_intrarg); 415 pch->ch_resid = pch->ch_blksize; 416 } 417 ++fifolr; 418 } 419 } 420 421 mutex_exit(&sc->sc_intr_lock); 422 423 return 0; 424 } 425 426 static int 427 rk_i2s_dai_set_sysclk(audio_dai_tag_t dai, u_int rate, int dir) 428 { 429 struct rk_i2s_softc * const sc = audio_dai_private(dai); 430 int error; 431 432 error = clk_set_rate(sc->sc_clk, rate); 433 if (error != 0) { 434 device_printf(sc->sc_dev, "failed to set sysclk to %u Hz: %d\n", 435 rate, error); 436 return error; 437 } 438 439 return 0; 440 } 441 442 static int 443 rk_i2s_dai_set_format(audio_dai_tag_t dai, u_int format) 444 { 445 struct rk_i2s_softc * const sc = audio_dai_private(dai); 446 uint32_t txcr, rxcr, ckr; 447 448 const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK); 449 const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK); 450 const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK); 451 452 txcr = RD4(sc, I2S_TXCR); 453 rxcr = RD4(sc, I2S_RXCR); 454 ckr = RD4(sc, I2S_CKR); 455 456 txcr &= ~(TXCR_IBM|TXCR_PBM|TXCR_TFS); 457 rxcr &= ~(RXCR_IBM|RXCR_PBM|RXCR_TFS); 458 switch (fmt) { 459 case AUDIO_DAI_FORMAT_I2S: 460 txcr |= __SHIFTIN(0, TXCR_IBM); 461 rxcr |= __SHIFTIN(0, RXCR_IBM); 462 break; 463 case AUDIO_DAI_FORMAT_LJ: 464 txcr |= __SHIFTIN(1, TXCR_IBM); 465 rxcr |= __SHIFTIN(1, RXCR_IBM); 466 break; 467 case AUDIO_DAI_FORMAT_RJ: 468 txcr |= __SHIFTIN(2, TXCR_IBM); 469 rxcr |= __SHIFTIN(2, RXCR_IBM); 470 break; 471 case AUDIO_DAI_FORMAT_DSPA: 472 txcr |= __SHIFTIN(0, TXCR_PBM); 473 txcr |= TXCR_TFS; 474 rxcr |= __SHIFTIN(0, RXCR_PBM); 475 txcr |= RXCR_TFS; 476 break; 477 case AUDIO_DAI_FORMAT_DSPB: 478 txcr |= __SHIFTIN(1, TXCR_PBM); 479 txcr |= TXCR_TFS; 480 rxcr |= __SHIFTIN(1, RXCR_PBM); 481 txcr |= RXCR_TFS; 482 break; 483 default: 484 return EINVAL; 485 } 486 487 WR4(sc, I2S_TXCR, txcr); 488 WR4(sc, I2S_RXCR, rxcr); 489 490 switch (pol) { 491 case AUDIO_DAI_POLARITY_IB_NF: 492 ckr |= CKR_CKP; 493 break; 494 case AUDIO_DAI_POLARITY_NB_NF: 495 ckr &= ~CKR_CKP; 496 break; 497 default: 498 return EINVAL; 499 } 500 501 switch (clk) { 502 case AUDIO_DAI_CLOCK_CBM_CFM: 503 ckr |= CKR_MSS; /* sclk input */ 504 break; 505 case AUDIO_DAI_CLOCK_CBS_CFS: 506 ckr &= ~CKR_MSS; /* sclk output */ 507 break; 508 default: 509 return EINVAL; 510 } 511 512 WR4(sc, I2S_CKR, ckr); 513 514 return 0; 515 } 516 517 static audio_dai_tag_t 518 rk_i2s_dai_get_tag(device_t dev, const void *data, size_t len) 519 { 520 struct rk_i2s_softc * const sc = device_private(dev); 521 522 if (len != 4) 523 return NULL; 524 525 return &sc->sc_dai; 526 } 527 528 static struct fdtbus_dai_controller_func rk_i2s_dai_funcs = { 529 .get_tag = rk_i2s_dai_get_tag 530 }; 531 532 static int 533 rk_i2s_clock_init(struct rk_i2s_softc *sc) 534 { 535 const int phandle = sc->sc_phandle; 536 int error; 537 538 sc->sc_clk = fdtbus_clock_get(phandle, "i2s_clk"); 539 if (sc->sc_clk == NULL) { 540 aprint_error(": couldn't find i2s_clk clock\n"); 541 return ENXIO; 542 } 543 error = clk_enable(sc->sc_clk); 544 if (error != 0) { 545 aprint_error(": couldn't enable i2s_clk clock: %d\n", error); 546 return error; 547 } 548 549 /* Enable bus clock */ 550 if (fdtbus_clock_enable(phandle, "i2s_hclk", true) != 0) { 551 aprint_error(": couldn't enable i2s_hclk clock: %d\n", error); 552 return error; 553 } 554 555 return 0; 556 } 557 558 static int 559 rk_i2s_match(device_t parent, cfdata_t cf, void *aux) 560 { 561 struct fdt_attach_args * const faa = aux; 562 563 return of_match_compat_data(faa->faa_phandle, compat_data); 564 } 565 566 static void 567 rk_i2s_attach(device_t parent, device_t self, void *aux) 568 { 569 struct rk_i2s_softc * const sc = device_private(self); 570 struct fdt_attach_args * const faa = aux; 571 const int phandle = faa->faa_phandle; 572 char intrstr[128]; 573 bus_addr_t addr; 574 bus_size_t size; 575 uint32_t val; 576 577 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 578 aprint_error(": couldn't get registers\n"); 579 return; 580 } 581 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 582 aprint_error(": couldn't decode interrupt\n"); 583 return; 584 } 585 586 sc->sc_dev = self; 587 sc->sc_phandle = phandle; 588 sc->sc_bst = faa->faa_bst; 589 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 590 aprint_error(": couldn't map registers\n"); 591 return; 592 } 593 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 594 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 595 596 sc->sc_conf = (void *)of_search_compatible(phandle, compat_data)->data; 597 sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 598 if (sc->sc_grf != NULL && sc->sc_conf->oe_mask != 0) { 599 syscon_lock(sc->sc_grf); 600 val = __SHIFTIN(sc->sc_conf->oe_val, sc->sc_conf->oe_mask); 601 val |= (sc->sc_conf->oe_mask << 16); 602 syscon_write_4(sc->sc_grf, sc->sc_conf->oe_reg, val); 603 syscon_unlock(sc->sc_grf); 604 } 605 606 if (rk_i2s_clock_init(sc) != 0) 607 return; 608 609 aprint_naive("\n"); 610 aprint_normal(": I2S/PCM controller\n"); 611 612 if (fdtbus_intr_establish(phandle, 0, IPL_AUDIO, FDT_INTR_MPSAFE, rk_i2s_intr, sc) == NULL) { 613 aprint_error_dev(self, "couldn't establish interrupt on %s\n", intrstr); 614 return; 615 } 616 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 617 618 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 619 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 620 sc->sc_format.validbits = 16; 621 sc->sc_format.precision = 16; 622 sc->sc_format.channels = 2; 623 sc->sc_format.channel_mask = AUFMT_STEREO; 624 sc->sc_format.frequency_type = 1; 625 sc->sc_format.frequency[0] = RK_I2S_SAMPLE_RATE; 626 627 sc->sc_dai.dai_set_sysclk = rk_i2s_dai_set_sysclk; 628 sc->sc_dai.dai_set_format = rk_i2s_dai_set_format; 629 sc->sc_dai.dai_hw_if = &rk_i2s_hw_if; 630 sc->sc_dai.dai_dev = self; 631 sc->sc_dai.dai_priv = sc; 632 fdtbus_register_dai_controller(self, phandle, &rk_i2s_dai_funcs); 633 } 634 635 CFATTACH_DECL_NEW(rk_i2s, sizeof(struct rk_i2s_softc), 636 rk_i2s_match, rk_i2s_attach, NULL, NULL); 637
Indexes created Wed Oct 01 19:09:53 GMT 2025