rk_pwm.c revision 1.4
1 /* $NetBSD: rk_pwm.c,v 1.4 2021/01/18 02:35:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk_pwm.c,v 1.4 2021/01/18 02:35:49 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/pwm/pwmvar.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #define PWM0_CNT 0x00 45 #define PWM0_PERIOD_HPR 0x04 46 #define PWM0_DUTY_LPR 0x08 47 #define PWM0_CTRL 0x0c 48 #define CTRL_RPT __BITS(31,24) 49 #define CTRL_SCALE __BITS(23,16) 50 #define CTRL_PRESCALE __BITS(14,12) 51 #define CTRL_CLK_SEL __BIT(9) 52 #define CTRL_LP_EN __BIT(8) 53 #define CTRL_OUTPUT_MODE __BIT(5) 54 #define CTRL_INACTIVE_POL __BIT(4) 55 #define CTRL_DUTY_POL __BIT(3) 56 #define CTRL_PWM_MODE __BITS(2,1) 57 #define CTRL_PWM_MODE_ONESHOT 0 58 #define CTRL_PWM_MODE_CONTINUOUS 1 59 #define CTRL_PWM_MODE_CAPTURE 2 60 #define CTRL_PWM_EN __BIT(0) 61 62 enum rk_pwm_type { 63 PWM_RK3288 = 1, 64 }; 65 66 static const struct device_compatible_entry compat_data[] = { 67 { .compat = "rockchip,rk3288-pwm", .value = PWM_RK3288 }, 68 69 { 0 } 70 }; 71 72 struct rk_pwm_softc { 73 device_t sc_dev; 74 bus_space_tag_t sc_bst; 75 bus_space_handle_t sc_bsh; 76 77 struct pwm_controller sc_pwm; 78 struct pwm_config sc_conf; 79 80 u_int sc_clkfreq; 81 }; 82 83 #define PWM_READ(sc, reg) \ 84 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 85 #define PWM_WRITE(sc, reg, val) \ 86 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 87 88 static pwm_tag_t 89 rk_pwm_get_tag(device_t dev, const void *data, size_t len) 90 { 91 struct rk_pwm_softc * const sc = device_private(dev); 92 const u_int *pwm = data; 93 94 if (len != 16) 95 return NULL; 96 97 const u_int index = be32toh(pwm[1]); 98 if (index != 0) 99 return NULL; 100 101 const u_int period = be32toh(pwm[2]); 102 const u_int polarity = be32toh(pwm[3]); 103 104 sc->sc_conf.period = period; 105 sc->sc_conf.polarity = polarity ? PWM_ACTIVE_LOW : PWM_ACTIVE_HIGH; 106 107 return &sc->sc_pwm; 108 } 109 110 static struct fdtbus_pwm_controller_func rk_pwm_funcs = { 111 .get_tag = rk_pwm_get_tag 112 }; 113 114 static int 115 rk_pwm_enable(pwm_tag_t pwm, bool enable) 116 { 117 struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev); 118 uint32_t ctrl, octrl; 119 120 octrl = ctrl = PWM_READ(sc, PWM0_CTRL); 121 if (enable) 122 ctrl |= CTRL_PWM_EN; 123 else 124 ctrl &= ~CTRL_PWM_EN; 125 126 if (ctrl != octrl) 127 PWM_WRITE(sc, PWM0_CTRL, ctrl); 128 129 return 0; 130 } 131 132 static int 133 rk_pwm_get_config(pwm_tag_t pwm, struct pwm_config *conf) 134 { 135 struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev); 136 137 #if 0 138 /* XXX may be useful someday */ 139 140 uint32_t ctrl, period, duty; 141 u_int div; 142 143 ctrl = PWM_READ(sc, PWM0_CTRL); 144 period = PWM_READ(sc, PWM0_PERIOD_HPR); 145 duty = PWM_READ(sc, PWM0_DUTY_LPR); 146 147 if (ctrl & CTRL_CLK_SEL) { 148 div = __SHIFTOUT(ctrl, CTRL_SCALE) * 2; 149 if (div == 0) 150 div = 512; 151 } else { 152 div = 1; 153 } 154 div /= (1 << __SHIFTOUT(ctrl, CTRL_PRESCALE)); 155 156 const uint64_t rate = sc->sc_clkfreq / div; 157 158 conf->polarity = (ctrl & CTRL_DUTY_POL) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW; 159 conf->period = (u_int)(((uint64_t)period * 1000000000) / rate); 160 conf->duty_cycle = (u_int)(((uint64_t)duty * 1000000000) / rate); 161 #else 162 *conf = sc->sc_conf; 163 #endif 164 165 return 0; 166 } 167 168 static int 169 rk_pwm_set_config(pwm_tag_t pwm, const struct pwm_config *conf) 170 { 171 struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev); 172 uint32_t ctrl; 173 174 const uint64_t rate = sc->sc_clkfreq; 175 const uint32_t period = (u_int)((conf->period * rate) / 1000000000); 176 const uint32_t duty = (u_int)((conf->duty_cycle * rate) / 1000000000); 177 178 /* Preserve PWM_EN flag */ 179 ctrl = PWM_READ(sc, PWM0_CTRL) & CTRL_PWM_EN; 180 181 ctrl |= __SHIFTIN(CTRL_PWM_MODE_CONTINUOUS, CTRL_PWM_MODE); 182 if (conf->polarity == PWM_ACTIVE_HIGH) 183 ctrl |= CTRL_DUTY_POL; 184 else 185 ctrl |= CTRL_INACTIVE_POL; 186 187 PWM_WRITE(sc, PWM0_CTRL, 0); 188 PWM_WRITE(sc, PWM0_PERIOD_HPR, period); 189 PWM_WRITE(sc, PWM0_DUTY_LPR, duty); 190 PWM_WRITE(sc, PWM0_CTRL, ctrl); 191 192 sc->sc_conf = *conf; 193 194 return 0; 195 } 196 197 static int 198 rk_pwm_match(device_t parent, cfdata_t cf, void *aux) 199 { 200 struct fdt_attach_args * const faa = aux; 201 202 return of_match_compat_data(faa->faa_phandle, compat_data); 203 } 204 205 static void 206 rk_pwm_attach(device_t parent, device_t self, void *aux) 207 { 208 struct rk_pwm_softc * const sc = device_private(self); 209 struct fdt_attach_args * const faa = aux; 210 const int phandle = faa->faa_phandle; 211 struct clk *clk; 212 bus_addr_t addr; 213 bus_size_t size; 214 int error; 215 216 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 217 aprint_error(": couldn't get registers\n"); 218 return; 219 } 220 221 clk = fdtbus_clock_get_index(phandle, 0); 222 if (clk == NULL) { 223 aprint_error(": couldn't get clock\n"); 224 return; 225 } 226 227 sc->sc_dev = self; 228 sc->sc_clkfreq = clk_get_rate(clk); 229 sc->sc_bst = faa->faa_bst; 230 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 231 if (error) { 232 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 233 addr, error); 234 return; 235 } 236 237 aprint_naive("\n"); 238 aprint_normal(": PWM\n"); 239 240 sc->sc_pwm.pwm_enable = rk_pwm_enable; 241 sc->sc_pwm.pwm_get_config = rk_pwm_get_config; 242 sc->sc_pwm.pwm_set_config = rk_pwm_set_config; 243 sc->sc_pwm.pwm_dev = self; 244 245 fdtbus_register_pwm_controller(self, phandle, 246 &rk_pwm_funcs); 247 } 248 249 CFATTACH_DECL_NEW(rk_pwm, sizeof(struct rk_pwm_softc), 250 rk_pwm_match, rk_pwm_attach, NULL, NULL); 251
Indexes created Thu Oct 02 01:09:59 GMT 2025