rk_spi.c revision 1.1
1 /* $NetBSD: rk_spi.c,v 1.1 2019/08/05 15:22:59 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tobias Nygren. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: rk_spi.c,v 1.1 2019/08/05 15:22:59 tnn Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/bitops.h> 42 #include <dev/spi/spivar.h> 43 #include <dev/fdt/fdtvar.h> 44 #include <arm/fdt/arm_fdtvar.h> 45 46 #define SPI_CTRLR0 0x00 47 #define SPI_CTRLR0_MTM __BIT(21) 48 #define SPI_CTRLR0_OPM __BIT(20) 49 #define SPI_CTRLR0_XFM __BITS(19, 18) 50 #define SPI_CTRLR0_FRF __BITS(17, 16) 51 #define SPI_CTRLR0_RSD __BITS(15, 14) 52 #define SPI_CTRLR0_BHT __BIT(13) 53 #define SPI_CTRLR0_FBM __BIT(12) 54 #define SPI_CTRLR0_EM __BIT(11) 55 #define SPI_CTRLR0_RW __BIT(10) 56 #define SPI_CTRLR0_CSM __BITS(9, 8) 57 #define SPI_CTRLR0_SCPOL __BIT(7) 58 #define SPI_CTRLR0_SCPH __BIT(6) 59 #define SPI_CTRLR0_CFS __BITS(5, 2) 60 #define SPI_CTRLR0_DFS __BITS(1, 0) 61 #define SPI_CTRLR0_DFS_4BIT 0x0 62 #define SPI_CTRLR0_DFS_8BIT 0x1 63 #define SPI_CTRLR0_DFS_16BIT 0x2 64 65 #define SPI_CTRLR1 0x04 66 #define SPI_CTRLR1_NDM __BITS(15, 0) 67 68 #define SPI_ENR 0x08 69 #define SPI_ENR_ENR __BIT(0) 70 71 #define SPI_SER 0x0c 72 #define SPI_SER_SER1 __BIT(1) 73 #define SPI_SER_SER0 __BIT(0) 74 75 #define SPI_BAUDR 0x10 76 #define SPI_BAUDR_BAUDR __BITS(15, 0) 77 78 #define SPI_TXFTLR 0x14 79 #define SPI_TXFTLR_TXFLTR __BITS(4, 0) 80 81 #define SPI_RXFTLR 0x18 82 #define SPI_RXFLTR_RXFLTR __BITS(4, 0) 83 84 #define SPI_TXFLR 0x1c 85 #define SPI_TXFLR_TXFLR __BITS(5, 0) 86 87 #define SPI_RXFLR 0x20 88 #define SPI_RXFLR_RXFLR __BITS(5, 0) 89 90 #define SPI_SR 0x24 91 #define SPI_SR_RFF __BIT(4) 92 #define SPI_SR_RFE __BIT(3) 93 #define SPI_SR_TFE __BIT(2) 94 #define SPI_SR_TFF __BIT(1) 95 #define SPI_SR_BSF __BIT(0) 96 97 #define SPI_IPR 0x28 98 #define SPI_IPR_IPR __BIT(0) 99 100 #define SPI_IMR 0x2c 101 #define SPI_IMR_RFFIM __BIT(4) 102 #define SPI_IMR_RFOIM __BIT(3) 103 #define SPI_IMR_RFUIM __BIT(2) 104 #define SPI_IMR_TFOIM __BIT(1) 105 #define SPI_IMR_TFEIM __BIT(0) 106 107 #define SPI_ISR 0x30 108 #define SPI_ISR_RFFIS __BIT(4) 109 #define SPI_ISR_RFOIS __BIT(3) 110 #define SPI_ISR_RFUIS __BIT(2) 111 #define SPI_ISR_TFOIS __BIT(1) 112 #define SPI_ISR_TFEIS __BIT(0) 113 114 #define SPI_RISR 0x34 115 #define SPI_RISR_RFFRIS __BIT(4) 116 #define SPI_RISR_RFORIS __BIT(3) 117 #define SPI_RISR_RFURIS __BIT(2) 118 #define SPI_RISR_TFORIS __BIT(1) 119 #define SPI_RISR_TFERIS __BIT(0) 120 121 #define SPI_ICR 0x38 122 #define SPI_ICR_CTFOI __BIT(3) 123 #define SPI_ICR_CRFOI __BIT(2) 124 #define SPI_ICR_CRFUI __BIT(1) 125 #define SPI_ICR_CCI __BIT(0) 126 #define SPI_ICR_ALL __BITS(3, 0) 127 128 #define SPI_DMACR 0x3c 129 #define SPI_DMACR_TDE __BIT(1) 130 #define SPI_DMACR_RDE __BIT(0) 131 132 #define SPI_DMATDLR 0x40 133 #define SPI_DMATDLR_TDL __BITS(4, 0) 134 135 #define SPI_DMARDLR 0x44 136 #define SPI_DMARDLR_RDL __BITS(4, 0) 137 138 #define SPI_TXDR 0x400 139 #define SPI_TXDR_TXDR __BITS(15, 0) 140 141 #define SPI_RXDR 0x800 142 #define SPI_RXDR_RXDR __BITS(15, 0) 143 144 #define SPI_FIFOLEN 32 145 146 static const char * const compatible[] = { 147 #if 0 /* should work on RK3328 but untested */ 148 "rockchip,rk3066-spi", 149 "rockchip,rk3328-spi", 150 #endif 151 "rockchip,rk3399-spi", 152 NULL 153 }; 154 155 struct rk_spi_softc { 156 device_t sc_dev; 157 bus_space_tag_t sc_bst; 158 bus_space_handle_t sc_bsh; 159 void *sc_ih; 160 u_int sc_spi_freq; 161 struct spi_controller sc_spi; 162 SIMPLEQ_HEAD(,spi_transfer) sc_q; 163 struct spi_transfer *sc_transfer; 164 struct spi_chunk *sc_rchunk, *sc_wchunk; 165 volatile bool sc_running; 166 }; 167 168 #define SPIREG_READ(sc, reg) \ 169 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 170 #define SPIREG_WRITE(sc, reg, val) \ 171 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 172 173 static int rk_spi_match(device_t, cfdata_t, void *); 174 static void rk_spi_attach(device_t, device_t, void *); 175 176 static int rk_spi_configure(void *, int, int, int); 177 static int rk_spi_transfer(void *, struct spi_transfer *); 178 179 static void rk_spi_txfifo_fill(struct rk_spi_softc * const, size_t); 180 static void rk_spi_rxfifo_drain(struct rk_spi_softc * const, size_t); 181 static void rk_spi_rxtx(struct rk_spi_softc * const); 182 static void rk_spi_set_interrupt_mask(struct rk_spi_softc * const); 183 static void rk_spi_start(struct rk_spi_softc * const); 184 static int rk_spi_intr(void *); 185 186 CFATTACH_DECL_NEW(rk_spi, sizeof(struct rk_spi_softc), 187 rk_spi_match, rk_spi_attach, NULL, NULL); 188 189 static int 190 rk_spi_match(device_t parent, cfdata_t cf, void *aux) 191 { 192 struct fdt_attach_args * const faa = aux; 193 194 return of_match_compatible(faa->faa_phandle, compatible); 195 } 196 197 static void 198 rk_spi_attach(device_t parent, device_t self, void *aux) 199 { 200 struct rk_spi_softc * const sc = device_private(self); 201 struct fdt_attach_args * const faa = aux; 202 const int phandle = faa->faa_phandle; 203 bus_addr_t addr; 204 bus_size_t size; 205 struct clk *sclk, *pclk; 206 char intrstr[128]; 207 struct spibus_attach_args sba; 208 209 sc->sc_dev = self; 210 sc->sc_bst = faa->faa_bst; 211 SIMPLEQ_INIT(&sc->sc_q); 212 213 if ((sclk = fdtbus_clock_get(phandle, "spiclk")) == NULL 214 || clk_enable(sclk) != 0) { 215 aprint_error(": couldn't enable sclk\n"); 216 return; 217 } 218 219 if ((pclk = fdtbus_clock_get(phandle, "apb_pclk")) == NULL 220 || clk_enable(pclk) != 0) { 221 aprint_error(": couldn't enable pclk\n"); 222 return; 223 } 224 225 sc->sc_spi_freq = clk_get_rate(sclk); 226 227 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 228 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 229 aprint_error(": couldn't map registers\n"); 230 return; 231 } 232 233 SPIREG_WRITE(sc, SPI_ENR, 0); 234 SPIREG_WRITE(sc, SPI_IMR, 0); 235 236 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 237 aprint_error(": failed to decode interrupt\n"); 238 return; 239 } 240 241 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, rk_spi_intr, sc); 242 if (sc->sc_ih == NULL) { 243 aprint_error(": unable to establish interrupt\n"); 244 return; 245 } 246 247 aprint_naive("\n"); 248 aprint_normal(": SPI\n"); 249 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 250 251 sc->sc_spi.sct_cookie = sc; 252 sc->sc_spi.sct_configure = rk_spi_configure; 253 sc->sc_spi.sct_transfer = rk_spi_transfer; 254 sc->sc_spi.sct_nslaves = 2; 255 256 sba.sba_controller = &sc->sc_spi; 257 258 (void) config_found_ia(self, "spibus", &sba, spibus_print); 259 } 260 261 static int 262 rk_spi_configure(void *cookie, int slave, int mode, int speed) 263 { 264 struct rk_spi_softc * const sc = cookie; 265 uint32_t ctrlr0; 266 uint16_t divider; 267 268 divider = (sc->sc_spi_freq / speed) & ~1; 269 if (divider < 2) 270 return EINVAL; 271 272 if (slave >= sc->sc_spi.sct_nslaves) 273 return EINVAL; 274 275 ctrlr0 = SPI_CTRLR0_BHT | __SHIFTIN(SPI_CTRLR0_DFS_8BIT, SPI_CTRLR0_DFS); 276 277 switch (mode) { 278 case SPI_MODE_0: 279 ctrlr0 |= 0; 280 break; 281 case SPI_MODE_1: 282 ctrlr0 |= SPI_CTRLR0_SCPH; 283 break; 284 case SPI_MODE_2: 285 ctrlr0 |= SPI_CTRLR0_SCPOL; 286 break; 287 case SPI_MODE_3: 288 ctrlr0 |= SPI_CTRLR0_SCPH | SPI_CTRLR0_SCPOL; 289 break; 290 default: 291 return EINVAL; 292 } 293 294 SPIREG_WRITE(sc, SPI_ENR, 0); 295 SPIREG_WRITE(sc, SPI_SER, 0); 296 SPIREG_WRITE(sc, SPI_CTRLR0, ctrlr0); 297 SPIREG_WRITE(sc, SPI_BAUDR, divider); 298 299 SPIREG_WRITE(sc, SPI_DMACR, 0); 300 SPIREG_WRITE(sc, SPI_DMATDLR, 0); 301 SPIREG_WRITE(sc, SPI_DMARDLR, 0); 302 303 SPIREG_WRITE(sc, SPI_IPR, 0); 304 SPIREG_WRITE(sc, SPI_IMR, 0); 305 SPIREG_WRITE(sc, SPI_ICR, SPI_ICR_ALL); 306 307 SPIREG_WRITE(sc, SPI_ENR, 1); 308 309 return 0; 310 } 311 312 static int 313 rk_spi_transfer(void *cookie, struct spi_transfer *st) 314 { 315 struct rk_spi_softc * const sc = cookie; 316 int s; 317 318 s = splbio(); 319 spi_transq_enqueue(&sc->sc_q, st); 320 if (sc->sc_running == false) { 321 rk_spi_start(sc); 322 } 323 splx(s); 324 325 return 0; 326 } 327 328 static void 329 rk_spi_txfifo_fill(struct rk_spi_softc * const sc, size_t maxlen) 330 { 331 struct spi_chunk *chunk = sc->sc_wchunk; 332 size_t len; 333 uint8_t b; 334 335 if (chunk == NULL) 336 return; 337 338 len = MIN(maxlen, chunk->chunk_wresid); 339 chunk->chunk_wresid -= len; 340 while (len--) { 341 if (chunk->chunk_wptr) { 342 b = *chunk->chunk_wptr++; 343 } else { 344 b = 0; 345 } 346 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDR, b); 347 } 348 if (sc->sc_wchunk->chunk_wresid == 0) { 349 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 350 } 351 } 352 353 static void 354 rk_spi_rxfifo_drain(struct rk_spi_softc * const sc, size_t maxlen) 355 { 356 struct spi_chunk *chunk = sc->sc_rchunk; 357 size_t len; 358 uint8_t b; 359 360 if (chunk == NULL) 361 return; 362 363 len = MIN(maxlen, chunk->chunk_rresid); 364 chunk->chunk_rresid -= len; 365 366 while (len--) { 367 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDR); 368 if (chunk->chunk_rptr) { 369 *chunk->chunk_rptr++ = b; 370 } 371 } 372 if (sc->sc_rchunk->chunk_rresid == 0) { 373 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 374 } 375 } 376 377 static void 378 rk_spi_rxtx(struct rk_spi_softc * const sc) 379 { 380 bool again; 381 uint32_t reg; 382 size_t avail; 383 384 /* Service both FIFOs until no more progress can be made. */ 385 again = true; 386 while (again) { 387 again = false; 388 reg = SPIREG_READ(sc, SPI_RXFLR); 389 avail = __SHIFTOUT(reg, SPI_RXFLR_RXFLR); 390 if (avail > 0) { 391 KASSERT(sc->sc_rchunk != NULL); 392 rk_spi_rxfifo_drain(sc, avail); 393 again = true; 394 } 395 reg = SPIREG_READ(sc, SPI_TXFLR); 396 avail = SPI_FIFOLEN - __SHIFTOUT(reg, SPI_TXFLR_TXFLR); 397 if (avail > 0 && sc->sc_wchunk != NULL) { 398 rk_spi_txfifo_fill(sc, avail); 399 again = true; 400 } 401 } 402 } 403 404 static void 405 rk_spi_set_interrupt_mask(struct rk_spi_softc * const sc) 406 { 407 uint32_t imr = SPI_IMR_RFOIM | SPI_IMR_RFUIM | SPI_IMR_TFOIM; 408 int len; 409 410 /* 411 * Delay rx interrupts until the FIFO has the # of bytes we'd 412 * ideally like to receive, or FIFO is half full. 413 */ 414 len = sc->sc_rchunk != NULL 415 ? MIN(sc->sc_rchunk->chunk_rresid, SPI_FIFOLEN / 2) : 0; 416 if (len > 0) { 417 SPIREG_WRITE(sc, SPI_RXFTLR, len - 1); 418 imr |= SPI_IMR_RFFIM; 419 } 420 421 /* 422 * Delay tx interrupts until the FIFO can accept the # of bytes we'd 423 * ideally like to transmit, or the FIFO is half empty. 424 */ 425 len = sc->sc_wchunk != NULL 426 ? MIN(sc->sc_wchunk->chunk_wresid, SPI_FIFOLEN / 2) : 0; 427 if (len > 0) { 428 SPIREG_WRITE(sc, SPI_TXFTLR, SPI_FIFOLEN - len); 429 imr |= SPI_IMR_TFEIM; 430 } 431 432 /* If xfer is done, then interrupt as soon as the tx fifo is empty. */ 433 if (!ISSET(imr, (SPI_IMR_RFFIM | SPI_IMR_TFEIM))) { 434 SPIREG_WRITE(sc, SPI_TXFTLR, 0); 435 imr |= SPI_IMR_TFEIM; 436 } 437 438 SPIREG_WRITE(sc, SPI_IMR, imr); 439 } 440 441 static void 442 rk_spi_start(struct rk_spi_softc * const sc) 443 { 444 struct spi_transfer *st; 445 446 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 447 spi_transq_dequeue(&sc->sc_q); 448 KASSERT(sc->sc_transfer == NULL); 449 sc->sc_transfer = st; 450 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 451 sc->sc_running = true; 452 453 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves); 454 SPIREG_WRITE(sc, SPI_SER, 1 << st->st_slave); 455 456 rk_spi_rxtx(sc); 457 rk_spi_set_interrupt_mask(sc); 458 459 if (!cold) 460 return; 461 462 for (;;) { 463 (void) rk_spi_intr(sc); 464 if (ISSET(st->st_flags, SPI_F_DONE)) 465 break; 466 } 467 } 468 sc->sc_running = false; 469 } 470 471 static int 472 rk_spi_intr(void *cookie) 473 { 474 struct rk_spi_softc * const sc = cookie; 475 struct spi_transfer *st; 476 uint32_t isr; 477 uint32_t sr; 478 uint32_t icr = SPI_ICR_CCI; 479 480 isr = SPIREG_READ(sc, SPI_ISR); 481 if (!isr) 482 return 0; 483 484 if (ISSET(isr, SPI_ISR_RFOIS)) { 485 device_printf(sc->sc_dev, "RXFIFO overflow\n"); 486 icr |= SPI_ICR_CRFOI; 487 } 488 if (ISSET(isr, SPI_ISR_RFUIS)) { 489 device_printf(sc->sc_dev, "RXFIFO underflow\n"); 490 icr |= SPI_ICR_CRFUI; 491 } 492 if (ISSET(isr, SPI_ISR_TFOIS)) { 493 device_printf(sc->sc_dev, "TXFIFO overflow\n"); 494 icr |= SPI_ICR_CTFOI; 495 } 496 497 rk_spi_rxtx(sc); 498 499 if (sc->sc_rchunk == NULL && sc->sc_wchunk == NULL) { 500 do { 501 sr = SPIREG_READ(sc, SPI_SR); 502 } while (ISSET(sr, SPI_SR_BSF)); 503 SPIREG_WRITE(sc, SPI_IMR, 0); 504 SPIREG_WRITE(sc, SPI_SER, 0); 505 st = sc->sc_transfer; 506 sc->sc_transfer = NULL; 507 KASSERT(st != NULL); 508 spi_done(st, 0); 509 sc->sc_running = false; 510 } else { 511 rk_spi_set_interrupt_mask(sc); 512 } 513 514 SPIREG_WRITE(sc, SPI_ICR, icr); 515 516 return 1; 517 } 518
Indexes created Tue Sep 30 20:09:53 GMT 2025