rk_spi.c revision 1.4
1 /* $NetBSD: rk_spi.c,v 1.4 2020/04/01 20:37:32 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tobias Nygren. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: rk_spi.c,v 1.4 2020/04/01 20:37:32 tnn Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/bitops.h> 42 #include <dev/spi/spivar.h> 43 #include <dev/fdt/fdtvar.h> 44 #include <arm/fdt/arm_fdtvar.h> 45 46 #define SPI_CTRLR0 0x00 47 #define SPI_CTRLR0_MTM __BIT(21) 48 #define SPI_CTRLR0_OPM __BIT(20) 49 #define SPI_CTRLR0_XFM __BITS(19, 18) 50 #define SPI_CTRLR0_FRF __BITS(17, 16) 51 #define SPI_CTRLR0_RSD __BITS(15, 14) 52 #define SPI_CTRLR0_BHT __BIT(13) 53 #define SPI_CTRLR0_FBM __BIT(12) 54 #define SPI_CTRLR0_EM __BIT(11) 55 #define SPI_CTRLR0_RW __BIT(10) 56 #define SPI_CTRLR0_CSM __BITS(9, 8) 57 #define SPI_CTRLR0_SCPOL __BIT(7) 58 #define SPI_CTRLR0_SCPH __BIT(6) 59 #define SPI_CTRLR0_CFS __BITS(5, 2) 60 #define SPI_CTRLR0_DFS __BITS(1, 0) 61 #define SPI_CTRLR0_DFS_4BIT 0x0 62 #define SPI_CTRLR0_DFS_8BIT 0x1 63 #define SPI_CTRLR0_DFS_16BIT 0x2 64 65 #define SPI_CTRLR1 0x04 66 #define SPI_CTRLR1_NDM __BITS(15, 0) 67 68 #define SPI_ENR 0x08 69 #define SPI_ENR_ENR __BIT(0) 70 71 #define SPI_SER 0x0c 72 #define SPI_SER_SER1 __BIT(1) 73 #define SPI_SER_SER0 __BIT(0) 74 75 #define SPI_BAUDR 0x10 76 #define SPI_BAUDR_BAUDR __BITS(15, 0) 77 78 #define SPI_TXFTLR 0x14 79 #define SPI_TXFTLR_TXFLTR __BITS(4, 0) 80 81 #define SPI_RXFTLR 0x18 82 #define SPI_RXFLTR_RXFLTR __BITS(4, 0) 83 84 #define SPI_TXFLR 0x1c 85 #define SPI_TXFLR_TXFLR __BITS(5, 0) 86 87 #define SPI_RXFLR 0x20 88 #define SPI_RXFLR_RXFLR __BITS(5, 0) 89 90 #define SPI_SR 0x24 91 #define SPI_SR_RFF __BIT(4) 92 #define SPI_SR_RFE __BIT(3) 93 #define SPI_SR_TFE __BIT(2) 94 #define SPI_SR_TFF __BIT(1) 95 #define SPI_SR_BSF __BIT(0) 96 97 #define SPI_IPR 0x28 98 #define SPI_IPR_IPR __BIT(0) 99 100 #define SPI_IMR 0x2c 101 #define SPI_IMR_RFFIM __BIT(4) 102 #define SPI_IMR_RFOIM __BIT(3) 103 #define SPI_IMR_RFUIM __BIT(2) 104 #define SPI_IMR_TFOIM __BIT(1) 105 #define SPI_IMR_TFEIM __BIT(0) 106 107 #define SPI_ISR 0x30 108 #define SPI_ISR_RFFIS __BIT(4) 109 #define SPI_ISR_RFOIS __BIT(3) 110 #define SPI_ISR_RFUIS __BIT(2) 111 #define SPI_ISR_TFOIS __BIT(1) 112 #define SPI_ISR_TFEIS __BIT(0) 113 114 #define SPI_RISR 0x34 115 #define SPI_RISR_RFFRIS __BIT(4) 116 #define SPI_RISR_RFORIS __BIT(3) 117 #define SPI_RISR_RFURIS __BIT(2) 118 #define SPI_RISR_TFORIS __BIT(1) 119 #define SPI_RISR_TFERIS __BIT(0) 120 121 #define SPI_ICR 0x38 122 #define SPI_ICR_CTFOI __BIT(3) 123 #define SPI_ICR_CRFOI __BIT(2) 124 #define SPI_ICR_CRFUI __BIT(1) 125 #define SPI_ICR_CCI __BIT(0) 126 #define SPI_ICR_ALL __BITS(3, 0) 127 128 #define SPI_DMACR 0x3c 129 #define SPI_DMACR_TDE __BIT(1) 130 #define SPI_DMACR_RDE __BIT(0) 131 132 #define SPI_DMATDLR 0x40 133 #define SPI_DMATDLR_TDL __BITS(4, 0) 134 135 #define SPI_DMARDLR 0x44 136 #define SPI_DMARDLR_RDL __BITS(4, 0) 137 138 #define SPI_TXDR 0x400 139 #define SPI_TXDR_TXDR __BITS(15, 0) 140 141 #define SPI_RXDR 0x800 142 #define SPI_RXDR_RXDR __BITS(15, 0) 143 144 #define SPI_FIFOLEN 32 145 146 static const char * const compatible[] = { 147 #if 0 /* should work on RK3328 but untested */ 148 "rockchip,rk3066-spi", 149 "rockchip,rk3328-spi", 150 #endif 151 "rockchip,rk3399-spi", 152 NULL 153 }; 154 155 struct rk_spi_softc { 156 device_t sc_dev; 157 bus_space_tag_t sc_bst; 158 bus_space_handle_t sc_bsh; 159 void *sc_ih; 160 u_int sc_spi_freq; 161 struct spi_controller sc_spi; 162 SIMPLEQ_HEAD(,spi_transfer) sc_q; 163 struct spi_transfer *sc_transfer; 164 struct spi_chunk *sc_rchunk, *sc_wchunk; 165 volatile bool sc_running; 166 }; 167 168 #define SPIREG_READ(sc, reg) \ 169 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 170 #define SPIREG_WRITE(sc, reg, val) \ 171 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 172 173 static struct spi_controller *rk_spi_get_controller(device_t); 174 static int rk_spi_match(device_t, cfdata_t, void *); 175 static void rk_spi_attach(device_t, device_t, void *); 176 177 static int rk_spi_configure(void *, int, int, int); 178 static int rk_spi_transfer(void *, struct spi_transfer *); 179 180 static void rk_spi_txfifo_fill(struct rk_spi_softc * const, size_t); 181 static void rk_spi_rxfifo_drain(struct rk_spi_softc * const, size_t); 182 static void rk_spi_rxtx(struct rk_spi_softc * const); 183 static void rk_spi_set_interrupt_mask(struct rk_spi_softc * const); 184 static void rk_spi_start(struct rk_spi_softc * const); 185 static int rk_spi_intr(void *); 186 187 CFATTACH_DECL_NEW(rk_spi, sizeof(struct rk_spi_softc), 188 rk_spi_match, rk_spi_attach, NULL, NULL); 189 190 static const struct fdtbus_spi_controller_func rk_spi_funcs = { 191 .get_controller = rk_spi_get_controller 192 }; 193 194 static struct spi_controller * 195 rk_spi_get_controller(device_t dev) 196 { 197 struct rk_spi_softc * const sc = device_private(dev); 198 199 return &sc->sc_spi; 200 } 201 202 static int 203 rk_spi_match(device_t parent, cfdata_t cf, void *aux) 204 { 205 struct fdt_attach_args * const faa = aux; 206 207 return of_match_compatible(faa->faa_phandle, compatible); 208 } 209 210 static void 211 rk_spi_attach(device_t parent, device_t self, void *aux) 212 { 213 struct rk_spi_softc * const sc = device_private(self); 214 struct fdt_attach_args * const faa = aux; 215 const int phandle = faa->faa_phandle; 216 bus_addr_t addr; 217 bus_size_t size; 218 struct clk *sclk, *pclk; 219 char intrstr[128]; 220 221 sc->sc_dev = self; 222 sc->sc_bst = faa->faa_bst; 223 SIMPLEQ_INIT(&sc->sc_q); 224 225 if ((sclk = fdtbus_clock_get(phandle, "spiclk")) == NULL 226 || clk_enable(sclk) != 0) { 227 aprint_error(": couldn't enable sclk\n"); 228 return; 229 } 230 231 if ((pclk = fdtbus_clock_get(phandle, "apb_pclk")) == NULL 232 || clk_enable(pclk) != 0) { 233 aprint_error(": couldn't enable pclk\n"); 234 return; 235 } 236 237 sc->sc_spi_freq = clk_get_rate(sclk); 238 239 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 240 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 241 aprint_error(": couldn't map registers\n"); 242 return; 243 } 244 245 SPIREG_WRITE(sc, SPI_ENR, 0); 246 SPIREG_WRITE(sc, SPI_IMR, 0); 247 248 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 249 aprint_error(": failed to decode interrupt\n"); 250 return; 251 } 252 253 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, rk_spi_intr, sc); 254 if (sc->sc_ih == NULL) { 255 aprint_error(": unable to establish interrupt\n"); 256 return; 257 } 258 259 aprint_naive("\n"); 260 aprint_normal(": SPI\n"); 261 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 262 263 sc->sc_spi.sct_cookie = sc; 264 sc->sc_spi.sct_configure = rk_spi_configure; 265 sc->sc_spi.sct_transfer = rk_spi_transfer; 266 sc->sc_spi.sct_nslaves = 2; 267 268 fdtbus_register_spi_controller(self, phandle, &rk_spi_funcs); 269 (void) fdtbus_attach_spibus(self, phandle, spibus_print); 270 } 271 272 static int 273 rk_spi_configure(void *cookie, int slave, int mode, int speed) 274 { 275 struct rk_spi_softc * const sc = cookie; 276 uint32_t ctrlr0; 277 uint16_t divider; 278 279 divider = (sc->sc_spi_freq / speed) & ~1; 280 if (divider < 2) { 281 aprint_error_dev(sc->sc_dev, 282 "spi_clk %u is too low for speed %u, using speed %u\n", 283 sc->sc_spi_freq, speed, sc->sc_spi_freq / 2); 284 divider = 2; 285 } 286 287 if (slave >= sc->sc_spi.sct_nslaves) 288 return EINVAL; 289 290 ctrlr0 = SPI_CTRLR0_BHT | __SHIFTIN(SPI_CTRLR0_DFS_8BIT, SPI_CTRLR0_DFS); 291 292 switch (mode) { 293 case SPI_MODE_0: 294 ctrlr0 |= 0; 295 break; 296 case SPI_MODE_1: 297 ctrlr0 |= SPI_CTRLR0_SCPH; 298 break; 299 case SPI_MODE_2: 300 ctrlr0 |= SPI_CTRLR0_SCPOL; 301 break; 302 case SPI_MODE_3: 303 ctrlr0 |= SPI_CTRLR0_SCPH | SPI_CTRLR0_SCPOL; 304 break; 305 default: 306 return EINVAL; 307 } 308 309 SPIREG_WRITE(sc, SPI_ENR, 0); 310 SPIREG_WRITE(sc, SPI_SER, 0); 311 SPIREG_WRITE(sc, SPI_CTRLR0, ctrlr0); 312 SPIREG_WRITE(sc, SPI_BAUDR, divider); 313 314 SPIREG_WRITE(sc, SPI_DMACR, 0); 315 SPIREG_WRITE(sc, SPI_DMATDLR, 0); 316 SPIREG_WRITE(sc, SPI_DMARDLR, 0); 317 318 SPIREG_WRITE(sc, SPI_IPR, 0); 319 SPIREG_WRITE(sc, SPI_IMR, 0); 320 SPIREG_WRITE(sc, SPI_ICR, SPI_ICR_ALL); 321 322 SPIREG_WRITE(sc, SPI_ENR, 1); 323 324 return 0; 325 } 326 327 static int 328 rk_spi_transfer(void *cookie, struct spi_transfer *st) 329 { 330 struct rk_spi_softc * const sc = cookie; 331 int s; 332 333 s = splbio(); 334 spi_transq_enqueue(&sc->sc_q, st); 335 if (sc->sc_running == false) { 336 rk_spi_start(sc); 337 } 338 splx(s); 339 340 return 0; 341 } 342 343 static void 344 rk_spi_txfifo_fill(struct rk_spi_softc * const sc, size_t maxlen) 345 { 346 struct spi_chunk *chunk = sc->sc_wchunk; 347 size_t len; 348 uint8_t b; 349 350 if (chunk == NULL) 351 return; 352 353 len = MIN(maxlen, chunk->chunk_wresid); 354 chunk->chunk_wresid -= len; 355 while (len--) { 356 if (chunk->chunk_wptr) { 357 b = *chunk->chunk_wptr++; 358 } else { 359 b = 0; 360 } 361 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDR, b); 362 } 363 if (sc->sc_wchunk->chunk_wresid == 0) { 364 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 365 } 366 } 367 368 static void 369 rk_spi_rxfifo_drain(struct rk_spi_softc * const sc, size_t maxlen) 370 { 371 struct spi_chunk *chunk = sc->sc_rchunk; 372 size_t len; 373 uint8_t b; 374 375 if (chunk == NULL) 376 return; 377 378 len = MIN(maxlen, chunk->chunk_rresid); 379 chunk->chunk_rresid -= len; 380 381 while (len--) { 382 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDR); 383 if (chunk->chunk_rptr) { 384 *chunk->chunk_rptr++ = b; 385 } 386 } 387 if (sc->sc_rchunk->chunk_rresid == 0) { 388 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 389 } 390 } 391 392 static void 393 rk_spi_rxtx(struct rk_spi_softc * const sc) 394 { 395 bool again; 396 uint32_t reg; 397 size_t avail; 398 399 /* Service both FIFOs until no more progress can be made. */ 400 again = true; 401 while (again) { 402 again = false; 403 reg = SPIREG_READ(sc, SPI_RXFLR); 404 avail = __SHIFTOUT(reg, SPI_RXFLR_RXFLR); 405 if (avail > 0) { 406 KASSERT(sc->sc_rchunk != NULL); 407 rk_spi_rxfifo_drain(sc, avail); 408 again = true; 409 } 410 reg = SPIREG_READ(sc, SPI_TXFLR); 411 avail = SPI_FIFOLEN - __SHIFTOUT(reg, SPI_TXFLR_TXFLR); 412 if (avail > 0 && sc->sc_wchunk != NULL) { 413 rk_spi_txfifo_fill(sc, avail); 414 again = true; 415 } 416 } 417 } 418 419 static void 420 rk_spi_set_interrupt_mask(struct rk_spi_softc * const sc) 421 { 422 uint32_t imr = SPI_IMR_RFOIM | SPI_IMR_RFUIM | SPI_IMR_TFOIM; 423 int len; 424 425 /* 426 * Delay rx interrupts until the FIFO has the # of bytes we'd 427 * ideally like to receive, or FIFO is half full. 428 */ 429 len = sc->sc_rchunk != NULL 430 ? MIN(sc->sc_rchunk->chunk_rresid, SPI_FIFOLEN / 2) : 0; 431 if (len > 0) { 432 SPIREG_WRITE(sc, SPI_RXFTLR, len - 1); 433 imr |= SPI_IMR_RFFIM; 434 } 435 436 /* 437 * Delay tx interrupts until the FIFO can accept the # of bytes we'd 438 * ideally like to transmit, or the FIFO is half empty. 439 */ 440 len = sc->sc_wchunk != NULL 441 ? MIN(sc->sc_wchunk->chunk_wresid, SPI_FIFOLEN / 2) : 0; 442 if (len > 0) { 443 SPIREG_WRITE(sc, SPI_TXFTLR, SPI_FIFOLEN - len); 444 imr |= SPI_IMR_TFEIM; 445 } 446 447 /* If xfer is done, then interrupt as soon as the tx fifo is empty. */ 448 if (!ISSET(imr, (SPI_IMR_RFFIM | SPI_IMR_TFEIM))) { 449 SPIREG_WRITE(sc, SPI_TXFTLR, 0); 450 imr |= SPI_IMR_TFEIM; 451 } 452 453 SPIREG_WRITE(sc, SPI_IMR, imr); 454 } 455 456 static void 457 rk_spi_start(struct rk_spi_softc * const sc) 458 { 459 struct spi_transfer *st; 460 461 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 462 spi_transq_dequeue(&sc->sc_q); 463 KASSERT(sc->sc_transfer == NULL); 464 sc->sc_transfer = st; 465 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 466 sc->sc_running = true; 467 468 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves); 469 SPIREG_WRITE(sc, SPI_SER, 1 << st->st_slave); 470 471 rk_spi_rxtx(sc); 472 rk_spi_set_interrupt_mask(sc); 473 474 if (!cold) 475 return; 476 477 for (;;) { 478 (void) rk_spi_intr(sc); 479 if (ISSET(st->st_flags, SPI_F_DONE)) 480 break; 481 } 482 } 483 sc->sc_running = false; 484 } 485 486 static int 487 rk_spi_intr(void *cookie) 488 { 489 struct rk_spi_softc * const sc = cookie; 490 struct spi_transfer *st; 491 uint32_t isr; 492 uint32_t sr; 493 uint32_t icr = SPI_ICR_CCI; 494 495 isr = SPIREG_READ(sc, SPI_ISR); 496 if (!isr) 497 return 0; 498 499 if (ISSET(isr, SPI_ISR_RFOIS)) { 500 device_printf(sc->sc_dev, "RXFIFO overflow\n"); 501 icr |= SPI_ICR_CRFOI; 502 } 503 if (ISSET(isr, SPI_ISR_RFUIS)) { 504 device_printf(sc->sc_dev, "RXFIFO underflow\n"); 505 icr |= SPI_ICR_CRFUI; 506 } 507 if (ISSET(isr, SPI_ISR_TFOIS)) { 508 device_printf(sc->sc_dev, "TXFIFO overflow\n"); 509 icr |= SPI_ICR_CTFOI; 510 } 511 512 rk_spi_rxtx(sc); 513 514 if (sc->sc_rchunk == NULL && sc->sc_wchunk == NULL) { 515 do { 516 sr = SPIREG_READ(sc, SPI_SR); 517 } while (ISSET(sr, SPI_SR_BSF)); 518 SPIREG_WRITE(sc, SPI_IMR, 0); 519 SPIREG_WRITE(sc, SPI_SER, 0); 520 st = sc->sc_transfer; 521 sc->sc_transfer = NULL; 522 KASSERT(st != NULL); 523 spi_done(st, 0); 524 sc->sc_running = false; 525 } else { 526 rk_spi_set_interrupt_mask(sc); 527 } 528 529 SPIREG_WRITE(sc, SPI_ICR, icr); 530 531 return 1; 532 } 533
Indexes created Tue Sep 30 20:09:53 GMT 2025