rk_spi.c revision 1.6.4.1
1 /* $NetBSD: rk_spi.c,v 1.6.4.1 2021/05/19 02:58:26 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tobias Nygren. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: rk_spi.c,v 1.6.4.1 2021/05/19 02:58:26 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/bitops.h> 42 #include <dev/spi/spivar.h> 43 #include <dev/fdt/fdtvar.h> 44 #include <arm/fdt/arm_fdtvar.h> 45 46 #define SPI_CTRLR0 0x00 47 #define SPI_CTRLR0_MTM __BIT(21) 48 #define SPI_CTRLR0_OPM __BIT(20) 49 #define SPI_CTRLR0_XFM __BITS(19, 18) 50 #define SPI_CTRLR0_FRF __BITS(17, 16) 51 #define SPI_CTRLR0_RSD __BITS(15, 14) 52 #define SPI_CTRLR0_BHT __BIT(13) 53 #define SPI_CTRLR0_FBM __BIT(12) 54 #define SPI_CTRLR0_EM __BIT(11) 55 #define SPI_CTRLR0_RW __BIT(10) 56 #define SPI_CTRLR0_CSM __BITS(9, 8) 57 #define SPI_CTRLR0_SCPOL __BIT(7) 58 #define SPI_CTRLR0_SCPH __BIT(6) 59 #define SPI_CTRLR0_CFS __BITS(5, 2) 60 #define SPI_CTRLR0_DFS __BITS(1, 0) 61 #define SPI_CTRLR0_DFS_4BIT 0x0 62 #define SPI_CTRLR0_DFS_8BIT 0x1 63 #define SPI_CTRLR0_DFS_16BIT 0x2 64 65 #define SPI_CTRLR1 0x04 66 #define SPI_CTRLR1_NDM __BITS(15, 0) 67 68 #define SPI_ENR 0x08 69 #define SPI_ENR_ENR __BIT(0) 70 71 #define SPI_SER 0x0c 72 #define SPI_SER_SER1 __BIT(1) 73 #define SPI_SER_SER0 __BIT(0) 74 75 #define SPI_BAUDR 0x10 76 #define SPI_BAUDR_BAUDR __BITS(15, 0) 77 78 #define SPI_TXFTLR 0x14 79 #define SPI_TXFTLR_TXFLTR __BITS(4, 0) 80 81 #define SPI_RXFTLR 0x18 82 #define SPI_RXFLTR_RXFLTR __BITS(4, 0) 83 84 #define SPI_TXFLR 0x1c 85 #define SPI_TXFLR_TXFLR __BITS(5, 0) 86 87 #define SPI_RXFLR 0x20 88 #define SPI_RXFLR_RXFLR __BITS(5, 0) 89 90 #define SPI_SR 0x24 91 #define SPI_SR_RFF __BIT(4) 92 #define SPI_SR_RFE __BIT(3) 93 #define SPI_SR_TFE __BIT(2) 94 #define SPI_SR_TFF __BIT(1) 95 #define SPI_SR_BSF __BIT(0) 96 97 #define SPI_IPR 0x28 98 #define SPI_IPR_IPR __BIT(0) 99 100 #define SPI_IMR 0x2c 101 #define SPI_IMR_RFFIM __BIT(4) 102 #define SPI_IMR_RFOIM __BIT(3) 103 #define SPI_IMR_RFUIM __BIT(2) 104 #define SPI_IMR_TFOIM __BIT(1) 105 #define SPI_IMR_TFEIM __BIT(0) 106 107 #define SPI_ISR 0x30 108 #define SPI_ISR_RFFIS __BIT(4) 109 #define SPI_ISR_RFOIS __BIT(3) 110 #define SPI_ISR_RFUIS __BIT(2) 111 #define SPI_ISR_TFOIS __BIT(1) 112 #define SPI_ISR_TFEIS __BIT(0) 113 114 #define SPI_RISR 0x34 115 #define SPI_RISR_RFFRIS __BIT(4) 116 #define SPI_RISR_RFORIS __BIT(3) 117 #define SPI_RISR_RFURIS __BIT(2) 118 #define SPI_RISR_TFORIS __BIT(1) 119 #define SPI_RISR_TFERIS __BIT(0) 120 121 #define SPI_ICR 0x38 122 #define SPI_ICR_CTFOI __BIT(3) 123 #define SPI_ICR_CRFOI __BIT(2) 124 #define SPI_ICR_CRFUI __BIT(1) 125 #define SPI_ICR_CCI __BIT(0) 126 #define SPI_ICR_ALL __BITS(3, 0) 127 128 #define SPI_DMACR 0x3c 129 #define SPI_DMACR_TDE __BIT(1) 130 #define SPI_DMACR_RDE __BIT(0) 131 132 #define SPI_DMATDLR 0x40 133 #define SPI_DMATDLR_TDL __BITS(4, 0) 134 135 #define SPI_DMARDLR 0x44 136 #define SPI_DMARDLR_RDL __BITS(4, 0) 137 138 #define SPI_TXDR 0x400 139 #define SPI_TXDR_TXDR __BITS(15, 0) 140 141 #define SPI_RXDR 0x800 142 #define SPI_RXDR_RXDR __BITS(15, 0) 143 144 #define SPI_FIFOLEN 32 145 146 static const struct device_compatible_entry compat_data[] = { 147 #if 0 /* should work on RK3328 but untested */ 148 { .compat = "rockchip,rk3066-spi" }, 149 { .compat = "rockchip,rk3328-spi" }, 150 #endif 151 { .compat = "rockchip,rk3399-spi" }, 152 DEVICE_COMPAT_EOL 153 }; 154 155 struct rk_spi_softc { 156 device_t sc_dev; 157 bus_space_tag_t sc_bst; 158 bus_space_handle_t sc_bsh; 159 void *sc_ih; 160 u_int sc_spi_freq; 161 struct spi_controller sc_spi; 162 SIMPLEQ_HEAD(,spi_transfer) sc_q; 163 struct spi_transfer *sc_transfer; 164 struct spi_chunk *sc_rchunk, *sc_wchunk; 165 volatile bool sc_running; 166 }; 167 168 #define SPIREG_READ(sc, reg) \ 169 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 170 #define SPIREG_WRITE(sc, reg, val) \ 171 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 172 173 static int rk_spi_match(device_t, cfdata_t, void *); 174 static void rk_spi_attach(device_t, device_t, void *); 175 176 static int rk_spi_configure(void *, int, int, int); 177 static int rk_spi_transfer(void *, struct spi_transfer *); 178 179 static void rk_spi_txfifo_fill(struct rk_spi_softc * const, size_t); 180 static void rk_spi_rxfifo_drain(struct rk_spi_softc * const, size_t); 181 static void rk_spi_rxtx(struct rk_spi_softc * const); 182 static void rk_spi_set_interrupt_mask(struct rk_spi_softc * const); 183 static void rk_spi_start(struct rk_spi_softc * const); 184 static int rk_spi_intr(void *); 185 186 CFATTACH_DECL_NEW(rk_spi, sizeof(struct rk_spi_softc), 187 rk_spi_match, rk_spi_attach, NULL, NULL); 188 189 static int 190 rk_spi_match(device_t parent, cfdata_t cf, void *aux) 191 { 192 struct fdt_attach_args * const faa = aux; 193 194 return of_compatible_match(faa->faa_phandle, compat_data); 195 } 196 197 static void 198 rk_spi_attach(device_t parent, device_t self, void *aux) 199 { 200 struct rk_spi_softc * const sc = device_private(self); 201 struct fdt_attach_args * const faa = aux; 202 const int phandle = faa->faa_phandle; 203 bus_addr_t addr; 204 bus_size_t size; 205 struct clk *sclk, *pclk; 206 char intrstr[128]; 207 208 sc->sc_dev = self; 209 sc->sc_bst = faa->faa_bst; 210 SIMPLEQ_INIT(&sc->sc_q); 211 212 if ((sclk = fdtbus_clock_get(phandle, "spiclk")) == NULL 213 || clk_enable(sclk) != 0) { 214 aprint_error(": couldn't enable sclk\n"); 215 return; 216 } 217 218 if ((pclk = fdtbus_clock_get(phandle, "apb_pclk")) == NULL 219 || clk_enable(pclk) != 0) { 220 aprint_error(": couldn't enable pclk\n"); 221 return; 222 } 223 224 sc->sc_spi_freq = clk_get_rate(sclk); 225 226 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 227 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 228 aprint_error(": couldn't map registers\n"); 229 return; 230 } 231 232 SPIREG_WRITE(sc, SPI_ENR, 0); 233 SPIREG_WRITE(sc, SPI_IMR, 0); 234 235 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 236 aprint_error(": failed to decode interrupt\n"); 237 return; 238 } 239 240 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0, 241 rk_spi_intr, sc, device_xname(self)); 242 if (sc->sc_ih == NULL) { 243 aprint_error(": unable to establish interrupt\n"); 244 return; 245 } 246 247 aprint_naive("\n"); 248 aprint_normal(": SPI\n"); 249 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 250 251 sc->sc_spi.sct_cookie = sc; 252 sc->sc_spi.sct_configure = rk_spi_configure; 253 sc->sc_spi.sct_transfer = rk_spi_transfer; 254 sc->sc_spi.sct_nslaves = 2; 255 256 fdtbus_register_spi_controller(&sc->sc_spi, phandle); 257 258 struct spibus_attach_args sba = { 259 .sba_controller = &sc->sc_spi, 260 }; 261 config_found(self, &sba, spibus_print, 262 CFARG_DEVHANDLE, device_handle(self), 263 CFARG_EOL); 264 } 265 266 static int 267 rk_spi_configure(void *cookie, int slave, int mode, int speed) 268 { 269 struct rk_spi_softc * const sc = cookie; 270 uint32_t ctrlr0; 271 uint16_t divider; 272 273 divider = (sc->sc_spi_freq / speed) & ~1; 274 if (divider < 2) { 275 aprint_error_dev(sc->sc_dev, 276 "spi_clk %u is too low for speed %u, using speed %u\n", 277 sc->sc_spi_freq, speed, sc->sc_spi_freq / 2); 278 divider = 2; 279 } 280 281 if (slave >= sc->sc_spi.sct_nslaves) 282 return EINVAL; 283 284 ctrlr0 = SPI_CTRLR0_BHT | __SHIFTIN(SPI_CTRLR0_DFS_8BIT, SPI_CTRLR0_DFS); 285 286 switch (mode) { 287 case SPI_MODE_0: 288 ctrlr0 |= 0; 289 break; 290 case SPI_MODE_1: 291 ctrlr0 |= SPI_CTRLR0_SCPH; 292 break; 293 case SPI_MODE_2: 294 ctrlr0 |= SPI_CTRLR0_SCPOL; 295 break; 296 case SPI_MODE_3: 297 ctrlr0 |= SPI_CTRLR0_SCPH | SPI_CTRLR0_SCPOL; 298 break; 299 default: 300 return EINVAL; 301 } 302 303 SPIREG_WRITE(sc, SPI_ENR, 0); 304 SPIREG_WRITE(sc, SPI_SER, 0); 305 SPIREG_WRITE(sc, SPI_CTRLR0, ctrlr0); 306 SPIREG_WRITE(sc, SPI_BAUDR, divider); 307 308 SPIREG_WRITE(sc, SPI_DMACR, 0); 309 SPIREG_WRITE(sc, SPI_DMATDLR, 0); 310 SPIREG_WRITE(sc, SPI_DMARDLR, 0); 311 312 SPIREG_WRITE(sc, SPI_IPR, 0); 313 SPIREG_WRITE(sc, SPI_IMR, 0); 314 SPIREG_WRITE(sc, SPI_ICR, SPI_ICR_ALL); 315 316 SPIREG_WRITE(sc, SPI_ENR, 1); 317 318 return 0; 319 } 320 321 static int 322 rk_spi_transfer(void *cookie, struct spi_transfer *st) 323 { 324 struct rk_spi_softc * const sc = cookie; 325 int s; 326 327 s = splbio(); 328 spi_transq_enqueue(&sc->sc_q, st); 329 if (sc->sc_running == false) { 330 rk_spi_start(sc); 331 } 332 splx(s); 333 334 return 0; 335 } 336 337 static void 338 rk_spi_txfifo_fill(struct rk_spi_softc * const sc, size_t maxlen) 339 { 340 struct spi_chunk *chunk = sc->sc_wchunk; 341 size_t len; 342 uint8_t b; 343 344 if (chunk == NULL) 345 return; 346 347 len = MIN(maxlen, chunk->chunk_wresid); 348 chunk->chunk_wresid -= len; 349 while (len--) { 350 if (chunk->chunk_wptr) { 351 b = *chunk->chunk_wptr++; 352 } else { 353 b = 0; 354 } 355 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDR, b); 356 } 357 if (sc->sc_wchunk->chunk_wresid == 0) { 358 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 359 } 360 } 361 362 static void 363 rk_spi_rxfifo_drain(struct rk_spi_softc * const sc, size_t maxlen) 364 { 365 struct spi_chunk *chunk = sc->sc_rchunk; 366 size_t len; 367 uint8_t b; 368 369 if (chunk == NULL) 370 return; 371 372 len = MIN(maxlen, chunk->chunk_rresid); 373 chunk->chunk_rresid -= len; 374 375 while (len--) { 376 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDR); 377 if (chunk->chunk_rptr) { 378 *chunk->chunk_rptr++ = b; 379 } 380 } 381 if (sc->sc_rchunk->chunk_rresid == 0) { 382 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 383 } 384 } 385 386 static void 387 rk_spi_rxtx(struct rk_spi_softc * const sc) 388 { 389 bool again; 390 uint32_t reg; 391 size_t avail; 392 393 /* Service both FIFOs until no more progress can be made. */ 394 again = true; 395 while (again) { 396 again = false; 397 reg = SPIREG_READ(sc, SPI_RXFLR); 398 avail = __SHIFTOUT(reg, SPI_RXFLR_RXFLR); 399 if (avail > 0) { 400 KASSERT(sc->sc_rchunk != NULL); 401 rk_spi_rxfifo_drain(sc, avail); 402 again = true; 403 } 404 reg = SPIREG_READ(sc, SPI_TXFLR); 405 avail = SPI_FIFOLEN - __SHIFTOUT(reg, SPI_TXFLR_TXFLR); 406 if (avail > 0 && sc->sc_wchunk != NULL) { 407 rk_spi_txfifo_fill(sc, avail); 408 again = true; 409 } 410 } 411 } 412 413 static void 414 rk_spi_set_interrupt_mask(struct rk_spi_softc * const sc) 415 { 416 uint32_t imr = SPI_IMR_RFOIM | SPI_IMR_RFUIM | SPI_IMR_TFOIM; 417 int len; 418 419 /* 420 * Delay rx interrupts until the FIFO has the # of bytes we'd 421 * ideally like to receive, or FIFO is half full. 422 */ 423 len = sc->sc_rchunk != NULL 424 ? MIN(sc->sc_rchunk->chunk_rresid, SPI_FIFOLEN / 2) : 0; 425 if (len > 0) { 426 SPIREG_WRITE(sc, SPI_RXFTLR, len - 1); 427 imr |= SPI_IMR_RFFIM; 428 } 429 430 /* 431 * Delay tx interrupts until the FIFO can accept the # of bytes we'd 432 * ideally like to transmit, or the FIFO is half empty. 433 */ 434 len = sc->sc_wchunk != NULL 435 ? MIN(sc->sc_wchunk->chunk_wresid, SPI_FIFOLEN / 2) : 0; 436 if (len > 0) { 437 SPIREG_WRITE(sc, SPI_TXFTLR, SPI_FIFOLEN - len); 438 imr |= SPI_IMR_TFEIM; 439 } 440 441 /* If xfer is done, then interrupt as soon as the tx fifo is empty. */ 442 if (!ISSET(imr, (SPI_IMR_RFFIM | SPI_IMR_TFEIM))) { 443 SPIREG_WRITE(sc, SPI_TXFTLR, 0); 444 imr |= SPI_IMR_TFEIM; 445 } 446 447 SPIREG_WRITE(sc, SPI_IMR, imr); 448 } 449 450 static void 451 rk_spi_start(struct rk_spi_softc * const sc) 452 { 453 struct spi_transfer *st; 454 455 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 456 spi_transq_dequeue(&sc->sc_q); 457 KASSERT(sc->sc_transfer == NULL); 458 sc->sc_transfer = st; 459 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 460 sc->sc_running = true; 461 462 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves); 463 SPIREG_WRITE(sc, SPI_SER, 1 << st->st_slave); 464 465 rk_spi_rxtx(sc); 466 rk_spi_set_interrupt_mask(sc); 467 468 if (!cold) 469 return; 470 471 for (;;) { 472 (void) rk_spi_intr(sc); 473 if (ISSET(st->st_flags, SPI_F_DONE)) 474 break; 475 } 476 } 477 sc->sc_running = false; 478 } 479 480 static int 481 rk_spi_intr(void *cookie) 482 { 483 struct rk_spi_softc * const sc = cookie; 484 struct spi_transfer *st; 485 uint32_t isr; 486 uint32_t sr; 487 uint32_t icr = SPI_ICR_CCI; 488 489 isr = SPIREG_READ(sc, SPI_ISR); 490 if (!isr) 491 return 0; 492 493 if (ISSET(isr, SPI_ISR_RFOIS)) { 494 device_printf(sc->sc_dev, "RXFIFO overflow\n"); 495 icr |= SPI_ICR_CRFOI; 496 } 497 if (ISSET(isr, SPI_ISR_RFUIS)) { 498 device_printf(sc->sc_dev, "RXFIFO underflow\n"); 499 icr |= SPI_ICR_CRFUI; 500 } 501 if (ISSET(isr, SPI_ISR_TFOIS)) { 502 device_printf(sc->sc_dev, "TXFIFO overflow\n"); 503 icr |= SPI_ICR_CTFOI; 504 } 505 506 rk_spi_rxtx(sc); 507 508 if (sc->sc_rchunk == NULL && sc->sc_wchunk == NULL) { 509 do { 510 sr = SPIREG_READ(sc, SPI_SR); 511 } while (ISSET(sr, SPI_SR_BSF)); 512 SPIREG_WRITE(sc, SPI_IMR, 0); 513 SPIREG_WRITE(sc, SPI_SER, 0); 514 st = sc->sc_transfer; 515 sc->sc_transfer = NULL; 516 KASSERT(st != NULL); 517 spi_done(st, 0); 518 sc->sc_running = false; 519 } else { 520 rk_spi_set_interrupt_mask(sc); 521 } 522 523 SPIREG_WRITE(sc, SPI_ICR, icr); 524 525 return 1; 526 } 527
Indexes created Sun Oct 12 02:09:55 GMT 2025