rk_spi.c revision 1.6.4.2
1 /* $NetBSD: rk_spi.c,v 1.6.4.2 2021/06/17 04:46:18 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tobias Nygren. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: rk_spi.c,v 1.6.4.2 2021/06/17 04:46:18 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/bitops.h> 42 #include <dev/spi/spivar.h> 43 #include <dev/fdt/fdtvar.h> 44 #include <arm/fdt/arm_fdtvar.h> 45 46 #define SPI_CTRLR0 0x00 47 #define SPI_CTRLR0_MTM __BIT(21) 48 #define SPI_CTRLR0_OPM __BIT(20) 49 #define SPI_CTRLR0_XFM __BITS(19, 18) 50 #define SPI_CTRLR0_FRF __BITS(17, 16) 51 #define SPI_CTRLR0_RSD __BITS(15, 14) 52 #define SPI_CTRLR0_BHT __BIT(13) 53 #define SPI_CTRLR0_FBM __BIT(12) 54 #define SPI_CTRLR0_EM __BIT(11) 55 #define SPI_CTRLR0_RW __BIT(10) 56 #define SPI_CTRLR0_CSM __BITS(9, 8) 57 #define SPI_CTRLR0_SCPOL __BIT(7) 58 #define SPI_CTRLR0_SCPH __BIT(6) 59 #define SPI_CTRLR0_CFS __BITS(5, 2) 60 #define SPI_CTRLR0_DFS __BITS(1, 0) 61 #define SPI_CTRLR0_DFS_4BIT 0x0 62 #define SPI_CTRLR0_DFS_8BIT 0x1 63 #define SPI_CTRLR0_DFS_16BIT 0x2 64 65 #define SPI_CTRLR1 0x04 66 #define SPI_CTRLR1_NDM __BITS(15, 0) 67 68 #define SPI_ENR 0x08 69 #define SPI_ENR_ENR __BIT(0) 70 71 #define SPI_SER 0x0c 72 #define SPI_SER_SER1 __BIT(1) 73 #define SPI_SER_SER0 __BIT(0) 74 75 #define SPI_BAUDR 0x10 76 #define SPI_BAUDR_BAUDR __BITS(15, 0) 77 78 #define SPI_TXFTLR 0x14 79 #define SPI_TXFTLR_TXFLTR __BITS(4, 0) 80 81 #define SPI_RXFTLR 0x18 82 #define SPI_RXFLTR_RXFLTR __BITS(4, 0) 83 84 #define SPI_TXFLR 0x1c 85 #define SPI_TXFLR_TXFLR __BITS(5, 0) 86 87 #define SPI_RXFLR 0x20 88 #define SPI_RXFLR_RXFLR __BITS(5, 0) 89 90 #define SPI_SR 0x24 91 #define SPI_SR_RFF __BIT(4) 92 #define SPI_SR_RFE __BIT(3) 93 #define SPI_SR_TFE __BIT(2) 94 #define SPI_SR_TFF __BIT(1) 95 #define SPI_SR_BSF __BIT(0) 96 97 #define SPI_IPR 0x28 98 #define SPI_IPR_IPR __BIT(0) 99 100 #define SPI_IMR 0x2c 101 #define SPI_IMR_RFFIM __BIT(4) 102 #define SPI_IMR_RFOIM __BIT(3) 103 #define SPI_IMR_RFUIM __BIT(2) 104 #define SPI_IMR_TFOIM __BIT(1) 105 #define SPI_IMR_TFEIM __BIT(0) 106 107 #define SPI_ISR 0x30 108 #define SPI_ISR_RFFIS __BIT(4) 109 #define SPI_ISR_RFOIS __BIT(3) 110 #define SPI_ISR_RFUIS __BIT(2) 111 #define SPI_ISR_TFOIS __BIT(1) 112 #define SPI_ISR_TFEIS __BIT(0) 113 114 #define SPI_RISR 0x34 115 #define SPI_RISR_RFFRIS __BIT(4) 116 #define SPI_RISR_RFORIS __BIT(3) 117 #define SPI_RISR_RFURIS __BIT(2) 118 #define SPI_RISR_TFORIS __BIT(1) 119 #define SPI_RISR_TFERIS __BIT(0) 120 121 #define SPI_ICR 0x38 122 #define SPI_ICR_CTFOI __BIT(3) 123 #define SPI_ICR_CRFOI __BIT(2) 124 #define SPI_ICR_CRFUI __BIT(1) 125 #define SPI_ICR_CCI __BIT(0) 126 #define SPI_ICR_ALL __BITS(3, 0) 127 128 #define SPI_DMACR 0x3c 129 #define SPI_DMACR_TDE __BIT(1) 130 #define SPI_DMACR_RDE __BIT(0) 131 132 #define SPI_DMATDLR 0x40 133 #define SPI_DMATDLR_TDL __BITS(4, 0) 134 135 #define SPI_DMARDLR 0x44 136 #define SPI_DMARDLR_RDL __BITS(4, 0) 137 138 #define SPI_TXDR 0x400 139 #define SPI_TXDR_TXDR __BITS(15, 0) 140 141 #define SPI_RXDR 0x800 142 #define SPI_RXDR_RXDR __BITS(15, 0) 143 144 #define SPI_FIFOLEN 32 145 146 static const struct device_compatible_entry compat_data[] = { 147 { .compat = "rockchip,rk3066-spi" }, 148 { .compat = "rockchip,rk3328-spi" }, 149 { .compat = "rockchip,rk3399-spi" }, 150 DEVICE_COMPAT_EOL 151 }; 152 153 struct rk_spi_softc { 154 device_t sc_dev; 155 bus_space_tag_t sc_bst; 156 bus_space_handle_t sc_bsh; 157 void *sc_ih; 158 u_int sc_spi_freq; 159 struct spi_controller sc_spi; 160 SIMPLEQ_HEAD(,spi_transfer) sc_q; 161 struct spi_transfer *sc_transfer; 162 struct spi_chunk *sc_rchunk, *sc_wchunk; 163 volatile bool sc_running; 164 }; 165 166 #define SPIREG_READ(sc, reg) \ 167 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 168 #define SPIREG_WRITE(sc, reg, val) \ 169 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 170 171 static int rk_spi_match(device_t, cfdata_t, void *); 172 static void rk_spi_attach(device_t, device_t, void *); 173 174 static int rk_spi_configure(void *, int, int, int); 175 static int rk_spi_transfer(void *, struct spi_transfer *); 176 177 static void rk_spi_txfifo_fill(struct rk_spi_softc * const, size_t); 178 static void rk_spi_rxfifo_drain(struct rk_spi_softc * const, size_t); 179 static void rk_spi_rxtx(struct rk_spi_softc * const); 180 static void rk_spi_set_interrupt_mask(struct rk_spi_softc * const); 181 static void rk_spi_start(struct rk_spi_softc * const); 182 static int rk_spi_intr(void *); 183 184 CFATTACH_DECL_NEW(rk_spi, sizeof(struct rk_spi_softc), 185 rk_spi_match, rk_spi_attach, NULL, NULL); 186 187 static int 188 rk_spi_match(device_t parent, cfdata_t cf, void *aux) 189 { 190 struct fdt_attach_args * const faa = aux; 191 192 return of_compatible_match(faa->faa_phandle, compat_data); 193 } 194 195 static void 196 rk_spi_attach(device_t parent, device_t self, void *aux) 197 { 198 struct rk_spi_softc * const sc = device_private(self); 199 struct fdt_attach_args * const faa = aux; 200 const int phandle = faa->faa_phandle; 201 bus_addr_t addr; 202 bus_size_t size; 203 struct clk *sclk, *pclk; 204 char intrstr[128]; 205 206 sc->sc_dev = self; 207 sc->sc_bst = faa->faa_bst; 208 SIMPLEQ_INIT(&sc->sc_q); 209 210 if ((sclk = fdtbus_clock_get(phandle, "spiclk")) == NULL 211 || clk_enable(sclk) != 0) { 212 aprint_error(": couldn't enable sclk\n"); 213 return; 214 } 215 216 if ((pclk = fdtbus_clock_get(phandle, "apb_pclk")) == NULL 217 || clk_enable(pclk) != 0) { 218 aprint_error(": couldn't enable pclk\n"); 219 return; 220 } 221 222 sc->sc_spi_freq = clk_get_rate(sclk); 223 224 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 225 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 226 aprint_error(": couldn't map registers\n"); 227 return; 228 } 229 230 SPIREG_WRITE(sc, SPI_ENR, 0); 231 SPIREG_WRITE(sc, SPI_IMR, 0); 232 233 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 234 aprint_error(": failed to decode interrupt\n"); 235 return; 236 } 237 238 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0, 239 rk_spi_intr, sc, device_xname(self)); 240 if (sc->sc_ih == NULL) { 241 aprint_error(": unable to establish interrupt\n"); 242 return; 243 } 244 245 aprint_naive("\n"); 246 aprint_normal(": SPI\n"); 247 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 248 249 sc->sc_spi.sct_cookie = sc; 250 sc->sc_spi.sct_configure = rk_spi_configure; 251 sc->sc_spi.sct_transfer = rk_spi_transfer; 252 sc->sc_spi.sct_nslaves = 2; 253 254 fdtbus_register_spi_controller(&sc->sc_spi, phandle); 255 256 struct spibus_attach_args sba = { 257 .sba_controller = &sc->sc_spi, 258 }; 259 config_found(self, &sba, spibus_print, 260 CFARG_DEVHANDLE, device_handle(self), 261 CFARG_EOL); 262 } 263 264 static int 265 rk_spi_configure(void *cookie, int slave, int mode, int speed) 266 { 267 struct rk_spi_softc * const sc = cookie; 268 uint32_t ctrlr0; 269 uint16_t divider; 270 271 divider = (sc->sc_spi_freq / speed) & ~1; 272 if (divider < 2) { 273 aprint_error_dev(sc->sc_dev, 274 "spi_clk %u is too low for speed %u, using speed %u\n", 275 sc->sc_spi_freq, speed, sc->sc_spi_freq / 2); 276 divider = 2; 277 } 278 279 if (slave >= sc->sc_spi.sct_nslaves) 280 return EINVAL; 281 282 ctrlr0 = SPI_CTRLR0_BHT | __SHIFTIN(SPI_CTRLR0_DFS_8BIT, SPI_CTRLR0_DFS); 283 284 switch (mode) { 285 case SPI_MODE_0: 286 ctrlr0 |= 0; 287 break; 288 case SPI_MODE_1: 289 ctrlr0 |= SPI_CTRLR0_SCPH; 290 break; 291 case SPI_MODE_2: 292 ctrlr0 |= SPI_CTRLR0_SCPOL; 293 break; 294 case SPI_MODE_3: 295 ctrlr0 |= SPI_CTRLR0_SCPH | SPI_CTRLR0_SCPOL; 296 break; 297 default: 298 return EINVAL; 299 } 300 301 SPIREG_WRITE(sc, SPI_ENR, 0); 302 SPIREG_WRITE(sc, SPI_SER, 0); 303 SPIREG_WRITE(sc, SPI_CTRLR0, ctrlr0); 304 SPIREG_WRITE(sc, SPI_BAUDR, divider); 305 306 SPIREG_WRITE(sc, SPI_DMACR, 0); 307 SPIREG_WRITE(sc, SPI_DMATDLR, 0); 308 SPIREG_WRITE(sc, SPI_DMARDLR, 0); 309 310 SPIREG_WRITE(sc, SPI_IPR, 0); 311 SPIREG_WRITE(sc, SPI_IMR, 0); 312 SPIREG_WRITE(sc, SPI_ICR, SPI_ICR_ALL); 313 314 SPIREG_WRITE(sc, SPI_ENR, 1); 315 316 return 0; 317 } 318 319 static int 320 rk_spi_transfer(void *cookie, struct spi_transfer *st) 321 { 322 struct rk_spi_softc * const sc = cookie; 323 int s; 324 325 s = splbio(); 326 spi_transq_enqueue(&sc->sc_q, st); 327 if (sc->sc_running == false) { 328 rk_spi_start(sc); 329 } 330 splx(s); 331 332 return 0; 333 } 334 335 static void 336 rk_spi_txfifo_fill(struct rk_spi_softc * const sc, size_t maxlen) 337 { 338 struct spi_chunk *chunk = sc->sc_wchunk; 339 size_t len; 340 uint8_t b; 341 342 if (chunk == NULL) 343 return; 344 345 len = MIN(maxlen, chunk->chunk_wresid); 346 chunk->chunk_wresid -= len; 347 while (len--) { 348 if (chunk->chunk_wptr) { 349 b = *chunk->chunk_wptr++; 350 } else { 351 b = 0; 352 } 353 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDR, b); 354 } 355 if (sc->sc_wchunk->chunk_wresid == 0) { 356 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 357 } 358 } 359 360 static void 361 rk_spi_rxfifo_drain(struct rk_spi_softc * const sc, size_t maxlen) 362 { 363 struct spi_chunk *chunk = sc->sc_rchunk; 364 size_t len; 365 uint8_t b; 366 367 if (chunk == NULL) 368 return; 369 370 len = MIN(maxlen, chunk->chunk_rresid); 371 chunk->chunk_rresid -= len; 372 373 while (len--) { 374 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDR); 375 if (chunk->chunk_rptr) { 376 *chunk->chunk_rptr++ = b; 377 } 378 } 379 if (sc->sc_rchunk->chunk_rresid == 0) { 380 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 381 } 382 } 383 384 static void 385 rk_spi_rxtx(struct rk_spi_softc * const sc) 386 { 387 bool again; 388 uint32_t reg; 389 size_t avail; 390 391 /* Service both FIFOs until no more progress can be made. */ 392 again = true; 393 while (again) { 394 again = false; 395 reg = SPIREG_READ(sc, SPI_RXFLR); 396 avail = __SHIFTOUT(reg, SPI_RXFLR_RXFLR); 397 if (avail > 0) { 398 KASSERT(sc->sc_rchunk != NULL); 399 rk_spi_rxfifo_drain(sc, avail); 400 again = true; 401 } 402 reg = SPIREG_READ(sc, SPI_TXFLR); 403 avail = SPI_FIFOLEN - __SHIFTOUT(reg, SPI_TXFLR_TXFLR); 404 if (avail > 0 && sc->sc_wchunk != NULL) { 405 rk_spi_txfifo_fill(sc, avail); 406 again = true; 407 } 408 } 409 } 410 411 static void 412 rk_spi_set_interrupt_mask(struct rk_spi_softc * const sc) 413 { 414 uint32_t imr = SPI_IMR_RFOIM | SPI_IMR_RFUIM | SPI_IMR_TFOIM; 415 int len; 416 417 /* 418 * Delay rx interrupts until the FIFO has the # of bytes we'd 419 * ideally like to receive, or FIFO is half full. 420 */ 421 len = sc->sc_rchunk != NULL 422 ? MIN(sc->sc_rchunk->chunk_rresid, SPI_FIFOLEN / 2) : 0; 423 if (len > 0) { 424 SPIREG_WRITE(sc, SPI_RXFTLR, len - 1); 425 imr |= SPI_IMR_RFFIM; 426 } 427 428 /* 429 * Delay tx interrupts until the FIFO can accept the # of bytes we'd 430 * ideally like to transmit, or the FIFO is half empty. 431 */ 432 len = sc->sc_wchunk != NULL 433 ? MIN(sc->sc_wchunk->chunk_wresid, SPI_FIFOLEN / 2) : 0; 434 if (len > 0) { 435 SPIREG_WRITE(sc, SPI_TXFTLR, SPI_FIFOLEN - len); 436 imr |= SPI_IMR_TFEIM; 437 } 438 439 /* If xfer is done, then interrupt as soon as the tx fifo is empty. */ 440 if (!ISSET(imr, (SPI_IMR_RFFIM | SPI_IMR_TFEIM))) { 441 SPIREG_WRITE(sc, SPI_TXFTLR, 0); 442 imr |= SPI_IMR_TFEIM; 443 } 444 445 SPIREG_WRITE(sc, SPI_IMR, imr); 446 } 447 448 static void 449 rk_spi_start(struct rk_spi_softc * const sc) 450 { 451 struct spi_transfer *st; 452 453 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 454 spi_transq_dequeue(&sc->sc_q); 455 KASSERT(sc->sc_transfer == NULL); 456 sc->sc_transfer = st; 457 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 458 sc->sc_running = true; 459 460 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves); 461 SPIREG_WRITE(sc, SPI_SER, 1 << st->st_slave); 462 463 rk_spi_rxtx(sc); 464 rk_spi_set_interrupt_mask(sc); 465 466 if (!cold) 467 return; 468 469 for (;;) { 470 (void) rk_spi_intr(sc); 471 if (ISSET(st->st_flags, SPI_F_DONE)) 472 break; 473 } 474 } 475 sc->sc_running = false; 476 } 477 478 static int 479 rk_spi_intr(void *cookie) 480 { 481 struct rk_spi_softc * const sc = cookie; 482 struct spi_transfer *st; 483 uint32_t isr; 484 uint32_t sr; 485 uint32_t icr = SPI_ICR_CCI; 486 487 isr = SPIREG_READ(sc, SPI_ISR); 488 if (!isr) 489 return 0; 490 491 if (ISSET(isr, SPI_ISR_RFOIS)) { 492 device_printf(sc->sc_dev, "RXFIFO overflow\n"); 493 icr |= SPI_ICR_CRFOI; 494 } 495 if (ISSET(isr, SPI_ISR_RFUIS)) { 496 device_printf(sc->sc_dev, "RXFIFO underflow\n"); 497 icr |= SPI_ICR_CRFUI; 498 } 499 if (ISSET(isr, SPI_ISR_TFOIS)) { 500 device_printf(sc->sc_dev, "TXFIFO overflow\n"); 501 icr |= SPI_ICR_CTFOI; 502 } 503 504 rk_spi_rxtx(sc); 505 506 if (sc->sc_rchunk == NULL && sc->sc_wchunk == NULL) { 507 do { 508 sr = SPIREG_READ(sc, SPI_SR); 509 } while (ISSET(sr, SPI_SR_BSF)); 510 SPIREG_WRITE(sc, SPI_IMR, 0); 511 SPIREG_WRITE(sc, SPI_SER, 0); 512 st = sc->sc_transfer; 513 sc->sc_transfer = NULL; 514 KASSERT(st != NULL); 515 spi_done(st, 0); 516 sc->sc_running = false; 517 } else { 518 rk_spi_set_interrupt_mask(sc); 519 } 520 521 SPIREG_WRITE(sc, SPI_ICR, icr); 522 523 return 1; 524 } 525
Indexes created Sun Oct 12 02:09:55 GMT 2025