rk_tsadc.c revision 1.6 1 1.6 joerg /* $NetBSD: rk_tsadc.c,v 1.6 2019/06/01 19:32:19 joerg Exp $ */
2 1.1 mrg
3 1.1 mrg /*
4 1.1 mrg * Copyright (c) 2019 Matthew R. Green
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * Redistribution and use in source and binary forms, with or without
8 1.1 mrg * modification, are permitted provided that the following conditions
9 1.1 mrg * are met:
10 1.1 mrg * 1. Redistributions of source code must retain the above copyright
11 1.1 mrg * notice, this list of conditions and the following disclaimer.
12 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 mrg * notice, this list of conditions and the following disclaimer in the
14 1.1 mrg * documentation and/or other materials provided with the distribution.
15 1.1 mrg * 3. The name of the author may not be used to endorse or promote products
16 1.1 mrg * derived from this software without specific prior written permission.
17 1.1 mrg *
18 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 1.1 mrg * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 1.1 mrg * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 1.1 mrg * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.1 mrg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 mrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 mrg * SUCH DAMAGE.
29 1.1 mrg */
30 1.1 mrg
31 1.1 mrg #include <sys/cdefs.h>
32 1.1 mrg
33 1.6 joerg __KERNEL_RCSID(0, "$NetBSD: rk_tsadc.c,v 1.6 2019/06/01 19:32:19 joerg Exp $");
34 1.1 mrg
35 1.1 mrg /*
36 1.1 mrg * Driver for the TSADC temperature sensor monitor in RK3328 and RK3399.
37 1.1 mrg *
38 1.1 mrg * TODO:
39 1.1 mrg * - handle setting various temp values
40 1.1 mrg * - handle DT trips/temp value defaults
41 1.1 mrg * - interrupts aren't triggered (test by lowering warn/crit values), and
42 1.1 mrg * once they work, make the interrupt do something
43 1.1 mrg */
44 1.1 mrg
45 1.1 mrg #include <sys/param.h>
46 1.1 mrg #include <sys/bus.h>
47 1.1 mrg #include <sys/device.h>
48 1.1 mrg #include <sys/intr.h>
49 1.1 mrg #include <sys/systm.h>
50 1.1 mrg #include <sys/time.h>
51 1.1 mrg #include <sys/kmem.h>
52 1.1 mrg
53 1.1 mrg #include <dev/fdt/fdtvar.h>
54 1.1 mrg #include <dev/fdt/syscon.h>
55 1.1 mrg
56 1.1 mrg #include <dev/sysmon/sysmonvar.h>
57 1.1 mrg
58 1.1 mrg #ifdef RKTSADC_DEBUG
59 1.1 mrg #define DPRINTF(fmt, ...) \
60 1.1 mrg printf("%s:%d: " fmt "\n", __func__, __LINE__, ## __VA_ARGS__)
61 1.1 mrg #else
62 1.1 mrg #define DPRINTF(fmt, ...)
63 1.1 mrg #endif
64 1.1 mrg
65 1.1 mrg /* Register definitions */
66 1.1 mrg #define TSADC_USER_CON 0x00
67 1.1 mrg #define TSADC_USER_CON_ADC_STATUS __BIT(12)
68 1.1 mrg #define TSADC_USER_CON_INTER_PD_SOC __BITS(11,6)
69 1.1 mrg #define TSADC_USER_CON_START __BIT(5)
70 1.1 mrg #define TSADC_USER_CON_START_MODE __BIT(4)
71 1.1 mrg #define TSADC_USER_CON_ADC_POWER_CTRL __BIT(3)
72 1.1 mrg #define TSADC_USER_CON_ADC_INPUT_SRC_SEL __BITS(2,0)
73 1.1 mrg #define TSADC_AUTO_CON 0x04
74 1.1 mrg #define TSADC_AUTO_CON_LAST_TSHUT_2CRU __BIT(25)
75 1.1 mrg #define TSADC_AUTO_CON_LAST_TSHUT_2GPIO __BIT(24)
76 1.1 mrg #define TSADC_AUTO_CON_SAMPLE_DLY_SEL __BIT(17)
77 1.1 mrg #define TSADC_AUTO_CON_AUTO_STATUS __BIT(16)
78 1.1 mrg #define TSADC_AUTO_CON_SRC1_LT_EN __BIT(13)
79 1.1 mrg #define TSADC_AUTO_CON_SRC0_LT_EN __BIT(12)
80 1.1 mrg #define TSADC_AUTO_CON_TSHUT_POLARITY __BIT(8)
81 1.1 mrg #define TSADC_AUTO_CON_SRC1_EN __BIT(5)
82 1.1 mrg #define TSADC_AUTO_CON_SRC0_EN __BIT(4)
83 1.1 mrg #define TSADC_AUTO_CON_Q_SEL __BIT(1)
84 1.1 mrg #define TSADC_AUTO_CON_AUTO_EN __BIT(0)
85 1.1 mrg #define TSADC_INT_EN 0x08
86 1.1 mrg #define TSADC_INT_EN_EOC_INT_EN __BIT(16)
87 1.1 mrg #define TSADC_INT_EN_LT_INTEN_SRC1 __BIT(13)
88 1.1 mrg #define TSADC_INT_EN_LT_INTEN_SRC0 __BIT(12)
89 1.1 mrg #define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1 __BIT(9)
90 1.1 mrg #define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0 __BIT(8)
91 1.1 mrg #define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1 __BIT(5)
92 1.1 mrg #define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0 __BIT(4)
93 1.1 mrg #define TSADC_INT_EN_HT_INTEN_SRC1 __BIT(1)
94 1.1 mrg #define TSADC_INT_EN_HT_INTEN_SRC0 __BIT(0)
95 1.1 mrg #define TSADC_INT_PD 0x0c
96 1.1 mrg #define TSADC_INT_PD_EOC_INT_PD __BIT(16)
97 1.1 mrg #define TSADC_INT_PD_LT_IRQ_SRC1 __BIT(13)
98 1.1 mrg #define TSADC_INT_PD_LT_IRQ_SRC0 __BIT(12)
99 1.1 mrg #define TSADC_INT_PD_TSHUT_O_SRC1 __BIT(5)
100 1.1 mrg #define TSADC_INT_PD_TSHUT_O_SRC0 __BIT(4)
101 1.1 mrg #define TSADC_INT_PD_HT_IRQ_SRC1 __BIT(1)
102 1.1 mrg #define TSADC_INT_PD_HT_IRQ_SRC0 __BIT(0)
103 1.1 mrg #define TSADC_DATA0 0x20
104 1.1 mrg #define TSADC_DATA0_ADC_DATA __BITS(11,0)
105 1.1 mrg #define TSADC_DATA1 0x24
106 1.1 mrg #define TSADC_DATA1_ADC_DATA __BITS(11,0)
107 1.1 mrg #define TSADC_COMP0_INT 0x30
108 1.1 mrg #define TSADC_COMP0_INT_COMP_SRC0 __BITS(11,0)
109 1.1 mrg #define TSADC_COMP1_INT 0x34
110 1.1 mrg #define TSADC_COMP1_INT_COMP_SRC1 __BITS(11,0)
111 1.1 mrg #define TSADC_COMP0_SHUT 0x40
112 1.1 mrg #define TSADC_COMP0_SHUT_COMP_SRC0 __BITS(11,0)
113 1.1 mrg #define TSADC_COMP1_SHUT 0x44
114 1.1 mrg #define TSADC_COMP1_SHUT_COMP_SRC1 __BITS(11,0)
115 1.1 mrg #define TSADC_HIGH_INT_DEBOUNCE 0x60
116 1.1 mrg #define TSADC_HIGH_INT_DEBOUNCE_TEMP __BITS(7,0)
117 1.1 mrg #define TSADC_HIGH_TSHUT_DEBOUNCE 0x64
118 1.1 mrg #define TSADC_HIGH_TSHUT_DEBOUNCE_TEMP __BITS(7,0)
119 1.1 mrg #define TSADC_AUTO_PERIOD 0x68
120 1.1 mrg #define TSADC_AUTO_PERIOD_TEMP __BITS(31,0)
121 1.1 mrg #define TSADC_AUTO_PERIOD_HT 0x6c
122 1.1 mrg #define TSADC_AUTO_PERIOD_HT_TEMP __BITS(31,0)
123 1.1 mrg #define TSADC_COMP0_LOW_INT 0x80
124 1.1 mrg #define TSADC_COMP0_LOW_INT_COMP_SRC0 __BITS(11,0)
125 1.1 mrg #define TSADC_COMP1_LOW_INT 0x84
126 1.1 mrg #define TSADC_COMP1_LOW_INT_COMP_SRC1 __BITS(11,0)
127 1.1 mrg
128 1.4 mrg #define RK3328_TSADC_AUTO_PERIOD_TIME 250 /* 250ms */
129 1.4 mrg #define RK3399_TSADC_AUTO_PERIOD_TIME 1875 /* 2.5ms */
130 1.1 mrg #define TSADC_HT_DEBOUNCE_COUNT 4
131 1.1 mrg
132 1.1 mrg /*
133 1.1 mrg * All this magic is taking from the Linux rockchip_thermal driver.
134 1.1 mrg *
135 1.1 mrg * VCM means "voltage common mode", but the documentation for RK3399
136 1.1 mrg * does not mention this and I don't know what any of this really
137 1.1 mrg * is for.
138 1.1 mrg */
139 1.1 mrg #define RK3399_GRF_SARADC_TESTBIT 0xe644
140 1.1 mrg #define RK3399_GRF_SARADC_TESTBIT_ON (0x10001 << 2)
141 1.1 mrg #define RK3399_GRF_TSADC_TESTBIT_L 0xe648
142 1.1 mrg #define RK3399_GRF_TSADC_TESTBIT_VCM_EN_L (0x10001 << 7)
143 1.1 mrg #define RK3399_GRF_TSADC_TESTBIT_H 0xe64c
144 1.1 mrg #define RK3399_GRF_TSADC_TESTBIT_VCM_EN_H (0x10001 << 7)
145 1.1 mrg #define RK3399_GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
146 1.1 mrg
147 1.1 mrg #define TEMP_uC_TO_uK 273150000
148 1.1 mrg
149 1.1 mrg #define TSHUT_MODE_CPU 0
150 1.1 mrg #define TSHUT_MODE_GPIO 1
151 1.1 mrg
152 1.1 mrg #define TSHUT_LOW_ACTIVE 0
153 1.1 mrg #define TSHUT_HIGH_ACTIVE 1
154 1.1 mrg
155 1.1 mrg #define TSHUT_DEF_TEMP 95000
156 1.1 mrg
157 1.1 mrg #define TSADC_DATA_MAX 0xfff
158 1.1 mrg
159 1.5 mrg #define MAX_SENSORS 2
160 1.1 mrg
161 1.4 mrg typedef struct rk_data_array {
162 1.1 mrg uint32_t data; /* register value */
163 1.1 mrg int temp; /* micro-degC */
164 1.4 mrg } rk_data_array;
165 1.4 mrg
166 1.4 mrg struct rk_tsadc_softc;
167 1.5 mrg typedef struct rk_data {
168 1.5 mrg const rk_data_array *rd_array;
169 1.5 mrg size_t rd_size;
170 1.5 mrg void (*rd_init)(struct rk_tsadc_softc *, int, int);
171 1.5 mrg bool rd_decr; /* lower values -> higher temp */
172 1.5 mrg unsigned rd_min, rd_max;
173 1.5 mrg unsigned rd_auto_period;
174 1.5 mrg unsigned rd_num_sensors;
175 1.5 mrg } rk_data;
176 1.1 mrg
177 1.1 mrg /* Per-sensor data */
178 1.1 mrg struct rk_tsadc_sensor {
179 1.1 mrg envsys_data_t s_data;
180 1.1 mrg bool s_attached;
181 1.1 mrg /* TSADC register offsets for this sensor */
182 1.1 mrg unsigned s_data_reg;
183 1.1 mrg unsigned s_comp_tshut;
184 1.1 mrg unsigned s_comp_int;
185 1.2 mrg /* enable bit in AUTO_CON register */
186 1.1 mrg unsigned s_comp_int_en;
187 1.1 mrg /* warn/crit values in micro Kelvin */
188 1.1 mrg int s_warn;
189 1.1 mrg int s_tshut;
190 1.1 mrg };
191 1.1 mrg
192 1.1 mrg struct rk_tsadc_softc {
193 1.1 mrg device_t sc_dev;
194 1.1 mrg int sc_phandle;
195 1.1 mrg bus_space_tag_t sc_bst;
196 1.1 mrg bus_space_handle_t sc_bsh;
197 1.1 mrg size_t sc_size;
198 1.1 mrg uint32_t sc_data_mask;
199 1.1 mrg void *sc_ih;
200 1.1 mrg
201 1.1 mrg struct sysmon_envsys *sc_sme;
202 1.5 mrg struct rk_tsadc_sensor sc_sensors[MAX_SENSORS];
203 1.1 mrg
204 1.1 mrg struct clk *sc_clock;
205 1.1 mrg struct clk *sc_clockapb;
206 1.1 mrg struct fdtbus_reset *sc_reset;
207 1.1 mrg struct syscon *sc_syscon;
208 1.4 mrg
209 1.5 mrg const rk_data *sc_rd;
210 1.1 mrg };
211 1.1 mrg
212 1.1 mrg static int rk_tsadc_match(device_t, cfdata_t, void *);
213 1.1 mrg static void rk_tsadc_attach(device_t, device_t, void *);
214 1.1 mrg static int rk_tsadc_detach(device_t, int);
215 1.1 mrg static int rk_tsadc_init_clocks(struct rk_tsadc_softc *);
216 1.1 mrg static void rk_tsadc_init_counts(struct rk_tsadc_softc *);
217 1.1 mrg static void rk_tsadc_tshut_set(struct rk_tsadc_softc *s);
218 1.1 mrg static void rk_tsadc_init_tshut(struct rk_tsadc_softc *, int, int);
219 1.4 mrg static void rk_tsadc_init_rk3328(struct rk_tsadc_softc *, int, int);
220 1.4 mrg static void rk_tsadc_init_rk3399(struct rk_tsadc_softc *, int, int);
221 1.1 mrg static void rk_tsadc_init_enable(struct rk_tsadc_softc *);
222 1.4 mrg static void rk_tsadc_init(struct rk_tsadc_softc *, int, int);
223 1.1 mrg static void rk_tsadc_refresh(struct sysmon_envsys *, envsys_data_t *);
224 1.1 mrg static void rk_tsadc_get_limits(struct sysmon_envsys *, envsys_data_t *,
225 1.1 mrg sysmon_envsys_lim_t *, uint32_t *);
226 1.1 mrg
227 1.1 mrg static int rk_tsadc_intr(void *);
228 1.1 mrg static int rk_tsadc_data_to_temp(struct rk_tsadc_softc *, uint32_t);
229 1.1 mrg static uint32_t rk_tsadc_temp_to_data(struct rk_tsadc_softc *, int);
230 1.1 mrg
231 1.1 mrg /* RK3328/RK3399 compatible sensors */
232 1.1 mrg static const struct rk_tsadc_sensor rk_tsadc_sensors[] = {
233 1.1 mrg {
234 1.1 mrg .s_data = { .desc = "CPU" },
235 1.1 mrg .s_data_reg = TSADC_DATA0,
236 1.1 mrg .s_comp_tshut = TSADC_COMP0_SHUT,
237 1.1 mrg .s_comp_int = TSADC_COMP0_INT,
238 1.1 mrg .s_comp_int_en = TSADC_AUTO_CON_SRC0_EN,
239 1.1 mrg /*
240 1.1 mrg * XXX DT has:
241 1.1 mrg * cpu_alert1: cpu_alert1 {
242 1.1 mrg * temperature = <75000>;
243 1.1 mrg * hysteresis = <2000>;
244 1.1 mrg * cpu_crit: cpu_crit {
245 1.1 mrg * temperature = <95000>;
246 1.1 mrg * hysteresis = <2000>;
247 1.1 mrg * pull out of here?
248 1.1 mrg * do something with hysteresis? put in debounce?
249 1.1 mrg *
250 1.1 mrg * Note that tshut may be overriden by the board specific DT.
251 1.1 mrg */
252 1.1 mrg .s_warn = 75000000,
253 1.1 mrg .s_tshut = 95000000,
254 1.1 mrg }, {
255 1.1 mrg .s_data = { .desc = "GPU" },
256 1.1 mrg .s_data_reg = TSADC_DATA1,
257 1.1 mrg .s_comp_tshut = TSADC_COMP1_SHUT,
258 1.1 mrg .s_comp_int = TSADC_COMP1_INT,
259 1.1 mrg .s_comp_int_en = TSADC_AUTO_CON_SRC1_EN,
260 1.1 mrg .s_warn = 75000000,
261 1.1 mrg .s_tshut = 95000000,
262 1.1 mrg },
263 1.1 mrg };
264 1.1 mrg
265 1.5 mrg /*
266 1.5 mrg * Table from RK3328 manual. Note that the manual lists valid numbers as
267 1.5 mrg * 4096 - number. This also means it is increasing not decreasing for
268 1.5 mrg * higher temps, and the min and max are also offset from 4096.
269 1.5 mrg */
270 1.5 mrg #define RK3328_DATA_OFFSET (4096)
271 1.4 mrg static const rk_data_array rk3328_data_array[] = {
272 1.5 mrg #define ENTRY(d,C) \
273 1.5 mrg { .data = RK3328_DATA_OFFSET - (d), .temp = (C) * 1000 * 1000, }
274 1.4 mrg ENTRY(TSADC_DATA_MAX, -40),
275 1.4 mrg ENTRY(3800, -40),
276 1.4 mrg ENTRY(3792, -35),
277 1.4 mrg ENTRY(3783, -30),
278 1.4 mrg ENTRY(3774, -25),
279 1.4 mrg ENTRY(3765, -20),
280 1.4 mrg ENTRY(3756, -15),
281 1.4 mrg ENTRY(3747, -10),
282 1.4 mrg ENTRY(3737, -5),
283 1.4 mrg ENTRY(3728, 0),
284 1.4 mrg ENTRY(3718, 5),
285 1.4 mrg ENTRY(3708, 10),
286 1.4 mrg ENTRY(3698, 15),
287 1.4 mrg ENTRY(3688, 20),
288 1.4 mrg ENTRY(3678, 25),
289 1.4 mrg ENTRY(3667, 30),
290 1.4 mrg ENTRY(3656, 35),
291 1.4 mrg ENTRY(3645, 40),
292 1.4 mrg ENTRY(3634, 45),
293 1.4 mrg ENTRY(3623, 50),
294 1.4 mrg ENTRY(3611, 55),
295 1.4 mrg ENTRY(3600, 60),
296 1.4 mrg ENTRY(3588, 65),
297 1.4 mrg ENTRY(3575, 70),
298 1.4 mrg ENTRY(3563, 75),
299 1.4 mrg ENTRY(3550, 80),
300 1.4 mrg ENTRY(3537, 85),
301 1.4 mrg ENTRY(3524, 90),
302 1.4 mrg ENTRY(3510, 95),
303 1.4 mrg ENTRY(3496, 100),
304 1.4 mrg ENTRY(3482, 105),
305 1.4 mrg ENTRY(3467, 110),
306 1.4 mrg ENTRY(3452, 115),
307 1.4 mrg ENTRY(3437, 120),
308 1.4 mrg ENTRY(3421, 125),
309 1.4 mrg ENTRY(0, 125),
310 1.4 mrg #undef ENTRY
311 1.4 mrg };
312 1.4 mrg
313 1.4 mrg /* Table from RK3399 manual */
314 1.4 mrg static const rk_data_array rk3399_data_array[] = {
315 1.4 mrg #define ENTRY(d,C) { .data = (d), .temp = (C) * 1000 * 1000, }
316 1.4 mrg ENTRY(0, -40),
317 1.4 mrg ENTRY(402, -40),
318 1.4 mrg ENTRY(410, -35),
319 1.4 mrg ENTRY(419, -30),
320 1.4 mrg ENTRY(427, -25),
321 1.4 mrg ENTRY(436, -20),
322 1.4 mrg ENTRY(444, -15),
323 1.4 mrg ENTRY(453, -10),
324 1.4 mrg ENTRY(461, -5),
325 1.4 mrg ENTRY(470, 0),
326 1.4 mrg ENTRY(478, 5),
327 1.4 mrg ENTRY(487, 10),
328 1.4 mrg ENTRY(496, 15),
329 1.4 mrg ENTRY(504, 20),
330 1.4 mrg ENTRY(513, 25),
331 1.4 mrg ENTRY(521, 30),
332 1.4 mrg ENTRY(530, 35),
333 1.4 mrg ENTRY(538, 40),
334 1.4 mrg ENTRY(547, 45),
335 1.4 mrg ENTRY(555, 50),
336 1.4 mrg ENTRY(564, 55),
337 1.4 mrg ENTRY(573, 60),
338 1.4 mrg ENTRY(581, 65),
339 1.4 mrg ENTRY(590, 70),
340 1.4 mrg ENTRY(599, 75),
341 1.4 mrg ENTRY(607, 80),
342 1.4 mrg ENTRY(616, 85),
343 1.4 mrg ENTRY(624, 90),
344 1.4 mrg ENTRY(633, 95),
345 1.4 mrg ENTRY(642, 100),
346 1.4 mrg ENTRY(650, 105),
347 1.4 mrg ENTRY(659, 110),
348 1.4 mrg ENTRY(668, 115),
349 1.4 mrg ENTRY(677, 120),
350 1.4 mrg ENTRY(685, 125),
351 1.4 mrg ENTRY(TSADC_DATA_MAX, 125),
352 1.4 mrg #undef ENTRY
353 1.4 mrg };
354 1.4 mrg
355 1.5 mrg static const rk_data rk3328_data_table = {
356 1.5 mrg .rd_array = rk3328_data_array,
357 1.5 mrg .rd_size = __arraycount(rk3328_data_array),
358 1.5 mrg .rd_init = rk_tsadc_init_rk3328,
359 1.5 mrg .rd_decr = false,
360 1.5 mrg .rd_max = RK3328_DATA_OFFSET - 3420,
361 1.5 mrg .rd_min = RK3328_DATA_OFFSET - 3801,
362 1.5 mrg .rd_auto_period = RK3328_TSADC_AUTO_PERIOD_TIME,
363 1.5 mrg .rd_num_sensors = 1,
364 1.4 mrg };
365 1.4 mrg
366 1.5 mrg static const rk_data rk3399_data_table = {
367 1.5 mrg .rd_array = rk3399_data_array,
368 1.5 mrg .rd_size = __arraycount(rk3399_data_array),
369 1.5 mrg .rd_init = rk_tsadc_init_rk3399,
370 1.5 mrg .rd_decr = false,
371 1.5 mrg .rd_max = 686,
372 1.5 mrg .rd_min = 401,
373 1.5 mrg .rd_auto_period = RK3399_TSADC_AUTO_PERIOD_TIME,
374 1.5 mrg .rd_num_sensors = 2,
375 1.4 mrg };
376 1.4 mrg
377 1.4 mrg static const char * const compatible_rk3328[] = {
378 1.1 mrg "rockchip,rk3328-tsadc",
379 1.4 mrg NULL
380 1.4 mrg };
381 1.4 mrg
382 1.4 mrg static const char * const compatible_rk3399[] = {
383 1.1 mrg "rockchip,rk3399-tsadc",
384 1.1 mrg NULL
385 1.1 mrg };
386 1.1 mrg
387 1.1 mrg #define TSADC_READ(sc, reg) \
388 1.1 mrg bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
389 1.1 mrg #define TSADC_WRITE(sc, reg, val) \
390 1.1 mrg bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
391 1.1 mrg
392 1.1 mrg CFATTACH_DECL3_NEW(rk_tsadc, sizeof(struct rk_tsadc_softc),
393 1.1 mrg rk_tsadc_match, rk_tsadc_attach, rk_tsadc_detach, NULL, NULL, NULL,
394 1.1 mrg DVF_DETACH_SHUTDOWN);
395 1.1 mrg
396 1.1 mrg /* init/teardown support */
397 1.1 mrg static int
398 1.1 mrg rk_tsadc_match(device_t parent, cfdata_t cf, void *aux)
399 1.1 mrg {
400 1.1 mrg struct fdt_attach_args * const faa = aux;
401 1.1 mrg
402 1.4 mrg return of_match_compatible(faa->faa_phandle, compatible_rk3328) ||
403 1.4 mrg of_match_compatible(faa->faa_phandle, compatible_rk3399);
404 1.1 mrg }
405 1.1 mrg
406 1.1 mrg static void
407 1.1 mrg rk_tsadc_attach(device_t parent, device_t self, void *aux)
408 1.1 mrg {
409 1.1 mrg struct rk_tsadc_softc * const sc = device_private(self);
410 1.1 mrg struct fdt_attach_args * const faa = aux;
411 1.1 mrg char intrstr[128];
412 1.1 mrg const int phandle = faa->faa_phandle;
413 1.1 mrg bus_addr_t addr;
414 1.1 mrg int mode, polarity, tshut_temp;
415 1.1 mrg
416 1.1 mrg sc->sc_dev = self;
417 1.1 mrg sc->sc_phandle = phandle;
418 1.1 mrg sc->sc_bst = faa->faa_bst;
419 1.1 mrg
420 1.1 mrg aprint_naive("\n");
421 1.1 mrg aprint_normal(": RK3328/3399 Temperature Sensor ADC\n");
422 1.1 mrg
423 1.1 mrg sc->sc_sme = sysmon_envsys_create();
424 1.1 mrg
425 1.1 mrg sc->sc_sme->sme_name = device_xname(self);
426 1.1 mrg sc->sc_sme->sme_cookie = sc;
427 1.1 mrg sc->sc_sme->sme_refresh = rk_tsadc_refresh;
428 1.1 mrg sc->sc_sme->sme_get_limits = rk_tsadc_get_limits;
429 1.2 mrg sc->sc_data_mask = TSADC_DATA_MAX;
430 1.1 mrg
431 1.1 mrg pmf_device_register(self, NULL, NULL);
432 1.1 mrg
433 1.5 mrg if (of_match_compatible(faa->faa_phandle, compatible_rk3328)) {
434 1.5 mrg sc->sc_rd = &rk3328_data_table;
435 1.5 mrg } else {
436 1.5 mrg KASSERT(of_match_compatible(faa->faa_phandle, compatible_rk3399));
437 1.5 mrg sc->sc_rd = &rk3399_data_table;
438 1.5 mrg }
439 1.5 mrg
440 1.1 mrg /* Default to tshut via gpio and tshut low is active */
441 1.1 mrg if (of_getprop_uint32(phandle, "rockchip,hw-tshut-mode",
442 1.1 mrg &mode) != 0) {
443 1.1 mrg aprint_error(": could not get TSHUT mode, default to GPIO");
444 1.1 mrg mode = TSHUT_MODE_GPIO;
445 1.1 mrg }
446 1.1 mrg if (mode != TSHUT_MODE_CPU && mode != TSHUT_MODE_GPIO) {
447 1.1 mrg aprint_error(": TSHUT mode should be 0 or 1\n");
448 1.1 mrg goto fail;
449 1.1 mrg }
450 1.1 mrg
451 1.1 mrg if (of_getprop_uint32(phandle, "rockchip,hw-tshut-polarity",
452 1.1 mrg &polarity) != 0) {
453 1.1 mrg aprint_error(": could not get TSHUT polarity, default to low");
454 1.1 mrg polarity = TSHUT_LOW_ACTIVE;
455 1.1 mrg }
456 1.1 mrg if (of_getprop_uint32(phandle,
457 1.1 mrg "rockchip,hw-tshut-temp", &tshut_temp) != 0) {
458 1.1 mrg aprint_error(": could not get TSHUT temperature, default to %u",
459 1.1 mrg TSHUT_DEF_TEMP);
460 1.1 mrg tshut_temp = TSHUT_DEF_TEMP;
461 1.1 mrg }
462 1.1 mrg tshut_temp *= 1000; /* convert fdt ms -> us */
463 1.1 mrg
464 1.1 mrg memcpy(sc->sc_sensors, rk_tsadc_sensors, sizeof(sc->sc_sensors));
465 1.5 mrg for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
466 1.1 mrg struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
467 1.1 mrg
468 1.1 mrg rks->s_data.flags = ENVSYS_FMONLIMITS;
469 1.1 mrg rks->s_data.units = ENVSYS_STEMP;
470 1.1 mrg rks->s_data.state = ENVSYS_SINVALID;
471 1.1 mrg
472 1.1 mrg if (sysmon_envsys_sensor_attach(sc->sc_sme, &rks->s_data))
473 1.1 mrg goto fail;
474 1.1 mrg rks->s_attached = true;
475 1.1 mrg rks->s_tshut = tshut_temp;
476 1.3 mrg #if 0
477 1.1 mrg // testing
478 1.2 mrg rks->s_tshut = 68000000;
479 1.2 mrg rks->s_warn = 61000000;
480 1.1 mrg #endif
481 1.1 mrg }
482 1.1 mrg
483 1.1 mrg sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf");
484 1.1 mrg if (sc->sc_syscon == NULL) {
485 1.1 mrg aprint_error(": couldn't get grf syscon\n");
486 1.1 mrg goto fail;
487 1.1 mrg }
488 1.1 mrg if (fdtbus_get_reg(phandle, 0, &addr, &sc->sc_size) != 0) {
489 1.1 mrg aprint_error(": couldn't get registers\n");
490 1.1 mrg sc->sc_size = 0;
491 1.1 mrg goto fail;
492 1.1 mrg }
493 1.1 mrg if (bus_space_map(sc->sc_bst, addr, sc->sc_size, 0, &sc->sc_bsh) != 0) {
494 1.1 mrg aprint_error(": couldn't map registers\n");
495 1.1 mrg sc->sc_size = 0;
496 1.1 mrg goto fail;
497 1.1 mrg }
498 1.1 mrg
499 1.1 mrg if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
500 1.1 mrg aprint_error(": failed to decode interrupt\n");
501 1.1 mrg goto fail;
502 1.1 mrg }
503 1.1 mrg
504 1.1 mrg sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
505 1.1 mrg rk_tsadc_intr, sc);
506 1.1 mrg if (sc->sc_ih == NULL) {
507 1.1 mrg aprint_error_dev(self, "couldn't establish interrupt on %s\n",
508 1.1 mrg intrstr);
509 1.1 mrg goto fail;
510 1.1 mrg }
511 1.1 mrg aprint_normal_dev(self, "interrupting on %s\n", intrstr);
512 1.1 mrg
513 1.1 mrg if (rk_tsadc_init_clocks(sc)) {
514 1.1 mrg aprint_error(": couldn't enable clocks\n");
515 1.1 mrg return;
516 1.1 mrg }
517 1.1 mrg
518 1.1 mrg /*
519 1.1 mrg * Manual says to setup auto period (both), high temp (interrupt),
520 1.1 mrg * high temp (shutdown), enable high temp resets (TSHUT to GPIO
521 1.1 mrg * or reset chip), set the debounce times, and, finally, enable the
522 1.1 mrg * controller iself.
523 1.1 mrg */
524 1.4 mrg rk_tsadc_init(sc, mode, polarity);
525 1.1 mrg
526 1.1 mrg return;
527 1.1 mrg
528 1.1 mrg fail:
529 1.1 mrg rk_tsadc_detach(self, 0);
530 1.1 mrg }
531 1.1 mrg
532 1.1 mrg static int
533 1.1 mrg rk_tsadc_detach(device_t self, int flags)
534 1.1 mrg {
535 1.1 mrg struct rk_tsadc_softc *sc = device_private(self);
536 1.1 mrg
537 1.1 mrg pmf_device_deregister(self);
538 1.1 mrg
539 1.5 mrg for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
540 1.1 mrg struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
541 1.1 mrg
542 1.1 mrg if (rks->s_attached) {
543 1.1 mrg sysmon_envsys_sensor_detach(sc->sc_sme, &rks->s_data);
544 1.1 mrg rks->s_attached = false;
545 1.1 mrg }
546 1.1 mrg }
547 1.1 mrg
548 1.1 mrg sysmon_envsys_unregister(sc->sc_sme);
549 1.1 mrg
550 1.1 mrg if (sc->sc_clockapb)
551 1.1 mrg clk_disable(sc->sc_clockapb);
552 1.1 mrg if (sc->sc_clock)
553 1.1 mrg clk_disable(sc->sc_clock);
554 1.1 mrg
555 1.1 mrg if (sc->sc_ih)
556 1.1 mrg fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih);
557 1.1 mrg
558 1.1 mrg if (sc->sc_size)
559 1.1 mrg bus_space_unmap(sc->sc_bst, sc->sc_bsh, sc->sc_size);
560 1.1 mrg
561 1.1 mrg sysmon_envsys_destroy(sc->sc_sme);
562 1.1 mrg
563 1.1 mrg return 0;
564 1.1 mrg }
565 1.1 mrg
566 1.1 mrg static int
567 1.1 mrg rk_tsadc_init_clocks(struct rk_tsadc_softc *sc)
568 1.1 mrg {
569 1.1 mrg int error;
570 1.1 mrg
571 1.1 mrg fdtbus_clock_assign(sc->sc_phandle);
572 1.1 mrg
573 1.1 mrg sc->sc_reset = fdtbus_reset_get(sc->sc_phandle, "tsadc-apb");
574 1.1 mrg sc->sc_clock = fdtbus_clock_get(sc->sc_phandle, "tsadc");
575 1.1 mrg sc->sc_clockapb = fdtbus_clock_get(sc->sc_phandle, "apb_pclk");
576 1.1 mrg if (sc->sc_reset == NULL ||
577 1.1 mrg sc->sc_clock == NULL ||
578 1.1 mrg sc->sc_clockapb == NULL)
579 1.1 mrg return EINVAL;
580 1.1 mrg
581 1.1 mrg fdtbus_reset_assert(sc->sc_reset);
582 1.1 mrg
583 1.1 mrg error = clk_enable(sc->sc_clock);
584 1.1 mrg if (error) {
585 1.1 mrg fdtbus_reset_deassert(sc->sc_reset);
586 1.1 mrg return error;
587 1.1 mrg }
588 1.1 mrg
589 1.1 mrg error = clk_enable(sc->sc_clockapb);
590 1.1 mrg
591 1.1 mrg DELAY(20);
592 1.1 mrg fdtbus_reset_deassert(sc->sc_reset);
593 1.1 mrg
594 1.1 mrg return error;
595 1.1 mrg }
596 1.1 mrg
597 1.1 mrg static void
598 1.1 mrg rk_tsadc_init_counts(struct rk_tsadc_softc *sc)
599 1.1 mrg {
600 1.1 mrg
601 1.5 mrg TSADC_WRITE(sc, TSADC_AUTO_PERIOD, sc->sc_rd->rd_auto_period);
602 1.5 mrg TSADC_WRITE(sc, TSADC_AUTO_PERIOD_HT, sc->sc_rd->rd_auto_period);
603 1.1 mrg TSADC_WRITE(sc, TSADC_HIGH_INT_DEBOUNCE, TSADC_HT_DEBOUNCE_COUNT);
604 1.1 mrg TSADC_WRITE(sc, TSADC_HIGH_TSHUT_DEBOUNCE, TSADC_HT_DEBOUNCE_COUNT);
605 1.1 mrg }
606 1.1 mrg
607 1.1 mrg /* Configure the hardware with the tshut setup. */
608 1.1 mrg static void
609 1.1 mrg rk_tsadc_tshut_set(struct rk_tsadc_softc *sc)
610 1.1 mrg {
611 1.1 mrg uint32_t val = TSADC_READ(sc, TSADC_AUTO_CON);
612 1.1 mrg
613 1.5 mrg for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
614 1.1 mrg struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
615 1.5 mrg uint32_t data, warndata;
616 1.5 mrg
617 1.5 mrg if (!rks->s_attached)
618 1.5 mrg continue;
619 1.5 mrg
620 1.5 mrg data = rk_tsadc_temp_to_data(sc, rks->s_tshut);
621 1.5 mrg warndata = rk_tsadc_temp_to_data(sc, rks->s_warn);
622 1.1 mrg
623 1.1 mrg DPRINTF("(%s:%s): tshut/data %d/%u warn/data %d/%u",
624 1.1 mrg sc->sc_sme->sme_name, rks->s_data.desc,
625 1.1 mrg rks->s_tshut, data,
626 1.1 mrg rks->s_warn, warndata);
627 1.1 mrg
628 1.1 mrg if (data == sc->sc_data_mask) {
629 1.1 mrg aprint_error_dev(sc->sc_dev,
630 1.1 mrg "Failed converting critical temp %u.%06u to code",
631 1.1 mrg rks->s_tshut / 1000000, rks->s_tshut % 1000000);
632 1.1 mrg continue;
633 1.1 mrg }
634 1.1 mrg if (warndata == sc->sc_data_mask) {
635 1.1 mrg aprint_error_dev(sc->sc_dev,
636 1.1 mrg "Failed converting warn temp %u.%06u to code",
637 1.1 mrg rks->s_warn / 1000000, rks->s_warn % 1000000);
638 1.1 mrg continue;
639 1.1 mrg }
640 1.1 mrg
641 1.1 mrg TSADC_WRITE(sc, rks->s_comp_tshut, data);
642 1.1 mrg TSADC_WRITE(sc, rks->s_comp_int, warndata);
643 1.1 mrg
644 1.1 mrg val |= rks->s_comp_int_en;
645 1.1 mrg }
646 1.1 mrg TSADC_WRITE(sc, TSADC_AUTO_CON, val);
647 1.1 mrg }
648 1.1 mrg
649 1.1 mrg static void
650 1.1 mrg rk_tsadc_init_tshut(struct rk_tsadc_softc *sc, int mode, int polarity)
651 1.1 mrg {
652 1.1 mrg uint32_t val;
653 1.1 mrg
654 1.1 mrg /* Handle TSHUT temp setting. */
655 1.1 mrg rk_tsadc_tshut_set(sc);
656 1.1 mrg
657 1.1 mrg /* Handle TSHUT mode setting. */
658 1.1 mrg val = TSADC_READ(sc, TSADC_INT_EN);
659 1.1 mrg if (mode == TSHUT_MODE_CPU) {
660 1.1 mrg val |= TSADC_INT_EN_TSHUT_2CRU_EN_SRC1 |
661 1.1 mrg TSADC_INT_EN_TSHUT_2CRU_EN_SRC0;
662 1.1 mrg val &= ~(TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1 |
663 1.1 mrg TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0);
664 1.1 mrg } else {
665 1.1 mrg KASSERT(mode == TSHUT_MODE_GPIO);
666 1.1 mrg val &= ~(TSADC_INT_EN_TSHUT_2CRU_EN_SRC1 |
667 1.1 mrg TSADC_INT_EN_TSHUT_2CRU_EN_SRC0);
668 1.1 mrg val &= TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1 |
669 1.1 mrg TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0;
670 1.1 mrg }
671 1.1 mrg TSADC_WRITE(sc, TSADC_INT_EN, val);
672 1.1 mrg
673 1.1 mrg /* Handle TSHUT polarity setting. */
674 1.1 mrg val = TSADC_READ(sc, TSADC_AUTO_CON);
675 1.1 mrg if (polarity == TSHUT_HIGH_ACTIVE)
676 1.1 mrg val |= TSADC_AUTO_CON_TSHUT_POLARITY;
677 1.1 mrg else
678 1.1 mrg val &= ~TSADC_AUTO_CON_TSHUT_POLARITY;
679 1.1 mrg TSADC_WRITE(sc, TSADC_AUTO_CON, val);
680 1.1 mrg }
681 1.1 mrg
682 1.1 mrg static void
683 1.4 mrg rk_tsadc_init_rk3328(struct rk_tsadc_softc *sc, int mode, int polarity)
684 1.4 mrg {
685 1.4 mrg
686 1.4 mrg rk_tsadc_init_tshut(sc, mode, polarity);
687 1.4 mrg rk_tsadc_init_counts(sc);
688 1.4 mrg }
689 1.4 mrg
690 1.4 mrg static void
691 1.4 mrg rk_tsadc_init_rk3399(struct rk_tsadc_softc *sc, int mode, int polarity)
692 1.1 mrg {
693 1.1 mrg
694 1.1 mrg syscon_lock(sc->sc_syscon);
695 1.1 mrg syscon_write_4(sc->sc_syscon, RK3399_GRF_TSADC_TESTBIT_L,
696 1.1 mrg RK3399_GRF_TSADC_TESTBIT_VCM_EN_L);
697 1.1 mrg syscon_write_4(sc->sc_syscon, RK3399_GRF_TSADC_TESTBIT_H,
698 1.1 mrg RK3399_GRF_TSADC_TESTBIT_VCM_EN_H);
699 1.1 mrg
700 1.1 mrg DELAY(20);
701 1.1 mrg syscon_write_4(sc->sc_syscon, RK3399_GRF_SARADC_TESTBIT,
702 1.1 mrg RK3399_GRF_SARADC_TESTBIT_ON);
703 1.1 mrg syscon_write_4(sc->sc_syscon, RK3399_GRF_TSADC_TESTBIT_H,
704 1.1 mrg RK3399_GRF_TSADC_TESTBIT_H_ON);
705 1.1 mrg DELAY(100);
706 1.1 mrg syscon_unlock(sc->sc_syscon);
707 1.4 mrg
708 1.4 mrg rk_tsadc_init_counts(sc);
709 1.4 mrg rk_tsadc_init_tshut(sc, mode, polarity);
710 1.1 mrg }
711 1.1 mrg
712 1.1 mrg static void
713 1.1 mrg rk_tsadc_init_enable(struct rk_tsadc_softc *sc)
714 1.1 mrg {
715 1.1 mrg uint32_t val;
716 1.1 mrg
717 1.1 mrg val = TSADC_READ(sc, TSADC_AUTO_CON);
718 1.1 mrg val |= TSADC_AUTO_CON_AUTO_STATUS |
719 1.2 mrg TSADC_AUTO_CON_SRC1_LT_EN | TSADC_AUTO_CON_SRC0_LT_EN;
720 1.1 mrg TSADC_WRITE(sc, TSADC_AUTO_CON, val);
721 1.1 mrg
722 1.1 mrg /* Finally, register & enable the controller */
723 1.1 mrg sysmon_envsys_register(sc->sc_sme);
724 1.1 mrg
725 1.1 mrg val = TSADC_READ(sc, TSADC_AUTO_CON);
726 1.1 mrg val |= TSADC_AUTO_CON_AUTO_EN | TSADC_AUTO_CON_Q_SEL;
727 1.1 mrg TSADC_WRITE(sc, TSADC_AUTO_CON, val);
728 1.1 mrg }
729 1.1 mrg
730 1.4 mrg static void
731 1.4 mrg rk_tsadc_init(struct rk_tsadc_softc *sc, int mode, int polarity)
732 1.4 mrg {
733 1.4 mrg
734 1.5 mrg (*sc->sc_rd->rd_init)(sc, mode, polarity);
735 1.4 mrg rk_tsadc_init_enable(sc);
736 1.4 mrg }
737 1.4 mrg
738 1.1 mrg /* run time support */
739 1.1 mrg
740 1.5 mrg /* given edata, find the matching rk sensor structure */
741 1.1 mrg static struct rk_tsadc_sensor *
742 1.1 mrg rk_tsadc_edata_to_sensor(struct rk_tsadc_softc * const sc, envsys_data_t *edata)
743 1.1 mrg {
744 1.4 mrg
745 1.5 mrg for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
746 1.1 mrg struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
747 1.1 mrg
748 1.1 mrg if (&rks->s_data == edata)
749 1.1 mrg return rks;
750 1.1 mrg }
751 1.1 mrg return NULL;
752 1.1 mrg }
753 1.1 mrg
754 1.1 mrg static void
755 1.1 mrg rk_tsadc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
756 1.1 mrg {
757 1.1 mrg struct rk_tsadc_softc * const sc = sme->sme_cookie;
758 1.1 mrg struct rk_tsadc_sensor *rks = rk_tsadc_edata_to_sensor(sc, edata);
759 1.1 mrg unsigned data;
760 1.1 mrg int temp;
761 1.1 mrg
762 1.1 mrg if (rks == NULL)
763 1.1 mrg return;
764 1.1 mrg
765 1.1 mrg data = TSADC_READ(sc, rks->s_data_reg) & sc->sc_data_mask;
766 1.1 mrg temp = rk_tsadc_data_to_temp(sc, data);
767 1.1 mrg
768 1.4 mrg DPRINTF("(%s:%s): temp/data %d/%u",
769 1.4 mrg sc->sc_sme->sme_name, rks->s_data.desc,
770 1.4 mrg temp, data);
771 1.4 mrg
772 1.1 mrg if (temp == sc->sc_data_mask) {
773 1.1 mrg edata->state = ENVSYS_SINVALID;
774 1.1 mrg } else {
775 1.1 mrg edata->value_cur = temp + TEMP_uC_TO_uK;
776 1.1 mrg edata->state = ENVSYS_SVALID;
777 1.1 mrg }
778 1.1 mrg }
779 1.1 mrg
780 1.1 mrg static void
781 1.1 mrg rk_tsadc_get_limits(struct sysmon_envsys *sme,
782 1.1 mrg envsys_data_t *edata,
783 1.1 mrg sysmon_envsys_lim_t *lim,
784 1.1 mrg uint32_t *props)
785 1.1 mrg {
786 1.1 mrg struct rk_tsadc_softc *sc = sme->sme_cookie;
787 1.1 mrg struct rk_tsadc_sensor *rks = rk_tsadc_edata_to_sensor(sc, edata);
788 1.1 mrg
789 1.1 mrg if (rks == NULL)
790 1.1 mrg return;
791 1.1 mrg
792 1.1 mrg lim->sel_critmax = rks->s_tshut + TEMP_uC_TO_uK;
793 1.1 mrg lim->sel_warnmax = rks->s_warn + TEMP_uC_TO_uK;
794 1.1 mrg
795 1.1 mrg *props = PROP_CRITMAX | PROP_WARNMAX;
796 1.1 mrg }
797 1.1 mrg
798 1.1 mrg /* XXX do something with interrupts that don't happen yet. */
799 1.1 mrg static int
800 1.1 mrg rk_tsadc_intr(void *arg)
801 1.1 mrg {
802 1.1 mrg struct rk_tsadc_softc * const sc = arg;
803 1.1 mrg uint32_t val;
804 1.1 mrg
805 1.1 mrg /* XXX */
806 1.1 mrg DPRINTF("(%s): interrupted", sc->sc_sme->sme_name);
807 1.6 joerg for (unsigned n = 0; n < __arraycount(rk_tsadc_sensors); n++) {
808 1.1 mrg struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
809 1.1 mrg
810 1.1 mrg rk_tsadc_refresh(sc->sc_sme, (envsys_data_t *)rks);
811 1.1 mrg }
812 1.1 mrg
813 1.1 mrg /* ack interrupt */
814 1.1 mrg val = TSADC_READ(sc, TSADC_INT_PD);
815 1.1 mrg TSADC_WRITE(sc, TSADC_INT_PD, val & ~TSADC_INT_PD_EOC_INT_PD);
816 1.1 mrg
817 1.1 mrg return 1;
818 1.1 mrg }
819 1.1 mrg
820 1.1 mrg /*
821 1.1 mrg * Convert TDASC data codes to temp and reverse. The manual only has codes
822 1.1 mrg * and temperature values in 5 degC intervals, but says that interpolation
823 1.1 mrg * can be done to achieve better resolution between these values, and that
824 1.1 mrg * the spacing is linear.
825 1.1 mrg */
826 1.1 mrg static int
827 1.1 mrg rk_tsadc_data_to_temp(struct rk_tsadc_softc *sc, uint32_t data)
828 1.1 mrg {
829 1.1 mrg unsigned i;
830 1.5 mrg const rk_data *rd = sc->sc_rd;
831 1.1 mrg
832 1.5 mrg if (data > rd->rd_max || data < rd->rd_min) {
833 1.5 mrg DPRINTF("data out of range (%u > %u || %u < %u)",
834 1.5 mrg data, rd->rd_max, data, rd->rd_min);
835 1.4 mrg return sc->sc_data_mask;
836 1.4 mrg }
837 1.5 mrg for (i = 1; i < rd->rd_size; i++) {
838 1.5 mrg if (rd->rd_array[i].data >= data) {
839 1.2 mrg int temprange, offset;
840 1.2 mrg uint32_t datarange, datadiff;
841 1.4 mrg unsigned first, secnd;
842 1.2 mrg
843 1.5 mrg if (rd->rd_array[i].data == data)
844 1.5 mrg return rd->rd_array[i].temp;
845 1.2 mrg
846 1.2 mrg /* must interpolate */
847 1.5 mrg if (rd->rd_decr) {
848 1.4 mrg first = i;
849 1.4 mrg secnd = i+1;
850 1.4 mrg } else {
851 1.4 mrg first = i;
852 1.4 mrg secnd = i-1;
853 1.4 mrg }
854 1.4 mrg
855 1.5 mrg temprange = rd->rd_array[first].temp -
856 1.5 mrg rd->rd_array[secnd].temp;
857 1.5 mrg datarange = rd->rd_array[first].data -
858 1.5 mrg rd->rd_array[secnd].data;
859 1.5 mrg datadiff = data - rd->rd_array[secnd].data;
860 1.2 mrg
861 1.2 mrg offset = (temprange * datadiff) / datarange;
862 1.5 mrg return rd->rd_array[secnd].temp + offset;
863 1.1 mrg }
864 1.1 mrg }
865 1.4 mrg panic("didn't find range");
866 1.1 mrg }
867 1.1 mrg
868 1.1 mrg static uint32_t
869 1.1 mrg rk_tsadc_temp_to_data(struct rk_tsadc_softc *sc, int temp)
870 1.1 mrg {
871 1.1 mrg unsigned i;
872 1.5 mrg const rk_data *rd = sc->sc_rd;
873 1.1 mrg
874 1.5 mrg for (i = 1; i < rd->rd_size; i++) {
875 1.5 mrg if (rd->rd_array[i].temp >= temp) {
876 1.2 mrg int temprange, tempdiff;
877 1.2 mrg uint32_t datarange, offset;
878 1.4 mrg unsigned first, secnd;
879 1.2 mrg
880 1.5 mrg if (rd->rd_array[i].temp == temp)
881 1.5 mrg return rd->rd_array[i].data;
882 1.2 mrg
883 1.2 mrg /* must interpolate */
884 1.5 mrg if (rd->rd_decr) {
885 1.4 mrg first = i;
886 1.4 mrg secnd = i+1;
887 1.4 mrg } else {
888 1.4 mrg first = i;
889 1.4 mrg secnd = i-1;
890 1.4 mrg }
891 1.4 mrg
892 1.5 mrg datarange = rd->rd_array[first].data -
893 1.5 mrg rd->rd_array[secnd].data;
894 1.5 mrg temprange = rd->rd_array[first].temp -
895 1.5 mrg rd->rd_array[secnd].temp;
896 1.5 mrg tempdiff = temp - rd->rd_array[secnd].temp;
897 1.2 mrg
898 1.2 mrg offset = (datarange * tempdiff) / temprange;
899 1.5 mrg return rd->rd_array[secnd].data + offset;
900 1.1 mrg }
901 1.1 mrg }
902 1.1 mrg
903 1.1 mrg return sc->sc_data_mask;
904 1.1 mrg }
905