rk_usb.c revision 1.2.2.4
1 1.2.2.4 pgoyette /* $NetBSD: rk_usb.c,v 1.2.2.4 2018/09/06 06:55:27 pgoyette Exp $ */ 2 1.2.2.2 pgoyette 3 1.2.2.2 pgoyette /*- 4 1.2.2.2 pgoyette * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 1.2.2.2 pgoyette * All rights reserved. 6 1.2.2.2 pgoyette * 7 1.2.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 pgoyette * modification, are permitted provided that the following conditions 9 1.2.2.2 pgoyette * are met: 10 1.2.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 pgoyette * documentation and/or other materials provided with the distribution. 15 1.2.2.2 pgoyette * 16 1.2.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 1.2.2.2 pgoyette * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.2.2.2 pgoyette * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.2.2.2 pgoyette * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 1.2.2.2 pgoyette * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.2.2.2 pgoyette * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.2.2.2 pgoyette * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.2.2.2 pgoyette * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.2.2.2 pgoyette * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.2.2.2 pgoyette * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.2.2.2 pgoyette * POSSIBILITY OF SUCH DAMAGE. 27 1.2.2.2 pgoyette */ 28 1.2.2.2 pgoyette 29 1.2.2.2 pgoyette #include <sys/cdefs.h> 30 1.2.2.2 pgoyette 31 1.2.2.4 pgoyette __KERNEL_RCSID(0, "$NetBSD: rk_usb.c,v 1.2.2.4 2018/09/06 06:55:27 pgoyette Exp $"); 32 1.2.2.2 pgoyette 33 1.2.2.2 pgoyette #include <sys/param.h> 34 1.2.2.2 pgoyette #include <sys/bus.h> 35 1.2.2.2 pgoyette #include <sys/device.h> 36 1.2.2.2 pgoyette #include <sys/intr.h> 37 1.2.2.2 pgoyette #include <sys/systm.h> 38 1.2.2.2 pgoyette #include <sys/time.h> 39 1.2.2.2 pgoyette #include <sys/kmem.h> 40 1.2.2.2 pgoyette 41 1.2.2.2 pgoyette #include <dev/clk/clk_backend.h> 42 1.2.2.2 pgoyette 43 1.2.2.2 pgoyette #include <dev/fdt/fdtvar.h> 44 1.2.2.3 pgoyette #include <dev/fdt/syscon.h> 45 1.2.2.2 pgoyette 46 1.2.2.2 pgoyette static int rk_usb_match(device_t, cfdata_t, void *); 47 1.2.2.2 pgoyette static void rk_usb_attach(device_t, device_t, void *); 48 1.2.2.2 pgoyette 49 1.2.2.4 pgoyette #define RK3328_CON0_REG 0x100 50 1.2.2.4 pgoyette #define RK3328_CON1_REG 0x104 51 1.2.2.4 pgoyette #define RK3328_CON2_REG 0x108 52 1.2.2.4 pgoyette #define RK3328_USBPHY_COMMONONN __BIT(4) 53 1.2.2.4 pgoyette 54 1.2.2.4 pgoyette #define RK3399_GRF_USB20_PHY0_CON0_REG 0x0e450 55 1.2.2.4 pgoyette #define RK3399_GRF_USB20_PHY1_CON0_REG 0x0e460 56 1.2.2.4 pgoyette #define RK3399_USBPHY_COMMONONN __BIT(4) 57 1.2.2.4 pgoyette #define RK3399_GRF_USB20_PHY0_CON1_REG 0x0e454 58 1.2.2.4 pgoyette #define RK3399_GRF_USB20_PHY1_CON1_REG 0x0e464 59 1.2.2.4 pgoyette #define RK3399_GRF_USB20_PHY0_CON2_REG 0x0e458 60 1.2.2.4 pgoyette #define RK3399_GRF_USB20_PHY1_CON2_REG 0x0e468 61 1.2.2.4 pgoyette #define RK3399_USBPHY_SUSPEND_N __BIT(1) 62 1.2.2.4 pgoyette #define RK3399_USBPHY_UTMI_SEL __BIT(0) 63 1.2.2.4 pgoyette 64 1.2.2.4 pgoyette #define RK3399_PHY_NO(_sc) ((_sc)->sc_reg == 0xe450 ? 0 : 1) 65 1.2.2.2 pgoyette 66 1.2.2.2 pgoyette enum rk_usb_type { 67 1.2.2.2 pgoyette USB_RK3328 = 1, 68 1.2.2.4 pgoyette USB_RK3399, 69 1.2.2.2 pgoyette }; 70 1.2.2.2 pgoyette 71 1.2.2.2 pgoyette static const struct of_compat_data compat_data[] = { 72 1.2.2.2 pgoyette { "rockchip,rk3328-usb2phy", USB_RK3328 }, 73 1.2.2.4 pgoyette { "rockchip,rk3399-usb2phy", USB_RK3399 }, 74 1.2.2.2 pgoyette { NULL } 75 1.2.2.2 pgoyette }; 76 1.2.2.2 pgoyette 77 1.2.2.2 pgoyette struct rk_usb_clk { 78 1.2.2.2 pgoyette struct clk base; 79 1.2.2.2 pgoyette }; 80 1.2.2.2 pgoyette 81 1.2.2.2 pgoyette struct rk_usb_softc { 82 1.2.2.2 pgoyette device_t sc_dev; 83 1.2.2.3 pgoyette struct syscon *sc_syscon; 84 1.2.2.2 pgoyette enum rk_usb_type sc_type; 85 1.2.2.2 pgoyette 86 1.2.2.2 pgoyette struct clk_domain sc_clkdom; 87 1.2.2.2 pgoyette struct rk_usb_clk sc_usbclk; 88 1.2.2.4 pgoyette 89 1.2.2.4 pgoyette bus_addr_t sc_reg; 90 1.2.2.2 pgoyette }; 91 1.2.2.2 pgoyette 92 1.2.2.2 pgoyette CFATTACH_DECL_NEW(rk_usb, sizeof(struct rk_usb_softc), 93 1.2.2.2 pgoyette rk_usb_match, rk_usb_attach, NULL, NULL); 94 1.2.2.2 pgoyette 95 1.2.2.2 pgoyette static struct clk * 96 1.2.2.2 pgoyette rk_usb_clk_get(void *priv, const char *name) 97 1.2.2.2 pgoyette { 98 1.2.2.2 pgoyette struct rk_usb_softc * const sc = priv; 99 1.2.2.2 pgoyette 100 1.2.2.2 pgoyette if (strcmp(name, sc->sc_usbclk.base.name) != 0) 101 1.2.2.2 pgoyette return NULL; 102 1.2.2.2 pgoyette 103 1.2.2.2 pgoyette return &sc->sc_usbclk.base; 104 1.2.2.2 pgoyette } 105 1.2.2.2 pgoyette 106 1.2.2.2 pgoyette static void 107 1.2.2.2 pgoyette rk_usb_clk_put(void *priv, struct clk *clk) 108 1.2.2.2 pgoyette { 109 1.2.2.2 pgoyette } 110 1.2.2.2 pgoyette 111 1.2.2.2 pgoyette static u_int 112 1.2.2.2 pgoyette rk_usb_clk_get_rate(void *priv, struct clk *clk) 113 1.2.2.2 pgoyette { 114 1.2.2.2 pgoyette return 480000000; 115 1.2.2.2 pgoyette } 116 1.2.2.2 pgoyette 117 1.2.2.2 pgoyette static int 118 1.2.2.2 pgoyette rk_usb_clk_enable(void *priv, struct clk *clk) 119 1.2.2.2 pgoyette { 120 1.2.2.2 pgoyette struct rk_usb_softc * const sc = priv; 121 1.2.2.4 pgoyette uint32_t reg, write_mask, write_val; 122 1.2.2.2 pgoyette 123 1.2.2.4 pgoyette switch (sc->sc_type) { 124 1.2.2.4 pgoyette case USB_RK3328: 125 1.2.2.4 pgoyette reg = RK3328_CON2_REG; 126 1.2.2.4 pgoyette write_mask = RK3328_USBPHY_COMMONONN << 16; 127 1.2.2.4 pgoyette write_val = 0; 128 1.2.2.4 pgoyette break; 129 1.2.2.4 pgoyette case USB_RK3399: 130 1.2.2.4 pgoyette reg = RK3399_PHY_NO(sc) == 0 ? 131 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY0_CON0_REG : 132 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY1_CON0_REG; 133 1.2.2.4 pgoyette write_mask = RK3399_USBPHY_COMMONONN << 16; 134 1.2.2.4 pgoyette write_val = 0; 135 1.2.2.4 pgoyette break; 136 1.2.2.4 pgoyette default: 137 1.2.2.4 pgoyette return ENXIO; 138 1.2.2.4 pgoyette } 139 1.2.2.3 pgoyette 140 1.2.2.3 pgoyette syscon_lock(sc->sc_syscon); 141 1.2.2.4 pgoyette syscon_write_4(sc->sc_syscon, reg, write_mask | write_val); 142 1.2.2.3 pgoyette syscon_unlock(sc->sc_syscon); 143 1.2.2.2 pgoyette 144 1.2.2.2 pgoyette return 0; 145 1.2.2.2 pgoyette } 146 1.2.2.2 pgoyette 147 1.2.2.2 pgoyette static int 148 1.2.2.2 pgoyette rk_usb_clk_disable(void *priv, struct clk *clk) 149 1.2.2.2 pgoyette { 150 1.2.2.2 pgoyette struct rk_usb_softc * const sc = priv; 151 1.2.2.4 pgoyette uint32_t reg, write_mask, write_val; 152 1.2.2.2 pgoyette 153 1.2.2.4 pgoyette switch (sc->sc_type) { 154 1.2.2.4 pgoyette case USB_RK3328: 155 1.2.2.4 pgoyette reg = RK3328_CON2_REG; 156 1.2.2.4 pgoyette write_mask = RK3328_USBPHY_COMMONONN << 16; 157 1.2.2.4 pgoyette write_val = RK3328_USBPHY_COMMONONN; 158 1.2.2.4 pgoyette break; 159 1.2.2.4 pgoyette case USB_RK3399: 160 1.2.2.4 pgoyette reg = RK3399_PHY_NO(sc) == 0 ? 161 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY0_CON0_REG : 162 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY1_CON0_REG; 163 1.2.2.4 pgoyette write_mask = RK3399_USBPHY_COMMONONN << 16; 164 1.2.2.4 pgoyette write_val = RK3399_USBPHY_COMMONONN; 165 1.2.2.4 pgoyette break; 166 1.2.2.4 pgoyette default: 167 1.2.2.4 pgoyette return ENXIO; 168 1.2.2.4 pgoyette } 169 1.2.2.3 pgoyette 170 1.2.2.3 pgoyette syscon_lock(sc->sc_syscon); 171 1.2.2.4 pgoyette syscon_write_4(sc->sc_syscon, reg, write_mask | write_val); 172 1.2.2.3 pgoyette syscon_unlock(sc->sc_syscon); 173 1.2.2.2 pgoyette 174 1.2.2.2 pgoyette return 0; 175 1.2.2.2 pgoyette } 176 1.2.2.2 pgoyette 177 1.2.2.2 pgoyette static const struct clk_funcs rk_usb_clk_funcs = { 178 1.2.2.2 pgoyette .get = rk_usb_clk_get, 179 1.2.2.2 pgoyette .put = rk_usb_clk_put, 180 1.2.2.2 pgoyette .get_rate = rk_usb_clk_get_rate, 181 1.2.2.2 pgoyette .enable = rk_usb_clk_enable, 182 1.2.2.2 pgoyette .disable = rk_usb_clk_disable, 183 1.2.2.2 pgoyette }; 184 1.2.2.2 pgoyette 185 1.2.2.2 pgoyette static struct clk * 186 1.2.2.2 pgoyette rk_usb_fdt_decode(device_t dev, const void *data, size_t len) 187 1.2.2.2 pgoyette { 188 1.2.2.2 pgoyette struct rk_usb_softc * const sc = device_private(dev); 189 1.2.2.2 pgoyette 190 1.2.2.2 pgoyette if (len != 0) 191 1.2.2.2 pgoyette return NULL; 192 1.2.2.2 pgoyette 193 1.2.2.2 pgoyette return &sc->sc_usbclk.base; 194 1.2.2.2 pgoyette } 195 1.2.2.2 pgoyette 196 1.2.2.2 pgoyette static const struct fdtbus_clock_controller_func rk_usb_fdt_funcs = { 197 1.2.2.2 pgoyette .decode = rk_usb_fdt_decode 198 1.2.2.2 pgoyette }; 199 1.2.2.2 pgoyette 200 1.2.2.2 pgoyette static int 201 1.2.2.2 pgoyette rk_usb_match(device_t parent, cfdata_t cf, void *aux) 202 1.2.2.2 pgoyette { 203 1.2.2.2 pgoyette struct fdt_attach_args * const faa = aux; 204 1.2.2.2 pgoyette 205 1.2.2.2 pgoyette return of_match_compat_data(faa->faa_phandle, compat_data); 206 1.2.2.2 pgoyette } 207 1.2.2.2 pgoyette 208 1.2.2.2 pgoyette static void 209 1.2.2.2 pgoyette rk_usb_attach(device_t parent, device_t self, void *aux) 210 1.2.2.2 pgoyette { 211 1.2.2.2 pgoyette struct rk_usb_softc * const sc = device_private(self); 212 1.2.2.2 pgoyette struct fdt_attach_args * const faa = aux; 213 1.2.2.2 pgoyette const int phandle = faa->faa_phandle; 214 1.2.2.4 pgoyette struct clk *clk; 215 1.2.2.2 pgoyette int child; 216 1.2.2.2 pgoyette 217 1.2.2.4 pgoyette /* Cache the base address of this PHY so we know which instance we are */ 218 1.2.2.4 pgoyette if (fdtbus_get_reg(phandle, 0, &sc->sc_reg, NULL) != 0) { 219 1.2.2.4 pgoyette aprint_error(": couldn't get registers\n"); 220 1.2.2.4 pgoyette return; 221 1.2.2.4 pgoyette } 222 1.2.2.4 pgoyette 223 1.2.2.4 pgoyette clk = fdtbus_clock_get(phandle, "phyclk"); 224 1.2.2.4 pgoyette if (clk && clk_enable(clk) != 0) { 225 1.2.2.4 pgoyette aprint_error(": couldn't enable phy clock\n"); 226 1.2.2.4 pgoyette return; 227 1.2.2.4 pgoyette } 228 1.2.2.4 pgoyette 229 1.2.2.2 pgoyette sc->sc_dev = self; 230 1.2.2.2 pgoyette sc->sc_type = of_search_compatible(phandle, compat_data)->data; 231 1.2.2.3 pgoyette sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle)); 232 1.2.2.3 pgoyette if (sc->sc_syscon == NULL) { 233 1.2.2.3 pgoyette aprint_error(": couldn't get grf syscon\n"); 234 1.2.2.2 pgoyette return; 235 1.2.2.2 pgoyette } 236 1.2.2.2 pgoyette 237 1.2.2.2 pgoyette const char *clkname = fdtbus_get_string(phandle, "clock-output-names"); 238 1.2.2.2 pgoyette if (clkname == NULL) 239 1.2.2.2 pgoyette clkname = faa->faa_name; 240 1.2.2.2 pgoyette 241 1.2.2.2 pgoyette sc->sc_clkdom.name = device_xname(self); 242 1.2.2.2 pgoyette sc->sc_clkdom.funcs = &rk_usb_clk_funcs; 243 1.2.2.2 pgoyette sc->sc_clkdom.priv = sc; 244 1.2.2.2 pgoyette sc->sc_usbclk.base.domain = &sc->sc_clkdom; 245 1.2.2.2 pgoyette sc->sc_usbclk.base.name = kmem_asprintf("%s", clkname); 246 1.2.2.2 pgoyette clk_attach(&sc->sc_usbclk.base); 247 1.2.2.2 pgoyette 248 1.2.2.2 pgoyette aprint_naive("\n"); 249 1.2.2.2 pgoyette aprint_normal(": USB2 PHY\n"); 250 1.2.2.2 pgoyette 251 1.2.2.2 pgoyette fdtbus_register_clock_controller(self, phandle, &rk_usb_fdt_funcs); 252 1.2.2.2 pgoyette 253 1.2.2.2 pgoyette for (child = OF_child(phandle); child; child = OF_peer(child)) { 254 1.2.2.2 pgoyette if (!fdtbus_status_okay(child)) 255 1.2.2.2 pgoyette continue; 256 1.2.2.2 pgoyette 257 1.2.2.2 pgoyette struct fdt_attach_args cfaa = *faa; 258 1.2.2.2 pgoyette cfaa.faa_phandle = child; 259 1.2.2.2 pgoyette cfaa.faa_name = fdtbus_get_string(child, "name"); 260 1.2.2.2 pgoyette cfaa.faa_quiet = false; 261 1.2.2.2 pgoyette 262 1.2.2.2 pgoyette config_found(self, &cfaa, NULL); 263 1.2.2.2 pgoyette } 264 1.2.2.2 pgoyette } 265 1.2.2.2 pgoyette 266 1.2.2.2 pgoyette /* 267 1.2.2.2 pgoyette * USB PHY 268 1.2.2.2 pgoyette */ 269 1.2.2.2 pgoyette 270 1.2.2.2 pgoyette static int rk_usbphy_match(device_t, cfdata_t, void *); 271 1.2.2.2 pgoyette static void rk_usbphy_attach(device_t, device_t, void *); 272 1.2.2.2 pgoyette 273 1.2.2.2 pgoyette struct rk_usbphy_softc { 274 1.2.2.2 pgoyette device_t sc_dev; 275 1.2.2.2 pgoyette int sc_phandle; 276 1.2.2.4 pgoyette struct fdtbus_regulator *sc_supply; 277 1.2.2.2 pgoyette }; 278 1.2.2.2 pgoyette 279 1.2.2.2 pgoyette CFATTACH_DECL_NEW(rk_usbphy, sizeof(struct rk_usbphy_softc), 280 1.2.2.2 pgoyette rk_usbphy_match, rk_usbphy_attach, NULL, NULL); 281 1.2.2.2 pgoyette 282 1.2.2.2 pgoyette static void * 283 1.2.2.2 pgoyette rk_usbphy_acquire(device_t dev, const void *data, size_t len) 284 1.2.2.2 pgoyette { 285 1.2.2.2 pgoyette struct rk_usbphy_softc * const sc = device_private(dev); 286 1.2.2.2 pgoyette 287 1.2.2.2 pgoyette if (len != 0) 288 1.2.2.2 pgoyette return NULL; 289 1.2.2.2 pgoyette 290 1.2.2.2 pgoyette return sc; 291 1.2.2.2 pgoyette } 292 1.2.2.2 pgoyette 293 1.2.2.2 pgoyette static void 294 1.2.2.2 pgoyette rk_usbphy_release(device_t dev, void *priv) 295 1.2.2.2 pgoyette { 296 1.2.2.2 pgoyette } 297 1.2.2.2 pgoyette 298 1.2.2.2 pgoyette static int 299 1.2.2.2 pgoyette rk_usbphy_otg_enable(device_t dev, void *priv, bool enable) 300 1.2.2.2 pgoyette { 301 1.2.2.4 pgoyette struct rk_usbphy_softc * const sc = device_private(dev); 302 1.2.2.2 pgoyette struct rk_usb_softc * const usb_sc = device_private(device_parent(dev)); 303 1.2.2.4 pgoyette uint32_t reg, write_mask, write_val; 304 1.2.2.4 pgoyette int error; 305 1.2.2.2 pgoyette 306 1.2.2.4 pgoyette switch (usb_sc->sc_type) { 307 1.2.2.4 pgoyette case USB_RK3328: 308 1.2.2.4 pgoyette reg = RK3328_CON0_REG; 309 1.2.2.4 pgoyette write_mask = 0x1ffU << 16; 310 1.2.2.4 pgoyette write_val = enable ? 0 : 0x1d1; 311 1.2.2.4 pgoyette break; 312 1.2.2.4 pgoyette case USB_RK3399: 313 1.2.2.4 pgoyette reg = RK3399_PHY_NO(usb_sc) == 0 ? 314 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY0_CON1_REG : 315 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY1_CON1_REG; 316 1.2.2.4 pgoyette write_mask = (RK3399_USBPHY_SUSPEND_N|RK3399_USBPHY_UTMI_SEL) << 16; 317 1.2.2.4 pgoyette write_val = enable ? 0 : RK3399_USBPHY_UTMI_SEL; 318 1.2.2.4 pgoyette break; 319 1.2.2.4 pgoyette default: 320 1.2.2.4 pgoyette return ENXIO; 321 1.2.2.4 pgoyette } 322 1.2.2.4 pgoyette 323 1.2.2.4 pgoyette if (sc->sc_supply) { 324 1.2.2.4 pgoyette error = enable ? fdtbus_regulator_enable(sc->sc_supply) : 325 1.2.2.4 pgoyette fdtbus_regulator_disable(sc->sc_supply); 326 1.2.2.4 pgoyette if (error != 0) 327 1.2.2.4 pgoyette return error; 328 1.2.2.4 pgoyette } 329 1.2.2.3 pgoyette 330 1.2.2.3 pgoyette syscon_lock(usb_sc->sc_syscon); 331 1.2.2.4 pgoyette syscon_write_4(usb_sc->sc_syscon, reg, write_mask | write_val); 332 1.2.2.3 pgoyette syscon_unlock(usb_sc->sc_syscon); 333 1.2.2.2 pgoyette 334 1.2.2.2 pgoyette return 0; 335 1.2.2.2 pgoyette } 336 1.2.2.2 pgoyette 337 1.2.2.2 pgoyette static int 338 1.2.2.2 pgoyette rk_usbphy_host_enable(device_t dev, void *priv, bool enable) 339 1.2.2.2 pgoyette { 340 1.2.2.4 pgoyette struct rk_usbphy_softc * const sc = device_private(dev); 341 1.2.2.2 pgoyette struct rk_usb_softc * const usb_sc = device_private(device_parent(dev)); 342 1.2.2.4 pgoyette uint32_t reg, write_mask, write_val; 343 1.2.2.4 pgoyette int error; 344 1.2.2.2 pgoyette 345 1.2.2.4 pgoyette switch (usb_sc->sc_type) { 346 1.2.2.4 pgoyette case USB_RK3328: 347 1.2.2.4 pgoyette reg = RK3328_CON1_REG; 348 1.2.2.4 pgoyette write_mask = 0x1ffU << 16; 349 1.2.2.4 pgoyette write_val = enable ? 0 : 0x1d1; 350 1.2.2.4 pgoyette break; 351 1.2.2.4 pgoyette case USB_RK3399: 352 1.2.2.4 pgoyette reg = RK3399_PHY_NO(usb_sc) == 0 ? 353 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY0_CON2_REG : 354 1.2.2.4 pgoyette RK3399_GRF_USB20_PHY1_CON2_REG; 355 1.2.2.4 pgoyette write_mask = (RK3399_USBPHY_SUSPEND_N|RK3399_USBPHY_UTMI_SEL) << 16; 356 1.2.2.4 pgoyette write_val = enable ? 0 : RK3399_USBPHY_UTMI_SEL; 357 1.2.2.4 pgoyette break; 358 1.2.2.4 pgoyette default: 359 1.2.2.4 pgoyette return ENXIO; 360 1.2.2.4 pgoyette } 361 1.2.2.4 pgoyette 362 1.2.2.4 pgoyette if (sc->sc_supply) { 363 1.2.2.4 pgoyette error = enable ? fdtbus_regulator_enable(sc->sc_supply) : 364 1.2.2.4 pgoyette fdtbus_regulator_disable(sc->sc_supply); 365 1.2.2.4 pgoyette if (error != 0) 366 1.2.2.4 pgoyette return error; 367 1.2.2.4 pgoyette } 368 1.2.2.3 pgoyette 369 1.2.2.3 pgoyette syscon_lock(usb_sc->sc_syscon); 370 1.2.2.4 pgoyette syscon_write_4(usb_sc->sc_syscon, reg, write_mask | write_val); 371 1.2.2.3 pgoyette syscon_unlock(usb_sc->sc_syscon); 372 1.2.2.2 pgoyette 373 1.2.2.2 pgoyette return 0; 374 1.2.2.2 pgoyette } 375 1.2.2.2 pgoyette 376 1.2.2.2 pgoyette const struct fdtbus_phy_controller_func rk_usbphy_otg_funcs = { 377 1.2.2.2 pgoyette .acquire = rk_usbphy_acquire, 378 1.2.2.2 pgoyette .release = rk_usbphy_release, 379 1.2.2.2 pgoyette .enable = rk_usbphy_otg_enable, 380 1.2.2.2 pgoyette }; 381 1.2.2.2 pgoyette 382 1.2.2.2 pgoyette const struct fdtbus_phy_controller_func rk_usbphy_host_funcs = { 383 1.2.2.2 pgoyette .acquire = rk_usbphy_acquire, 384 1.2.2.2 pgoyette .release = rk_usbphy_release, 385 1.2.2.2 pgoyette .enable = rk_usbphy_host_enable, 386 1.2.2.2 pgoyette }; 387 1.2.2.2 pgoyette 388 1.2.2.2 pgoyette static int 389 1.2.2.2 pgoyette rk_usbphy_match(device_t parent, cfdata_t cf, void *aux) 390 1.2.2.2 pgoyette { 391 1.2.2.2 pgoyette struct fdt_attach_args * const faa = aux; 392 1.2.2.2 pgoyette const int phandle = faa->faa_phandle; 393 1.2.2.2 pgoyette const char *name = fdtbus_get_string(phandle, "name"); 394 1.2.2.2 pgoyette 395 1.2.2.2 pgoyette if (strcmp(name, "otg-port") == 0 || strcmp(name, "host-port") == 0) 396 1.2.2.2 pgoyette return 1; 397 1.2.2.2 pgoyette 398 1.2.2.2 pgoyette return 0; 399 1.2.2.2 pgoyette } 400 1.2.2.2 pgoyette 401 1.2.2.2 pgoyette static void 402 1.2.2.2 pgoyette rk_usbphy_attach(device_t parent, device_t self, void *aux) 403 1.2.2.2 pgoyette { 404 1.2.2.2 pgoyette struct rk_usbphy_softc * const sc = device_private(self); 405 1.2.2.2 pgoyette struct fdt_attach_args * const faa = aux; 406 1.2.2.2 pgoyette const int phandle = faa->faa_phandle; 407 1.2.2.2 pgoyette const char *name = fdtbus_get_string(phandle, "name"); 408 1.2.2.2 pgoyette 409 1.2.2.2 pgoyette sc->sc_dev = self; 410 1.2.2.2 pgoyette sc->sc_phandle = phandle; 411 1.2.2.4 pgoyette if (of_hasprop(phandle, "phy-supply")) { 412 1.2.2.4 pgoyette sc->sc_supply = fdtbus_regulator_acquire(phandle, "phy-supply"); 413 1.2.2.4 pgoyette if (sc->sc_supply == NULL) { 414 1.2.2.4 pgoyette aprint_error(": couldn't acquire regulator\n"); 415 1.2.2.4 pgoyette return; 416 1.2.2.4 pgoyette } 417 1.2.2.4 pgoyette } 418 1.2.2.2 pgoyette 419 1.2.2.2 pgoyette aprint_naive("\n"); 420 1.2.2.2 pgoyette 421 1.2.2.2 pgoyette if (strcmp(name, "otg-port") == 0) { 422 1.2.2.2 pgoyette aprint_normal(": USB2 OTG port\n"); 423 1.2.2.2 pgoyette fdtbus_register_phy_controller(self, phandle, &rk_usbphy_otg_funcs); 424 1.2.2.2 pgoyette } else if (strcmp(name, "host-port") == 0) { 425 1.2.2.2 pgoyette aprint_normal(": USB2 host port\n"); 426 1.2.2.2 pgoyette fdtbus_register_phy_controller(self, phandle, &rk_usbphy_host_funcs); 427 1.2.2.2 pgoyette } 428 1.2.2.2 pgoyette } 429
Indexes created Wed Oct 15 16:09:53 GMT 2025