rk_vop.c revision 1.1
1 /* $NetBSD: rk_vop.c,v 1.1 2019/11/09 23:30:14 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_vop.c,v 1.1 2019/11/09 23:30:14 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/conf.h> 39 #include <sys/sysctl.h> 40 41 #include <drm/drmP.h> 42 #include <drm/drm_crtc.h> 43 #include <drm/drm_crtc_helper.h> 44 #include <drm/drm_plane_helper.h> 45 46 #include <dev/fdt/fdtvar.h> 47 #include <dev/fdt/fdt_port.h> 48 49 #include <arm/rockchip/rk_drm.h> 50 51 #define VOP_REG_CFG_DONE 0x0000 52 #define REG_LOAD_EN __BIT(0) 53 #define VOP_SYS_CTRL 0x0008 54 #define VOP_STANDBY_EN __BIT(22) 55 #define MIPI_OUT_EN __BIT(15) 56 #define EDP_OUT_EN __BIT(14) 57 #define HDMI_OUT_EN __BIT(13) 58 #define RGB_OUT_EN __BIT(12) 59 #define VOP_DSP_CTRL0 0x0010 60 #define DSP_OUT_MODE __BITS(3,0) 61 #define DSP_OUT_MODE_RGB888 0 62 #define DSP_OUT_MODE_RGBaaa 15 63 #define VOP_DSP_CTRL1 0x0014 64 #define VOP_WIN0_CTRL 0x0030 65 #define WIN0_LB_MODE __BITS(7,5) 66 #define WIN0_LB_MODE_RGB_3840X2 2 67 #define WIN0_LB_MODE_RGB_2560X4 3 68 #define WIN0_LB_MODE_RGB_1920X5 4 69 #define WIN0_LB_MODE_RGB_1280X8 5 70 #define WIN0_DATA_FMT __BITS(3,1) 71 #define WIN0_DATA_FMT_ARGB888 0 72 #define WIN0_EN __BIT(0) 73 #define VOP_WIN0_COLOR_KEY 0x0038 74 #define VOP_WIN0_VIR 0x003c 75 #define WIN0_VIR_STRIDE __BITS(13,0) 76 #define VOP_WIN0_YRGB_MST 0x0040 77 #define VOP_WIN0_ACT_INFO 0x0048 78 #define WIN0_ACT_HEIGHT __BITS(28,16) 79 #define WIN0_ACT_WIDTH __BITS(12,0) 80 #define VOP_WIN0_DSP_INFO 0x004c 81 #define WIN0_DSP_HEIGHT __BITS(27,16) 82 #define WIN0_DSP_WIDTH __BITS(11,0) 83 #define VOP_WIN0_DSP_ST 0x0050 84 #define WIN0_DSP_YST __BITS(28,16) 85 #define WIN0_DSP_XST __BITS(12,0) 86 #define VOP_POST_DSP_HACT_INFO 0x0170 87 #define DSP_HACT_ST_POST __BITS(28,16) 88 #define DSP_HACT_END_POST __BITS(12,0) 89 #define VOP_POST_DSP_VACT_INFO 0x0174 90 #define DSP_VACT_ST_POST __BITS(28,16) 91 #define DSP_VACT_END_POST __BITS(12,0) 92 #define VOP_DSP_HTOTAL_HS_END 0x0188 93 #define DSP_HTOTAL __BITS(28,16) 94 #define DSP_HS_END __BITS(12,0) 95 #define VOP_DSP_HACT_ST_END 0x018c 96 #define DSP_HACT_ST __BITS(28,16) 97 #define DSP_HACT_END __BITS(12,0) 98 #define VOP_DSP_VTOTAL_VS_END 0x0190 99 #define DSP_VTOTAL __BITS(28,16) 100 #define DSP_VS_END __BITS(12,0) 101 #define VOP_DSP_VACT_ST_END 0x0194 102 #define DSP_VACT_ST __BITS(28,16) 103 #define DSP_VACT_END __BITS(12,0) 104 105 /* 106 * Polarity fields are in different locations depending on SoC and output type, 107 * but always in the same order. 108 */ 109 #define DSP_DCLK_POL __BIT(3) 110 #define DSP_DEN_POL __BIT(2) 111 #define DSP_VSYNC_POL __BIT(1) 112 #define DSP_HSYNC_POL __BIT(0) 113 114 enum vop_ep_type { 115 VOP_EP_MIPI, 116 VOP_EP_EDP, 117 VOP_EP_HDMI, 118 VOP_EP_MIPI1, 119 VOP_EP_DP, 120 VOP_NEP 121 }; 122 123 struct rk_vop_softc; 124 struct rk_vop_config; 125 126 struct rk_vop_crtc { 127 struct drm_crtc base; 128 struct rk_vop_softc *sc; 129 }; 130 131 struct rk_vop_encoder { 132 struct drm_encoder base; 133 struct rk_vop_softc *sc; 134 enum vop_ep_type ep_type; 135 }; 136 137 struct rk_vop_softc { 138 device_t sc_dev; 139 bus_space_tag_t sc_bst; 140 bus_space_handle_t sc_bsh; 141 int sc_phandle; 142 143 struct clk *sc_dclk; 144 145 struct rk_vop_crtc sc_crtc; 146 struct rk_vop_encoder sc_encoder[VOP_NEP]; 147 148 struct fdt_device_ports sc_ports; 149 150 struct rk_vop_config *sc_conf; 151 }; 152 153 #define to_rk_vop_crtc(x) container_of(x, struct rk_vop_crtc, base) 154 #define to_rk_vop_encoder(x) container_of(x, struct rk_vop_encoder, base) 155 156 #define RD4(sc, reg) \ 157 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 158 #define WR4(sc, reg, val) \ 159 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 160 161 struct rk_vop_config { 162 const char *descr; 163 u_int out_mode; 164 void (*init)(struct rk_vop_softc *); 165 void (*set_polarity)(struct rk_vop_softc *, 166 enum vop_ep_type, uint32_t); 167 }; 168 169 #define RK3399_VOP_MIPI_POL __BITS(31,28) 170 #define RK3399_VOP_EDP_POL __BITS(27,24) 171 #define RK3399_VOP_HDMI_POL __BITS(23,20) 172 #define RK3399_VOP_DP_POL __BITS(19,16) 173 174 #define RK3399_VOP_SYS_CTRL_ENABLE __BIT(11) 175 176 static void 177 rk3399_vop_set_polarity(struct rk_vop_softc *sc, enum vop_ep_type ep_type, uint32_t pol) 178 { 179 uint32_t mask, val; 180 181 switch (ep_type) { 182 case VOP_EP_MIPI: 183 case VOP_EP_MIPI1: 184 mask = RK3399_VOP_MIPI_POL; 185 break; 186 case VOP_EP_EDP: 187 mask = RK3399_VOP_EDP_POL; 188 break; 189 case VOP_EP_HDMI: 190 mask = RK3399_VOP_HDMI_POL; 191 break; 192 case VOP_EP_DP: 193 mask = RK3399_VOP_DP_POL; 194 break; 195 default: 196 return; 197 } 198 199 val = RD4(sc, VOP_DSP_CTRL1); 200 val &= ~mask; 201 val |= __SHIFTIN(pol, mask); 202 WR4(sc, VOP_DSP_CTRL1, val); 203 } 204 205 static void 206 rk3399_vop_init(struct rk_vop_softc *sc) 207 { 208 uint32_t val; 209 210 val = RD4(sc, VOP_SYS_CTRL); 211 val |= RK3399_VOP_SYS_CTRL_ENABLE; 212 WR4(sc, VOP_SYS_CTRL, val); 213 } 214 215 static const struct rk_vop_config rk3399_vop_lit_config = { 216 .descr = "RK3399 VOPL", 217 .out_mode = DSP_OUT_MODE_RGB888, 218 .init = rk3399_vop_init, 219 .set_polarity = rk3399_vop_set_polarity, 220 }; 221 222 static const struct rk_vop_config rk3399_vop_big_config = { 223 .descr = "RK3399 VOPB", 224 .out_mode = DSP_OUT_MODE_RGBaaa, 225 .init = rk3399_vop_init, 226 .set_polarity = rk3399_vop_set_polarity, 227 }; 228 229 static const struct of_compat_data compat_data[] = { 230 { "rockchip,rk3399-vop-big", (uintptr_t)&rk3399_vop_big_config }, 231 { "rockchip,rk3399-vop-lit", (uintptr_t)&rk3399_vop_lit_config }, 232 { NULL } 233 }; 234 235 static int 236 rk_vop_mode_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 237 int x, int y, int atomic) 238 { 239 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 240 struct rk_vop_softc * const sc = mixer_crtc->sc; 241 struct rk_drm_framebuffer *sfb = atomic? 242 to_rk_drm_framebuffer(fb) : 243 to_rk_drm_framebuffer(crtc->primary->fb); 244 245 uint64_t paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr; 246 247 KASSERT((paddr & ~0xffffffff) == 0); 248 249 /* Framebuffer start address */ 250 WR4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr); 251 252 return 0; 253 } 254 255 static void 256 rk_vop_destroy(struct drm_crtc *crtc) 257 { 258 drm_crtc_cleanup(crtc); 259 } 260 261 static const struct drm_crtc_funcs rk_vop_crtc_funcs = { 262 .set_config = drm_crtc_helper_set_config, 263 .destroy = rk_vop_destroy, 264 }; 265 266 static void 267 rk_vop_dpms(struct drm_crtc *crtc, int mode) 268 { 269 } 270 271 static bool 272 rk_vop_mode_fixup(struct drm_crtc *crtc, 273 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 274 { 275 return true; 276 } 277 278 static int 279 rk_vop_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 280 struct drm_display_mode *adjusted_mode, int x, int y, 281 struct drm_framebuffer *old_fb) 282 { 283 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 284 struct rk_vop_softc * const sc = mixer_crtc->sc; 285 uint32_t val; 286 u_int lb_mode; 287 int error; 288 289 const u_int hactive = adjusted_mode->hdisplay; 290 const u_int hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 291 const u_int hback_porch = adjusted_mode->htotal - adjusted_mode->hsync_end; 292 293 const u_int vactive = adjusted_mode->vdisplay; 294 const u_int vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 295 const u_int vback_porch = adjusted_mode->vtotal - adjusted_mode->vsync_end; 296 297 error = clk_set_rate(sc->sc_dclk, adjusted_mode->clock * 1000); 298 if (error != 0) 299 DRM_ERROR("couldn't set pixel clock: %d\n", error); 300 301 val = __SHIFTIN(hactive - 1, WIN0_ACT_WIDTH) | 302 __SHIFTIN(vactive - 1, WIN0_ACT_HEIGHT); 303 WR4(sc, VOP_WIN0_ACT_INFO, val); 304 305 val = __SHIFTIN(hactive - 1, WIN0_DSP_WIDTH) | 306 __SHIFTIN(vactive - 1, WIN0_DSP_HEIGHT); 307 WR4(sc, VOP_WIN0_DSP_INFO, val); 308 309 val = __SHIFTIN(hsync_len + hback_porch, WIN0_DSP_YST) | 310 __SHIFTIN(vsync_len + vback_porch, WIN0_DSP_XST); 311 WR4(sc, VOP_WIN0_DSP_ST, val); 312 313 WR4(sc, VOP_WIN0_COLOR_KEY, 0); 314 315 val = __SHIFTIN(hactive, WIN0_VIR_STRIDE); 316 WR4(sc, VOP_WIN0_VIR, val); 317 318 if (adjusted_mode->hdisplay > 2560) 319 lb_mode = WIN0_LB_MODE_RGB_3840X2; 320 else if (adjusted_mode->hdisplay > 1920) 321 lb_mode = WIN0_LB_MODE_RGB_2560X4; 322 else if (adjusted_mode->hdisplay > 1280) 323 lb_mode = WIN0_LB_MODE_RGB_1920X5; 324 else 325 lb_mode = WIN0_LB_MODE_RGB_1280X8; 326 327 val = __SHIFTIN(lb_mode, WIN0_LB_MODE) | 328 __SHIFTIN(WIN0_DATA_FMT_ARGB888, WIN0_DATA_FMT) | 329 WIN0_EN; 330 WR4(sc, VOP_WIN0_CTRL, val); 331 332 rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0); 333 334 return 0; 335 } 336 337 static int 338 rk_vop_mode_set_base(struct drm_crtc *crtc, int x, int y, 339 struct drm_framebuffer *old_fb) 340 { 341 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 342 struct rk_vop_softc * const sc = mixer_crtc->sc; 343 344 rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0); 345 346 /* Commit settings */ 347 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 348 349 return 0; 350 } 351 352 static int 353 rk_vop_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 354 int x, int y, enum mode_set_atomic state) 355 { 356 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 357 struct rk_vop_softc * const sc = mixer_crtc->sc; 358 359 rk_vop_mode_do_set_base(crtc, fb, x, y, 1); 360 361 /* Commit settings */ 362 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 363 364 return 0; 365 } 366 367 static void 368 rk_vop_disable(struct drm_crtc *crtc) 369 { 370 } 371 372 static void 373 rk_vop_prepare(struct drm_crtc *crtc) 374 { 375 } 376 377 static void 378 rk_vop_commit(struct drm_crtc *crtc) 379 { 380 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 381 struct rk_vop_softc * const sc = mixer_crtc->sc; 382 383 /* Commit settings */ 384 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 385 } 386 387 static const struct drm_crtc_helper_funcs rk_vop_crtc_helper_funcs = { 388 .dpms = rk_vop_dpms, 389 .mode_fixup = rk_vop_mode_fixup, 390 .mode_set = rk_vop_mode_set, 391 .mode_set_base = rk_vop_mode_set_base, 392 .mode_set_base_atomic = rk_vop_mode_set_base_atomic, 393 .disable = rk_vop_disable, 394 .prepare = rk_vop_prepare, 395 .commit = rk_vop_commit, 396 }; 397 398 static void 399 rk_vop_encoder_destroy(struct drm_encoder *encoder) 400 { 401 } 402 403 static const struct drm_encoder_funcs rk_vop_encoder_funcs = { 404 .destroy = rk_vop_encoder_destroy, 405 }; 406 407 static void 408 rk_vop_encoder_dpms(struct drm_encoder *encoder, int mode) 409 { 410 } 411 412 static bool 413 rk_vop_encoder_mode_fixup(struct drm_encoder *encoder, 414 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 415 { 416 return true; 417 } 418 419 static void 420 rk_vop_encoder_mode_set(struct drm_encoder *encoder, 421 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 422 { 423 struct rk_vop_encoder *rkencoder = to_rk_vop_encoder(encoder); 424 struct rk_vop_softc * const sc = rkencoder->sc; 425 uint32_t val; 426 u_int pol; 427 428 const u_int hactive = adjusted_mode->hdisplay; 429 const u_int hfront_porch = adjusted_mode->hsync_start - adjusted_mode->hdisplay; 430 const u_int hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 431 const u_int hback_porch = adjusted_mode->htotal - adjusted_mode->hsync_end; 432 433 const u_int vactive = adjusted_mode->vdisplay; 434 const u_int vfront_porch = adjusted_mode->vsync_start - adjusted_mode->vdisplay; 435 const u_int vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 436 const u_int vback_porch = adjusted_mode->vtotal - adjusted_mode->vsync_end; 437 438 pol = DSP_DCLK_POL; 439 if ((adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) != 0) 440 pol |= DSP_HSYNC_POL; 441 if ((adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) != 0) 442 pol |= DSP_VSYNC_POL; 443 sc->sc_conf->set_polarity(sc, rkencoder->ep_type, pol); 444 445 val = RD4(sc, VOP_SYS_CTRL); 446 val &= ~VOP_STANDBY_EN; 447 val &= ~(MIPI_OUT_EN|EDP_OUT_EN|HDMI_OUT_EN|RGB_OUT_EN); 448 switch (rkencoder->ep_type) { 449 case VOP_EP_MIPI: 450 case VOP_EP_MIPI1: 451 val |= MIPI_OUT_EN; 452 break; 453 case VOP_EP_EDP: 454 case VOP_EP_DP: 455 val |= EDP_OUT_EN; 456 break; 457 case VOP_EP_HDMI: 458 val |= HDMI_OUT_EN; 459 break; 460 default: 461 break; 462 } 463 WR4(sc, VOP_SYS_CTRL, val); 464 465 val = RD4(sc, VOP_DSP_CTRL0); 466 val &= ~DSP_OUT_MODE; 467 val |= __SHIFTIN(sc->sc_conf->out_mode, DSP_OUT_MODE); 468 WR4(sc, VOP_DSP_CTRL0, val); 469 470 val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST_POST) | 471 __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END_POST); 472 WR4(sc, VOP_POST_DSP_HACT_INFO, val); 473 474 val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST) | 475 __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END); 476 WR4(sc, VOP_DSP_HACT_ST_END, val); 477 478 val = __SHIFTIN(hsync_len, DSP_HTOTAL) | 479 __SHIFTIN(hsync_len + hback_porch + hactive + hfront_porch, DSP_HS_END); 480 WR4(sc, VOP_DSP_HTOTAL_HS_END, val); 481 482 val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST_POST) | 483 __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END_POST); 484 WR4(sc, VOP_POST_DSP_VACT_INFO, val); 485 486 val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST) | 487 __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END); 488 WR4(sc, VOP_DSP_VACT_ST_END, val); 489 490 val = __SHIFTIN(vsync_len, DSP_VTOTAL) | 491 __SHIFTIN(vsync_len + vback_porch + vactive + vfront_porch, DSP_VS_END); 492 WR4(sc, VOP_DSP_VTOTAL_VS_END, val); 493 } 494 495 static void 496 rk_vop_encoder_prepare(struct drm_encoder *encoder) 497 { 498 } 499 500 static void 501 rk_vop_encoder_commit(struct drm_encoder *encoder) 502 { 503 struct rk_vop_encoder *rkencoder = to_rk_vop_encoder(encoder); 504 struct rk_vop_softc * const sc = rkencoder->sc; 505 506 /* Commit settings */ 507 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 508 } 509 510 static const struct drm_encoder_helper_funcs rk_vop_encoder_helper_funcs = { 511 .dpms = rk_vop_encoder_dpms, 512 .mode_fixup = rk_vop_encoder_mode_fixup, 513 .prepare = rk_vop_encoder_prepare, 514 .commit = rk_vop_encoder_commit, 515 .mode_set = rk_vop_encoder_mode_set, 516 }; 517 518 static int 519 rk_vop_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 520 { 521 struct rk_vop_softc * const sc = device_private(dev); 522 struct drm_device *ddev; 523 u_int encoder_type; 524 525 if (!activate) 526 return EINVAL; 527 528 ddev = rk_drm_port_device(&sc->sc_ports); 529 if (ddev == NULL) { 530 DRM_ERROR("couldn't find DRM device\n"); 531 return ENXIO; 532 } 533 534 if (sc->sc_crtc.sc == NULL) { 535 sc->sc_crtc.sc = sc; 536 537 drm_crtc_init(ddev, &sc->sc_crtc.base, &rk_vop_crtc_funcs); 538 drm_crtc_helper_add(&sc->sc_crtc.base, &rk_vop_crtc_helper_funcs); 539 540 aprint_debug_dev(dev, "using CRTC %d for %s\n", 541 drm_crtc_index(&sc->sc_crtc.base), sc->sc_conf->descr); 542 } 543 544 const u_int ep_index = fdt_endpoint_index(ep); 545 if (ep_index >= VOP_NEP) { 546 DRM_ERROR("endpoint index %d out of range\n", ep_index); 547 return ENXIO; 548 } 549 550 switch (ep_index) { 551 case VOP_EP_MIPI: 552 case VOP_EP_MIPI1: 553 encoder_type = DRM_MODE_ENCODER_DSI; 554 break; 555 case VOP_EP_HDMI: 556 case VOP_EP_EDP: 557 case VOP_EP_DP: 558 encoder_type = DRM_MODE_ENCODER_TMDS; 559 break; 560 } 561 562 sc->sc_encoder[ep_index].sc = sc; 563 sc->sc_encoder[ep_index].ep_type = ep_index; 564 sc->sc_encoder[ep_index].base.possible_crtcs = 1 << drm_crtc_index(&sc->sc_crtc.base); 565 drm_encoder_init(ddev, &sc->sc_encoder[ep_index].base, &rk_vop_encoder_funcs, 566 encoder_type); 567 drm_encoder_helper_add(&sc->sc_encoder[ep_index].base, &rk_vop_encoder_helper_funcs); 568 569 return fdt_endpoint_activate(ep, activate); 570 } 571 572 static void * 573 rk_vop_ep_get_data(device_t dev, struct fdt_endpoint *ep) 574 { 575 struct rk_vop_softc * const sc = device_private(dev); 576 const u_int ep_index = fdt_endpoint_index(ep); 577 578 if (ep_index >= VOP_NEP) 579 return NULL; 580 581 if (sc->sc_encoder[ep_index].sc == NULL) 582 return NULL; 583 584 return &sc->sc_encoder[ep_index].base; 585 } 586 587 static int 588 rk_vop_match(device_t parent, cfdata_t cf, void *aux) 589 { 590 struct fdt_attach_args * const faa = aux; 591 592 return of_match_compat_data(faa->faa_phandle, compat_data); 593 } 594 595 static void 596 rk_vop_attach(device_t parent, device_t self, void *aux) 597 { 598 struct rk_vop_softc * const sc = device_private(self); 599 struct fdt_attach_args * const faa = aux; 600 const int phandle = faa->faa_phandle; 601 const char * const reset_names[] = { "axi", "ahb", "dclk" }; 602 const char * const clock_names[] = { "aclk_vop", "hclk_vop" }; 603 struct fdtbus_reset *rst; 604 bus_addr_t addr; 605 bus_size_t size; 606 u_int n; 607 608 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 609 aprint_error(": couldn't get registers\n"); 610 return; 611 } 612 613 fdtbus_clock_assign(phandle); 614 615 for (n = 0; n < __arraycount(reset_names); n++) { 616 rst = fdtbus_reset_get(phandle, reset_names[n]); 617 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 618 aprint_error(": couldn't de-assert reset %s\n", reset_names[n]); 619 return; 620 } 621 } 622 for (n = 0; n < __arraycount(clock_names); n++) { 623 if (fdtbus_clock_enable(phandle, clock_names[n], true) != 0) { 624 aprint_error(": couldn't enable clock %s\n", clock_names[n]); 625 return; 626 } 627 } 628 sc->sc_dclk = fdtbus_clock_get(phandle, "dclk_vop"); 629 if (sc->sc_dclk == NULL || clk_enable(sc->sc_dclk) != 0) { 630 aprint_error(": couldn't enable clock %s\n", "dclk_vop"); 631 return; 632 } 633 634 sc->sc_dev = self; 635 sc->sc_bst = faa->faa_bst; 636 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 637 aprint_error(": couldn't map registers\n"); 638 return; 639 } 640 sc->sc_phandle = faa->faa_phandle; 641 sc->sc_conf = (void *)of_search_compatible(phandle, compat_data)->data; 642 643 aprint_naive("\n"); 644 aprint_normal(": %s\n", sc->sc_conf->descr); 645 646 if (sc->sc_conf->init != NULL) 647 sc->sc_conf->init(sc); 648 649 sc->sc_ports.dp_ep_activate = rk_vop_ep_activate; 650 sc->sc_ports.dp_ep_get_data = rk_vop_ep_get_data; 651 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_ENCODER); 652 653 const int port_phandle = of_find_firstchild_byname(phandle, "port"); 654 if (port_phandle > 0) 655 rk_drm_register_port(port_phandle, &sc->sc_ports); 656 } 657 658 CFATTACH_DECL_NEW(rk_vop, sizeof(struct rk_vop_softc), 659 rk_vop_match, rk_vop_attach, NULL, NULL); 660
Indexes created Thu Oct 02 14:10:14 GMT 2025