rk_vop.c revision 1.10
1 /* $NetBSD: rk_vop.c,v 1.10 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_vop.c,v 1.10 2021/01/27 03:10:19 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/conf.h> 39 #include <sys/sysctl.h> 40 41 #include <drm/drmP.h> 42 #include <drm/drm_crtc.h> 43 #include <drm/drm_crtc_helper.h> 44 #include <drm/drm_plane_helper.h> 45 46 #include <dev/fdt/fdtvar.h> 47 #include <dev/fdt/fdt_port.h> 48 49 #include <arm/rockchip/rk_drm.h> 50 51 #define VOP_REG_CFG_DONE 0x0000 52 #define REG_LOAD_EN __BIT(0) 53 #define VOP_SYS_CTRL 0x0008 54 #define VOP_STANDBY_EN __BIT(22) 55 #define MIPI_OUT_EN __BIT(15) 56 #define EDP_OUT_EN __BIT(14) 57 #define HDMI_OUT_EN __BIT(13) 58 #define RGB_OUT_EN __BIT(12) 59 #define VOP_DSP_CTRL0 0x0010 60 #define DSP_OUT_MODE __BITS(3,0) 61 #define DSP_OUT_MODE_RGB888 0 62 #define DSP_OUT_MODE_RGBaaa 15 63 #define VOP_DSP_CTRL1 0x0014 64 #define VOP_WIN0_CTRL 0x0030 65 #define WIN0_LB_MODE __BITS(7,5) 66 #define WIN0_LB_MODE_RGB_3840X2 2 67 #define WIN0_LB_MODE_RGB_2560X4 3 68 #define WIN0_LB_MODE_RGB_1920X5 4 69 #define WIN0_LB_MODE_RGB_1280X8 5 70 #define WIN0_DATA_FMT __BITS(3,1) 71 #define WIN0_DATA_FMT_ARGB888 0 72 #define WIN0_EN __BIT(0) 73 #define VOP_WIN0_COLOR_KEY 0x0038 74 #define VOP_WIN0_VIR 0x003c 75 #define WIN0_VIR_STRIDE __BITS(13,0) 76 #define VOP_WIN0_YRGB_MST 0x0040 77 #define VOP_WIN0_ACT_INFO 0x0048 78 #define WIN0_ACT_HEIGHT __BITS(28,16) 79 #define WIN0_ACT_WIDTH __BITS(12,0) 80 #define VOP_WIN0_DSP_INFO 0x004c 81 #define WIN0_DSP_HEIGHT __BITS(27,16) 82 #define WIN0_DSP_WIDTH __BITS(11,0) 83 #define VOP_WIN0_DSP_ST 0x0050 84 #define WIN0_DSP_YST __BITS(28,16) 85 #define WIN0_DSP_XST __BITS(12,0) 86 #define VOP_POST_DSP_HACT_INFO 0x0170 87 #define DSP_HACT_ST_POST __BITS(28,16) 88 #define DSP_HACT_END_POST __BITS(12,0) 89 #define VOP_POST_DSP_VACT_INFO 0x0174 90 #define DSP_VACT_ST_POST __BITS(28,16) 91 #define DSP_VACT_END_POST __BITS(12,0) 92 #define VOP_DSP_HTOTAL_HS_END 0x0188 93 #define DSP_HS_END __BITS(28,16) 94 #define DSP_HTOTAL __BITS(12,0) 95 #define VOP_DSP_HACT_ST_END 0x018c 96 #define DSP_HACT_ST __BITS(28,16) 97 #define DSP_HACT_END __BITS(12,0) 98 #define VOP_DSP_VTOTAL_VS_END 0x0190 99 #define DSP_VS_END __BITS(28,16) 100 #define DSP_VTOTAL __BITS(12,0) 101 #define VOP_DSP_VACT_ST_END 0x0194 102 #define DSP_VACT_ST __BITS(28,16) 103 #define DSP_VACT_END __BITS(12,0) 104 105 /* 106 * Polarity fields are in different locations depending on SoC and output type, 107 * but always in the same order. 108 */ 109 #define DSP_DCLK_POL __BIT(3) 110 #define DSP_DEN_POL __BIT(2) 111 #define DSP_VSYNC_POL __BIT(1) 112 #define DSP_HSYNC_POL __BIT(0) 113 114 enum vop_ep_type { 115 VOP_EP_MIPI, 116 VOP_EP_EDP, 117 VOP_EP_HDMI, 118 VOP_EP_MIPI1, 119 VOP_EP_DP, 120 VOP_NEP 121 }; 122 123 struct rk_vop_softc; 124 struct rk_vop_config; 125 126 struct rk_vop_crtc { 127 struct drm_crtc base; 128 struct rk_vop_softc *sc; 129 }; 130 131 struct rk_vop_softc { 132 device_t sc_dev; 133 bus_space_tag_t sc_bst; 134 bus_space_handle_t sc_bsh; 135 int sc_phandle; 136 137 struct clk *sc_dclk; 138 139 struct rk_vop_crtc sc_crtc; 140 141 struct fdt_device_ports sc_ports; 142 143 const struct rk_vop_config *sc_conf; 144 }; 145 146 #define to_rk_vop_crtc(x) container_of(x, struct rk_vop_crtc, base) 147 148 #define RD4(sc, reg) \ 149 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 150 #define WR4(sc, reg, val) \ 151 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 152 153 struct rk_vop_config { 154 const char *descr; 155 u_int out_mode; 156 void (*init)(struct rk_vop_softc *); 157 void (*set_polarity)(struct rk_vop_softc *, 158 enum vop_ep_type, uint32_t); 159 }; 160 161 #define RK3399_VOP_MIPI_POL __BITS(31,28) 162 #define RK3399_VOP_EDP_POL __BITS(27,24) 163 #define RK3399_VOP_HDMI_POL __BITS(23,20) 164 #define RK3399_VOP_DP_POL __BITS(19,16) 165 166 #define RK3399_VOP_SYS_CTRL_ENABLE __BIT(11) 167 168 static void 169 rk3399_vop_set_polarity(struct rk_vop_softc *sc, enum vop_ep_type ep_type, uint32_t pol) 170 { 171 uint32_t mask, val; 172 173 switch (ep_type) { 174 case VOP_EP_MIPI: 175 case VOP_EP_MIPI1: 176 mask = RK3399_VOP_MIPI_POL; 177 break; 178 case VOP_EP_EDP: 179 mask = RK3399_VOP_EDP_POL; 180 break; 181 case VOP_EP_HDMI: 182 mask = RK3399_VOP_HDMI_POL; 183 break; 184 case VOP_EP_DP: 185 mask = RK3399_VOP_DP_POL; 186 break; 187 default: 188 return; 189 } 190 191 val = RD4(sc, VOP_DSP_CTRL1); 192 val &= ~mask; 193 val |= __SHIFTIN(pol, mask); 194 WR4(sc, VOP_DSP_CTRL1, val); 195 } 196 197 static void 198 rk3399_vop_init(struct rk_vop_softc *sc) 199 { 200 uint32_t val; 201 202 val = RD4(sc, VOP_SYS_CTRL); 203 val |= RK3399_VOP_SYS_CTRL_ENABLE; 204 WR4(sc, VOP_SYS_CTRL, val); 205 } 206 207 static const struct rk_vop_config rk3399_vop_lit_config = { 208 .descr = "RK3399 VOPL", 209 .out_mode = DSP_OUT_MODE_RGB888, 210 .init = rk3399_vop_init, 211 .set_polarity = rk3399_vop_set_polarity, 212 }; 213 214 static const struct rk_vop_config rk3399_vop_big_config = { 215 .descr = "RK3399 VOPB", 216 .out_mode = DSP_OUT_MODE_RGBaaa, 217 .init = rk3399_vop_init, 218 .set_polarity = rk3399_vop_set_polarity, 219 }; 220 221 static const struct device_compatible_entry compat_data[] = { 222 { .compat = "rockchip,rk3399-vop-big", 223 .data = &rk3399_vop_big_config }, 224 { .compat = "rockchip,rk3399-vop-lit", 225 .data = &rk3399_vop_lit_config }, 226 227 DEVICE_COMPAT_EOL 228 }; 229 230 static int 231 rk_vop_mode_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 232 int x, int y, int atomic) 233 { 234 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 235 struct rk_vop_softc * const sc = mixer_crtc->sc; 236 struct rk_drm_framebuffer *sfb = atomic? 237 to_rk_drm_framebuffer(fb) : 238 to_rk_drm_framebuffer(crtc->primary->fb); 239 240 uint64_t paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr; 241 242 243 paddr += y * sfb->base.pitches[0]; 244 paddr += x * drm_format_plane_cpp(sfb->base.pixel_format, 0); 245 246 KASSERT((paddr & ~0xffffffff) == 0); 247 248 const uint32_t vir = __SHIFTIN(sfb->base.pitches[0] / 4, 249 WIN0_VIR_STRIDE); 250 WR4(sc, VOP_WIN0_VIR, vir); 251 252 /* Framebuffer start address */ 253 WR4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr); 254 255 return 0; 256 } 257 258 static void 259 rk_vop_destroy(struct drm_crtc *crtc) 260 { 261 drm_crtc_cleanup(crtc); 262 } 263 264 static const struct drm_crtc_funcs rk_vop_crtc_funcs = { 265 .set_config = drm_crtc_helper_set_config, 266 .destroy = rk_vop_destroy, 267 }; 268 269 static void 270 rk_vop_dpms(struct drm_crtc *crtc, int mode) 271 { 272 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 273 struct rk_vop_softc * const sc = mixer_crtc->sc; 274 uint32_t val; 275 276 val = RD4(sc, VOP_SYS_CTRL); 277 278 switch (mode) { 279 case DRM_MODE_DPMS_ON: 280 val &= ~VOP_STANDBY_EN; 281 break; 282 case DRM_MODE_DPMS_STANDBY: 283 case DRM_MODE_DPMS_SUSPEND: 284 case DRM_MODE_DPMS_OFF: 285 val |= VOP_STANDBY_EN; 286 break; 287 } 288 289 WR4(sc, VOP_SYS_CTRL, val); 290 291 /* Commit settings */ 292 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 293 } 294 295 static bool 296 rk_vop_mode_fixup(struct drm_crtc *crtc, 297 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 298 { 299 return true; 300 } 301 302 static int 303 rk_vop_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 304 struct drm_display_mode *adjusted_mode, int x, int y, 305 struct drm_framebuffer *old_fb) 306 { 307 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 308 struct rk_vop_softc * const sc = mixer_crtc->sc; 309 uint32_t val; 310 u_int lb_mode; 311 int error; 312 u_int pol; 313 int connector_type = 0; 314 struct drm_connector * connector; 315 316 const u_int hactive = adjusted_mode->hdisplay; 317 const u_int hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 318 const u_int hback_porch = adjusted_mode->htotal - adjusted_mode->hsync_end; 319 const u_int hfront_porch = adjusted_mode->hsync_start - adjusted_mode->hdisplay; 320 321 const u_int vactive = adjusted_mode->vdisplay; 322 const u_int vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 323 const u_int vback_porch = adjusted_mode->vtotal - adjusted_mode->vsync_end; 324 const u_int vfront_porch = adjusted_mode->vsync_start - adjusted_mode->vdisplay; 325 326 error = clk_set_rate(sc->sc_dclk, adjusted_mode->clock * 1000); 327 if (error != 0) 328 DRM_ERROR("couldn't set pixel clock: %d\n", error); 329 330 val = __SHIFTIN(hactive - 1, WIN0_ACT_WIDTH) | 331 __SHIFTIN(vactive - 1, WIN0_ACT_HEIGHT); 332 WR4(sc, VOP_WIN0_ACT_INFO, val); 333 334 val = __SHIFTIN(hactive - 1, WIN0_DSP_WIDTH) | 335 __SHIFTIN(vactive - 1, WIN0_DSP_HEIGHT); 336 WR4(sc, VOP_WIN0_DSP_INFO, val); 337 338 val = __SHIFTIN(hsync_len + hback_porch, WIN0_DSP_XST) | 339 __SHIFTIN(vsync_len + vback_porch, WIN0_DSP_YST); 340 WR4(sc, VOP_WIN0_DSP_ST, val); 341 342 WR4(sc, VOP_WIN0_COLOR_KEY, 0); 343 344 if (adjusted_mode->hdisplay > 2560) 345 lb_mode = WIN0_LB_MODE_RGB_3840X2; 346 else if (adjusted_mode->hdisplay > 1920) 347 lb_mode = WIN0_LB_MODE_RGB_2560X4; 348 else if (adjusted_mode->hdisplay > 1280) 349 lb_mode = WIN0_LB_MODE_RGB_1920X5; 350 else 351 lb_mode = WIN0_LB_MODE_RGB_1280X8; 352 353 val = __SHIFTIN(lb_mode, WIN0_LB_MODE) | 354 __SHIFTIN(WIN0_DATA_FMT_ARGB888, WIN0_DATA_FMT) | 355 WIN0_EN; 356 WR4(sc, VOP_WIN0_CTRL, val); 357 358 rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0); 359 360 pol = DSP_DCLK_POL; 361 if ((adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) != 0) 362 pol |= DSP_HSYNC_POL; 363 if ((adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) != 0) 364 pol |= DSP_VSYNC_POL; 365 366 drm_for_each_connector(connector, crtc->dev) { 367 if ((connector->encoder) == NULL) 368 continue; 369 if (connector->encoder->crtc == crtc) { 370 connector_type = connector->connector_type; 371 break; 372 } 373 } 374 375 switch (connector_type) { 376 case DRM_MODE_CONNECTOR_HDMIA: 377 sc->sc_conf->set_polarity(sc, VOP_EP_HDMI, pol); 378 break; 379 case DRM_MODE_CONNECTOR_eDP: 380 sc->sc_conf->set_polarity(sc, VOP_EP_EDP, pol); 381 break; 382 } 383 384 val = RD4(sc, VOP_SYS_CTRL); 385 val &= ~VOP_STANDBY_EN; 386 val &= ~(MIPI_OUT_EN|EDP_OUT_EN|HDMI_OUT_EN|RGB_OUT_EN); 387 388 switch (connector_type) { 389 case DRM_MODE_CONNECTOR_HDMIA: 390 val |= HDMI_OUT_EN; 391 break; 392 case DRM_MODE_CONNECTOR_eDP: 393 val |= EDP_OUT_EN; 394 break; 395 } 396 WR4(sc, VOP_SYS_CTRL, val); 397 398 val = RD4(sc, VOP_DSP_CTRL0); 399 val &= ~DSP_OUT_MODE; 400 val |= __SHIFTIN(sc->sc_conf->out_mode, DSP_OUT_MODE); 401 WR4(sc, VOP_DSP_CTRL0, val); 402 403 val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST_POST) | 404 __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END_POST); 405 WR4(sc, VOP_POST_DSP_HACT_INFO, val); 406 407 val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST) | 408 __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END); 409 WR4(sc, VOP_DSP_HACT_ST_END, val); 410 411 val = __SHIFTIN(hsync_len, DSP_HTOTAL) | 412 __SHIFTIN(hsync_len + hback_porch + hactive + hfront_porch, DSP_HS_END); 413 WR4(sc, VOP_DSP_HTOTAL_HS_END, val); 414 415 val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST_POST) | 416 __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END_POST); 417 WR4(sc, VOP_POST_DSP_VACT_INFO, val); 418 419 val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST) | 420 __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END); 421 WR4(sc, VOP_DSP_VACT_ST_END, val); 422 423 val = __SHIFTIN(vsync_len, DSP_VTOTAL) | 424 __SHIFTIN(vsync_len + vback_porch + vactive + vfront_porch, DSP_VS_END); 425 WR4(sc, VOP_DSP_VTOTAL_VS_END, val); 426 427 return 0; 428 } 429 430 static int 431 rk_vop_mode_set_base(struct drm_crtc *crtc, int x, int y, 432 struct drm_framebuffer *old_fb) 433 { 434 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 435 struct rk_vop_softc * const sc = mixer_crtc->sc; 436 437 rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0); 438 439 /* Commit settings */ 440 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 441 442 return 0; 443 } 444 445 static int 446 rk_vop_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 447 int x, int y, enum mode_set_atomic state) 448 { 449 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 450 struct rk_vop_softc * const sc = mixer_crtc->sc; 451 452 rk_vop_mode_do_set_base(crtc, fb, x, y, 1); 453 454 /* Commit settings */ 455 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 456 457 return 0; 458 } 459 460 static void 461 rk_vop_disable(struct drm_crtc *crtc) 462 { 463 } 464 465 static void 466 rk_vop_prepare(struct drm_crtc *crtc) 467 { 468 } 469 470 static void 471 rk_vop_commit(struct drm_crtc *crtc) 472 { 473 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 474 struct rk_vop_softc * const sc = mixer_crtc->sc; 475 476 /* Commit settings */ 477 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 478 } 479 480 static const struct drm_crtc_helper_funcs rk_vop_crtc_helper_funcs = { 481 .dpms = rk_vop_dpms, 482 .mode_fixup = rk_vop_mode_fixup, 483 .mode_set = rk_vop_mode_set, 484 .mode_set_base = rk_vop_mode_set_base, 485 .mode_set_base_atomic = rk_vop_mode_set_base_atomic, 486 .disable = rk_vop_disable, 487 .prepare = rk_vop_prepare, 488 .commit = rk_vop_commit, 489 }; 490 491 static int 492 rk_vop_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 493 { 494 struct rk_vop_softc * const sc = device_private(dev); 495 struct drm_device *ddev; 496 497 if (!activate) 498 return EINVAL; 499 500 ddev = rk_drm_port_device(&sc->sc_ports); 501 if (ddev == NULL) { 502 DRM_ERROR("couldn't find DRM device\n"); 503 return ENXIO; 504 } 505 506 if (sc->sc_crtc.sc == NULL) { 507 sc->sc_crtc.sc = sc; 508 509 drm_crtc_init(ddev, &sc->sc_crtc.base, &rk_vop_crtc_funcs); 510 drm_crtc_helper_add(&sc->sc_crtc.base, &rk_vop_crtc_helper_funcs); 511 512 aprint_debug_dev(dev, "using CRTC %d for %s\n", 513 drm_crtc_index(&sc->sc_crtc.base), sc->sc_conf->descr); 514 } 515 516 const u_int ep_index = fdt_endpoint_index(ep); 517 if (ep_index >= VOP_NEP) { 518 DRM_ERROR("endpoint index %d out of range\n", ep_index); 519 return ENXIO; 520 } 521 522 return fdt_endpoint_activate(ep, activate); 523 } 524 525 static void * 526 rk_vop_ep_get_data(device_t dev, struct fdt_endpoint *ep) 527 { 528 struct rk_vop_softc * const sc = device_private(dev); 529 530 return &sc->sc_crtc.base; 531 } 532 533 static int 534 rk_vop_match(device_t parent, cfdata_t cf, void *aux) 535 { 536 struct fdt_attach_args * const faa = aux; 537 538 return of_compatible_match(faa->faa_phandle, compat_data); 539 } 540 541 static void 542 rk_vop_attach(device_t parent, device_t self, void *aux) 543 { 544 struct rk_vop_softc * const sc = device_private(self); 545 struct fdt_attach_args * const faa = aux; 546 const int phandle = faa->faa_phandle; 547 const char * const reset_names[] = { "axi", "ahb", "dclk" }; 548 const char * const clock_names[] = { "aclk_vop", "hclk_vop" }; 549 struct fdtbus_reset *rst; 550 bus_addr_t addr; 551 bus_size_t size; 552 u_int n; 553 554 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 555 aprint_error(": couldn't get registers\n"); 556 return; 557 } 558 559 fdtbus_clock_assign(phandle); 560 561 for (n = 0; n < __arraycount(reset_names); n++) { 562 rst = fdtbus_reset_get(phandle, reset_names[n]); 563 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 564 aprint_error(": couldn't de-assert reset %s\n", reset_names[n]); 565 return; 566 } 567 } 568 for (n = 0; n < __arraycount(clock_names); n++) { 569 if (fdtbus_clock_enable(phandle, clock_names[n], true) != 0) { 570 aprint_error(": couldn't enable clock %s\n", clock_names[n]); 571 return; 572 } 573 } 574 sc->sc_dclk = fdtbus_clock_get(phandle, "dclk_vop"); 575 if (sc->sc_dclk == NULL || clk_enable(sc->sc_dclk) != 0) { 576 aprint_error(": couldn't enable clock %s\n", "dclk_vop"); 577 return; 578 } 579 580 sc->sc_dev = self; 581 sc->sc_bst = faa->faa_bst; 582 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 583 aprint_error(": couldn't map registers\n"); 584 return; 585 } 586 sc->sc_phandle = faa->faa_phandle; 587 sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data; 588 589 aprint_naive("\n"); 590 aprint_normal(": %s\n", sc->sc_conf->descr); 591 592 if (sc->sc_conf->init != NULL) 593 sc->sc_conf->init(sc); 594 595 sc->sc_ports.dp_ep_activate = rk_vop_ep_activate; 596 sc->sc_ports.dp_ep_get_data = rk_vop_ep_get_data; 597 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_CRTC); 598 599 const int port_phandle = of_find_firstchild_byname(phandle, "port"); 600 if (port_phandle > 0) 601 rk_drm_register_port(port_phandle, &sc->sc_ports); 602 } 603 604 CFATTACH_DECL_NEW(rk_vop, sizeof(struct rk_vop_softc), 605 rk_vop_match, rk_vop_attach, NULL, NULL); 606
Indexes created Thu Oct 02 14:10:14 GMT 2025