rk_vop.c revision 1.11
1 /* $NetBSD: rk_vop.c,v 1.11 2021/12/19 11:00:46 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_vop.c,v 1.11 2021/12/19 11:00:46 riastradh Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/conf.h> 39 #include <sys/sysctl.h> 40 41 #include <drm/drm_drv.h> 42 #include <drm/drm_crtc.h> 43 #include <drm/drm_crtc_helper.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 47 #include <dev/fdt/fdtvar.h> 48 #include <dev/fdt/fdt_port.h> 49 50 #include <arm/rockchip/rk_drm.h> 51 52 #define VOP_REG_CFG_DONE 0x0000 53 #define REG_LOAD_EN __BIT(0) 54 #define VOP_SYS_CTRL 0x0008 55 #define VOP_STANDBY_EN __BIT(22) 56 #define MIPI_OUT_EN __BIT(15) 57 #define EDP_OUT_EN __BIT(14) 58 #define HDMI_OUT_EN __BIT(13) 59 #define RGB_OUT_EN __BIT(12) 60 #define VOP_DSP_CTRL0 0x0010 61 #define DSP_OUT_MODE __BITS(3,0) 62 #define DSP_OUT_MODE_RGB888 0 63 #define DSP_OUT_MODE_RGBaaa 15 64 #define VOP_DSP_CTRL1 0x0014 65 #define VOP_WIN0_CTRL 0x0030 66 #define WIN0_LB_MODE __BITS(7,5) 67 #define WIN0_LB_MODE_RGB_3840X2 2 68 #define WIN0_LB_MODE_RGB_2560X4 3 69 #define WIN0_LB_MODE_RGB_1920X5 4 70 #define WIN0_LB_MODE_RGB_1280X8 5 71 #define WIN0_DATA_FMT __BITS(3,1) 72 #define WIN0_DATA_FMT_ARGB888 0 73 #define WIN0_EN __BIT(0) 74 #define VOP_WIN0_COLOR_KEY 0x0038 75 #define VOP_WIN0_VIR 0x003c 76 #define WIN0_VIR_STRIDE __BITS(13,0) 77 #define VOP_WIN0_YRGB_MST 0x0040 78 #define VOP_WIN0_ACT_INFO 0x0048 79 #define WIN0_ACT_HEIGHT __BITS(28,16) 80 #define WIN0_ACT_WIDTH __BITS(12,0) 81 #define VOP_WIN0_DSP_INFO 0x004c 82 #define WIN0_DSP_HEIGHT __BITS(27,16) 83 #define WIN0_DSP_WIDTH __BITS(11,0) 84 #define VOP_WIN0_DSP_ST 0x0050 85 #define WIN0_DSP_YST __BITS(28,16) 86 #define WIN0_DSP_XST __BITS(12,0) 87 #define VOP_POST_DSP_HACT_INFO 0x0170 88 #define DSP_HACT_ST_POST __BITS(28,16) 89 #define DSP_HACT_END_POST __BITS(12,0) 90 #define VOP_POST_DSP_VACT_INFO 0x0174 91 #define DSP_VACT_ST_POST __BITS(28,16) 92 #define DSP_VACT_END_POST __BITS(12,0) 93 #define VOP_DSP_HTOTAL_HS_END 0x0188 94 #define DSP_HS_END __BITS(28,16) 95 #define DSP_HTOTAL __BITS(12,0) 96 #define VOP_DSP_HACT_ST_END 0x018c 97 #define DSP_HACT_ST __BITS(28,16) 98 #define DSP_HACT_END __BITS(12,0) 99 #define VOP_DSP_VTOTAL_VS_END 0x0190 100 #define DSP_VS_END __BITS(28,16) 101 #define DSP_VTOTAL __BITS(12,0) 102 #define VOP_DSP_VACT_ST_END 0x0194 103 #define DSP_VACT_ST __BITS(28,16) 104 #define DSP_VACT_END __BITS(12,0) 105 106 /* 107 * Polarity fields are in different locations depending on SoC and output type, 108 * but always in the same order. 109 */ 110 #define DSP_DCLK_POL __BIT(3) 111 #define DSP_DEN_POL __BIT(2) 112 #define DSP_VSYNC_POL __BIT(1) 113 #define DSP_HSYNC_POL __BIT(0) 114 115 enum vop_ep_type { 116 VOP_EP_MIPI, 117 VOP_EP_EDP, 118 VOP_EP_HDMI, 119 VOP_EP_MIPI1, 120 VOP_EP_DP, 121 VOP_NEP 122 }; 123 124 struct rk_vop_softc; 125 struct rk_vop_config; 126 127 struct rk_vop_crtc { 128 struct drm_crtc base; 129 struct rk_vop_softc *sc; 130 }; 131 132 struct rk_vop_softc { 133 device_t sc_dev; 134 bus_space_tag_t sc_bst; 135 bus_space_handle_t sc_bsh; 136 int sc_phandle; 137 138 struct clk *sc_dclk; 139 140 struct rk_vop_crtc sc_crtc; 141 142 struct fdt_device_ports sc_ports; 143 144 const struct rk_vop_config *sc_conf; 145 }; 146 147 #define to_rk_vop_crtc(x) container_of(x, struct rk_vop_crtc, base) 148 149 #define RD4(sc, reg) \ 150 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 151 #define WR4(sc, reg, val) \ 152 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 153 154 struct rk_vop_config { 155 const char *descr; 156 u_int out_mode; 157 void (*init)(struct rk_vop_softc *); 158 void (*set_polarity)(struct rk_vop_softc *, 159 enum vop_ep_type, uint32_t); 160 }; 161 162 #define RK3399_VOP_MIPI_POL __BITS(31,28) 163 #define RK3399_VOP_EDP_POL __BITS(27,24) 164 #define RK3399_VOP_HDMI_POL __BITS(23,20) 165 #define RK3399_VOP_DP_POL __BITS(19,16) 166 167 #define RK3399_VOP_SYS_CTRL_ENABLE __BIT(11) 168 169 static void 170 rk3399_vop_set_polarity(struct rk_vop_softc *sc, enum vop_ep_type ep_type, uint32_t pol) 171 { 172 uint32_t mask, val; 173 174 switch (ep_type) { 175 case VOP_EP_MIPI: 176 case VOP_EP_MIPI1: 177 mask = RK3399_VOP_MIPI_POL; 178 break; 179 case VOP_EP_EDP: 180 mask = RK3399_VOP_EDP_POL; 181 break; 182 case VOP_EP_HDMI: 183 mask = RK3399_VOP_HDMI_POL; 184 break; 185 case VOP_EP_DP: 186 mask = RK3399_VOP_DP_POL; 187 break; 188 default: 189 return; 190 } 191 192 val = RD4(sc, VOP_DSP_CTRL1); 193 val &= ~mask; 194 val |= __SHIFTIN(pol, mask); 195 WR4(sc, VOP_DSP_CTRL1, val); 196 } 197 198 static void 199 rk3399_vop_init(struct rk_vop_softc *sc) 200 { 201 uint32_t val; 202 203 val = RD4(sc, VOP_SYS_CTRL); 204 val |= RK3399_VOP_SYS_CTRL_ENABLE; 205 WR4(sc, VOP_SYS_CTRL, val); 206 } 207 208 static const struct rk_vop_config rk3399_vop_lit_config = { 209 .descr = "RK3399 VOPL", 210 .out_mode = DSP_OUT_MODE_RGB888, 211 .init = rk3399_vop_init, 212 .set_polarity = rk3399_vop_set_polarity, 213 }; 214 215 static const struct rk_vop_config rk3399_vop_big_config = { 216 .descr = "RK3399 VOPB", 217 .out_mode = DSP_OUT_MODE_RGBaaa, 218 .init = rk3399_vop_init, 219 .set_polarity = rk3399_vop_set_polarity, 220 }; 221 222 static const struct device_compatible_entry compat_data[] = { 223 { .compat = "rockchip,rk3399-vop-big", 224 .data = &rk3399_vop_big_config }, 225 { .compat = "rockchip,rk3399-vop-lit", 226 .data = &rk3399_vop_lit_config }, 227 228 DEVICE_COMPAT_EOL 229 }; 230 231 static int 232 rk_vop_mode_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 233 int x, int y, int atomic) 234 { 235 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 236 struct rk_vop_softc * const sc = mixer_crtc->sc; 237 struct rk_drm_framebuffer *sfb = atomic? 238 to_rk_drm_framebuffer(fb) : 239 to_rk_drm_framebuffer(crtc->primary->fb); 240 241 uint64_t paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr; 242 243 244 paddr += y * sfb->base.pitches[0]; 245 paddr += x * sfb->base.format->cpp[0]; 246 247 KASSERT((paddr & ~0xffffffff) == 0); 248 249 const uint32_t vir = __SHIFTIN(sfb->base.pitches[0] / 4, 250 WIN0_VIR_STRIDE); 251 WR4(sc, VOP_WIN0_VIR, vir); 252 253 /* Framebuffer start address */ 254 WR4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr); 255 256 return 0; 257 } 258 259 static void 260 rk_vop_destroy(struct drm_crtc *crtc) 261 { 262 drm_crtc_cleanup(crtc); 263 } 264 265 static const struct drm_crtc_funcs rk_vop_crtc_funcs = { 266 .set_config = drm_crtc_helper_set_config, 267 .destroy = rk_vop_destroy, 268 }; 269 270 static void 271 rk_vop_dpms(struct drm_crtc *crtc, int mode) 272 { 273 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 274 struct rk_vop_softc * const sc = mixer_crtc->sc; 275 uint32_t val; 276 277 val = RD4(sc, VOP_SYS_CTRL); 278 279 switch (mode) { 280 case DRM_MODE_DPMS_ON: 281 val &= ~VOP_STANDBY_EN; 282 break; 283 case DRM_MODE_DPMS_STANDBY: 284 case DRM_MODE_DPMS_SUSPEND: 285 case DRM_MODE_DPMS_OFF: 286 val |= VOP_STANDBY_EN; 287 break; 288 } 289 290 WR4(sc, VOP_SYS_CTRL, val); 291 292 /* Commit settings */ 293 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 294 } 295 296 static bool 297 rk_vop_mode_fixup(struct drm_crtc *crtc, 298 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 299 { 300 return true; 301 } 302 303 static int 304 rk_vop_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 305 struct drm_display_mode *adjusted_mode, int x, int y, 306 struct drm_framebuffer *old_fb) 307 { 308 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 309 struct rk_vop_softc * const sc = mixer_crtc->sc; 310 uint32_t val; 311 u_int lb_mode; 312 int error; 313 u_int pol; 314 int connector_type = 0; 315 struct drm_connector *connector; 316 struct drm_connector_list_iter conn_iter; 317 318 const u_int hactive = adjusted_mode->hdisplay; 319 const u_int hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 320 const u_int hback_porch = adjusted_mode->htotal - adjusted_mode->hsync_end; 321 const u_int hfront_porch = adjusted_mode->hsync_start - adjusted_mode->hdisplay; 322 323 const u_int vactive = adjusted_mode->vdisplay; 324 const u_int vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 325 const u_int vback_porch = adjusted_mode->vtotal - adjusted_mode->vsync_end; 326 const u_int vfront_porch = adjusted_mode->vsync_start - adjusted_mode->vdisplay; 327 328 error = clk_set_rate(sc->sc_dclk, adjusted_mode->clock * 1000); 329 if (error != 0) 330 DRM_ERROR("couldn't set pixel clock: %d\n", error); 331 332 val = __SHIFTIN(hactive - 1, WIN0_ACT_WIDTH) | 333 __SHIFTIN(vactive - 1, WIN0_ACT_HEIGHT); 334 WR4(sc, VOP_WIN0_ACT_INFO, val); 335 336 val = __SHIFTIN(hactive - 1, WIN0_DSP_WIDTH) | 337 __SHIFTIN(vactive - 1, WIN0_DSP_HEIGHT); 338 WR4(sc, VOP_WIN0_DSP_INFO, val); 339 340 val = __SHIFTIN(hsync_len + hback_porch, WIN0_DSP_XST) | 341 __SHIFTIN(vsync_len + vback_porch, WIN0_DSP_YST); 342 WR4(sc, VOP_WIN0_DSP_ST, val); 343 344 WR4(sc, VOP_WIN0_COLOR_KEY, 0); 345 346 if (adjusted_mode->hdisplay > 2560) 347 lb_mode = WIN0_LB_MODE_RGB_3840X2; 348 else if (adjusted_mode->hdisplay > 1920) 349 lb_mode = WIN0_LB_MODE_RGB_2560X4; 350 else if (adjusted_mode->hdisplay > 1280) 351 lb_mode = WIN0_LB_MODE_RGB_1920X5; 352 else 353 lb_mode = WIN0_LB_MODE_RGB_1280X8; 354 355 val = __SHIFTIN(lb_mode, WIN0_LB_MODE) | 356 __SHIFTIN(WIN0_DATA_FMT_ARGB888, WIN0_DATA_FMT) | 357 WIN0_EN; 358 WR4(sc, VOP_WIN0_CTRL, val); 359 360 rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0); 361 362 pol = DSP_DCLK_POL; 363 if ((adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) != 0) 364 pol |= DSP_HSYNC_POL; 365 if ((adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) != 0) 366 pol |= DSP_VSYNC_POL; 367 368 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 369 drm_for_each_connector_iter(connector, &conn_iter) { 370 if (connector->encoder == NULL) 371 continue; 372 if (connector->encoder->crtc == crtc) { 373 connector_type = connector->connector_type; 374 break; 375 } 376 } 377 drm_connector_list_iter_end(&conn_iter); 378 379 switch (connector_type) { 380 case DRM_MODE_CONNECTOR_HDMIA: 381 sc->sc_conf->set_polarity(sc, VOP_EP_HDMI, pol); 382 break; 383 case DRM_MODE_CONNECTOR_eDP: 384 sc->sc_conf->set_polarity(sc, VOP_EP_EDP, pol); 385 break; 386 } 387 388 val = RD4(sc, VOP_SYS_CTRL); 389 val &= ~VOP_STANDBY_EN; 390 val &= ~(MIPI_OUT_EN|EDP_OUT_EN|HDMI_OUT_EN|RGB_OUT_EN); 391 392 switch (connector_type) { 393 case DRM_MODE_CONNECTOR_HDMIA: 394 val |= HDMI_OUT_EN; 395 break; 396 case DRM_MODE_CONNECTOR_eDP: 397 val |= EDP_OUT_EN; 398 break; 399 } 400 WR4(sc, VOP_SYS_CTRL, val); 401 402 val = RD4(sc, VOP_DSP_CTRL0); 403 val &= ~DSP_OUT_MODE; 404 val |= __SHIFTIN(sc->sc_conf->out_mode, DSP_OUT_MODE); 405 WR4(sc, VOP_DSP_CTRL0, val); 406 407 val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST_POST) | 408 __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END_POST); 409 WR4(sc, VOP_POST_DSP_HACT_INFO, val); 410 411 val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST) | 412 __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END); 413 WR4(sc, VOP_DSP_HACT_ST_END, val); 414 415 val = __SHIFTIN(hsync_len, DSP_HTOTAL) | 416 __SHIFTIN(hsync_len + hback_porch + hactive + hfront_porch, DSP_HS_END); 417 WR4(sc, VOP_DSP_HTOTAL_HS_END, val); 418 419 val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST_POST) | 420 __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END_POST); 421 WR4(sc, VOP_POST_DSP_VACT_INFO, val); 422 423 val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST) | 424 __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END); 425 WR4(sc, VOP_DSP_VACT_ST_END, val); 426 427 val = __SHIFTIN(vsync_len, DSP_VTOTAL) | 428 __SHIFTIN(vsync_len + vback_porch + vactive + vfront_porch, DSP_VS_END); 429 WR4(sc, VOP_DSP_VTOTAL_VS_END, val); 430 431 return 0; 432 } 433 434 static int 435 rk_vop_mode_set_base(struct drm_crtc *crtc, int x, int y, 436 struct drm_framebuffer *old_fb) 437 { 438 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 439 struct rk_vop_softc * const sc = mixer_crtc->sc; 440 441 rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0); 442 443 /* Commit settings */ 444 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 445 446 return 0; 447 } 448 449 static int 450 rk_vop_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 451 int x, int y, enum mode_set_atomic state) 452 { 453 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 454 struct rk_vop_softc * const sc = mixer_crtc->sc; 455 456 rk_vop_mode_do_set_base(crtc, fb, x, y, 1); 457 458 /* Commit settings */ 459 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 460 461 return 0; 462 } 463 464 static void 465 rk_vop_disable(struct drm_crtc *crtc) 466 { 467 } 468 469 static void 470 rk_vop_prepare(struct drm_crtc *crtc) 471 { 472 } 473 474 static void 475 rk_vop_commit(struct drm_crtc *crtc) 476 { 477 struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc); 478 struct rk_vop_softc * const sc = mixer_crtc->sc; 479 480 /* Commit settings */ 481 WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN); 482 } 483 484 static const struct drm_crtc_helper_funcs rk_vop_crtc_helper_funcs = { 485 .dpms = rk_vop_dpms, 486 .mode_fixup = rk_vop_mode_fixup, 487 .mode_set = rk_vop_mode_set, 488 .mode_set_base = rk_vop_mode_set_base, 489 .mode_set_base_atomic = rk_vop_mode_set_base_atomic, 490 .disable = rk_vop_disable, 491 .prepare = rk_vop_prepare, 492 .commit = rk_vop_commit, 493 }; 494 495 static int 496 rk_vop_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 497 { 498 struct rk_vop_softc * const sc = device_private(dev); 499 struct drm_device *ddev; 500 501 if (!activate) 502 return EINVAL; 503 504 ddev = rk_drm_port_device(&sc->sc_ports); 505 if (ddev == NULL) { 506 DRM_ERROR("couldn't find DRM device\n"); 507 return ENXIO; 508 } 509 510 if (sc->sc_crtc.sc == NULL) { 511 sc->sc_crtc.sc = sc; 512 513 drm_crtc_init(ddev, &sc->sc_crtc.base, &rk_vop_crtc_funcs); 514 drm_crtc_helper_add(&sc->sc_crtc.base, &rk_vop_crtc_helper_funcs); 515 516 aprint_debug_dev(dev, "using CRTC %d for %s\n", 517 drm_crtc_index(&sc->sc_crtc.base), sc->sc_conf->descr); 518 } 519 520 const u_int ep_index = fdt_endpoint_index(ep); 521 if (ep_index >= VOP_NEP) { 522 DRM_ERROR("endpoint index %d out of range\n", ep_index); 523 return ENXIO; 524 } 525 526 return fdt_endpoint_activate(ep, activate); 527 } 528 529 static void * 530 rk_vop_ep_get_data(device_t dev, struct fdt_endpoint *ep) 531 { 532 struct rk_vop_softc * const sc = device_private(dev); 533 534 return &sc->sc_crtc.base; 535 } 536 537 static int 538 rk_vop_match(device_t parent, cfdata_t cf, void *aux) 539 { 540 struct fdt_attach_args * const faa = aux; 541 542 return of_compatible_match(faa->faa_phandle, compat_data); 543 } 544 545 static void 546 rk_vop_attach(device_t parent, device_t self, void *aux) 547 { 548 struct rk_vop_softc * const sc = device_private(self); 549 struct fdt_attach_args * const faa = aux; 550 const int phandle = faa->faa_phandle; 551 const char * const reset_names[] = { "axi", "ahb", "dclk" }; 552 const char * const clock_names[] = { "aclk_vop", "hclk_vop" }; 553 struct fdtbus_reset *rst; 554 bus_addr_t addr; 555 bus_size_t size; 556 u_int n; 557 558 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 559 aprint_error(": couldn't get registers\n"); 560 return; 561 } 562 563 fdtbus_clock_assign(phandle); 564 565 for (n = 0; n < __arraycount(reset_names); n++) { 566 rst = fdtbus_reset_get(phandle, reset_names[n]); 567 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 568 aprint_error(": couldn't de-assert reset %s\n", reset_names[n]); 569 return; 570 } 571 } 572 for (n = 0; n < __arraycount(clock_names); n++) { 573 if (fdtbus_clock_enable(phandle, clock_names[n], true) != 0) { 574 aprint_error(": couldn't enable clock %s\n", clock_names[n]); 575 return; 576 } 577 } 578 sc->sc_dclk = fdtbus_clock_get(phandle, "dclk_vop"); 579 if (sc->sc_dclk == NULL || clk_enable(sc->sc_dclk) != 0) { 580 aprint_error(": couldn't enable clock %s\n", "dclk_vop"); 581 return; 582 } 583 584 sc->sc_dev = self; 585 sc->sc_bst = faa->faa_bst; 586 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 587 aprint_error(": couldn't map registers\n"); 588 return; 589 } 590 sc->sc_phandle = faa->faa_phandle; 591 sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data; 592 593 aprint_naive("\n"); 594 aprint_normal(": %s\n", sc->sc_conf->descr); 595 596 if (sc->sc_conf->init != NULL) 597 sc->sc_conf->init(sc); 598 599 sc->sc_ports.dp_ep_activate = rk_vop_ep_activate; 600 sc->sc_ports.dp_ep_get_data = rk_vop_ep_get_data; 601 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_CRTC); 602 603 const int port_phandle = of_find_firstchild_byname(phandle, "port"); 604 if (port_phandle > 0) 605 rk_drm_register_port(port_phandle, &sc->sc_ports); 606 } 607 608 CFATTACH_DECL_NEW(rk_vop, sizeof(struct rk_vop_softc), 609 rk_vop_match, rk_vop_attach, NULL, NULL); 610
Indexes created Thu Oct 02 14:10:14 GMT 2025