s3c2400reg.h revision 1.3.4.2
1 1.3.4.2 skrll /* $NetBSD: s3c2400reg.h,v 1.3.4.2 2004/08/03 10:32:50 skrll Exp $ */ 2 1.3.4.2 skrll 3 1.3.4.2 skrll /* 4 1.3.4.2 skrll * Copyright (c) 2002, 2003 Genetec corp. All rights reserved. 5 1.3.4.2 skrll * Written by Hiroyuki Bessho for Genetec corp. 6 1.3.4.2 skrll * 7 1.3.4.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.3.4.2 skrll * modification, are permitted provided that the following conditions 9 1.3.4.2 skrll * are met: 10 1.3.4.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.3.4.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.3.4.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.4.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.3.4.2 skrll * documentation and/or other materials provided with the distribution. 15 1.3.4.2 skrll * 3. The name of Genetec corporation may not be used to endorse 16 1.3.4.2 skrll * or promote products derived from this software without specific prior 17 1.3.4.2 skrll * written permission. 18 1.3.4.2 skrll * 19 1.3.4.2 skrll * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 1.3.4.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.3.4.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.3.4.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 1.3.4.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.3.4.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.3.4.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.3.4.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.3.4.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.3.4.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.3.4.2 skrll * POSSIBILITY OF SUCH DAMAGE. 30 1.3.4.2 skrll */ 31 1.3.4.2 skrll 32 1.3.4.2 skrll 33 1.3.4.2 skrll /* 34 1.3.4.2 skrll * Samsung S3C2400 processor is ARM920T based integrated CPU 35 1.3.4.2 skrll * 36 1.3.4.2 skrll * Reference: 37 1.3.4.2 skrll * S3C2400X User's Manual 38 1.3.4.2 skrll */ 39 1.3.4.2 skrll #ifndef _ARM_S3C2400_S3C24X0REG_H_ 40 1.3.4.2 skrll #define _ARM_S3C2400_S3C24X0REG_H_ 41 1.3.4.2 skrll 42 1.3.4.2 skrll /* common definitions for S3C2800, S3C2400X and S3C2410X */ 43 1.3.4.2 skrll #include <arm/s3c2xx0/s3c2xx0reg.h> 44 1.3.4.2 skrll 45 1.3.4.2 skrll /* 46 1.3.4.2 skrll * Memory Map 47 1.3.4.2 skrll */ 48 1.3.4.2 skrll 49 1.3.4.2 skrll #define S3C2400_BANK_START(n) (0x02000000*(n)) 50 1.3.4.2 skrll #define S3C2400_SDRAM_START S3C2400_BANK_START(6) 51 1.3.4.2 skrll #define S3C2400_AHB_START 0x14000000 52 1.3.4.2 skrll #define S3C2400_APB_START 0x15000000 53 1.3.4.2 skrll 54 1.3.4.2 skrll /* 55 1.3.4.2 skrll * Physical address of integrated peripherals 56 1.3.4.2 skrll */ 57 1.3.4.2 skrll #define S3C2400_MEMCTL_BASE 0x14000000 /* memory controller */ 58 1.3.4.2 skrll #define S3C2400_USBHC_BASE 0x14200000 /* USB Host controller */ 59 1.3.4.2 skrll #define S3C2400_INTCTL_BASE 0x14400000 /* Interrupt controller */ 60 1.3.4.2 skrll #define S3C2400_INTCTL_SIZE 0x18 61 1.3.4.2 skrll #define S3C2400_DMAC_BASE 0x14600000 /* DMA controllers */ 62 1.3.4.2 skrll #define S3C2400_DMAC_SIZE 0x80 63 1.3.4.2 skrll #define S3C2400_CLKMAN_BASE 0x14800000 /* clock & power management */ 64 1.3.4.2 skrll #define S3C2400_CLKMAN_SIZE 0x18 65 1.3.4.2 skrll #define S3C2400_LCDC_BASE 0x14a00000 66 1.3.4.2 skrll #define S3C2400_UART_BASE 0x15000000 67 1.3.4.2 skrll #define S3C2400_UART_BASE(n) (S3C2400_UART_BASE+0x4000*(n)) 68 1.3.4.2 skrll #define S3C2400_TIMER_BASE 0x15100000 /* Timers */ 69 1.3.4.2 skrll #define S3C2400_USBDC_BASE 0x15200000 /* USB Device controller */ 70 1.3.4.2 skrll #define S3C2400_USBDC_SIZE 0x1fc 71 1.3.4.2 skrll #define S3C2400_WDT_BASE 0x15300000 /* Watch dog timer */ 72 1.3.4.2 skrll #define S3C2400_IIC_BASE 0x15400000 73 1.3.4.2 skrll #define S3C2400_IIS_BASE 0x15508000 74 1.3.4.2 skrll #define S3C2400_GPIO_BASE 0x15600000 75 1.3.4.2 skrll #define S3C2400_GPIO_SIZE 0x5c 76 1.3.4.2 skrll #define S3C2400_RTC_BASE 0x15700040 77 1.3.4.2 skrll #define S3C2400_RTC_SIZE 0x4c 78 1.3.4.2 skrll #define S3C2400_ADC_BASE 0x15800000 /* A/D converter */ 79 1.3.4.2 skrll #define S3C2400_ADC_SIZE 0x08 80 1.3.4.2 skrll #define S3C2400_SPI_BASE 0x15900000 81 1.3.4.2 skrll #define S3C2400_MMC_BASE 0x15a00000 82 1.3.4.2 skrll #define S3C2400_MMC_SIZE 0x40 83 1.3.4.2 skrll 84 1.3.4.2 skrll /* GPIO */ 85 1.3.4.2 skrll #define GPIO_PACON 0x00 /* port A configuration */ 86 1.3.4.2 skrll #define PCON_INPUT 0 /* Input port */ 87 1.3.4.2 skrll #define PCON_OUTPUT 1 /* Output port */ 88 1.3.4.2 skrll #define PCON_ALTFUN 2 /* Alternate function */ 89 1.3.4.2 skrll #define GPIO_PADAT 0x04 /* port A data */ 90 1.3.4.2 skrll #define GPIO_PBCON 0x08 91 1.3.4.2 skrll #define GPIO_PBDAT 0x0c 92 1.3.4.2 skrll #define GPIO_PBUP 0x10 93 1.3.4.2 skrll #define GPIO_PCCON 0x14 94 1.3.4.2 skrll #define GPIO_PCDAT 0x18 95 1.3.4.2 skrll #define GPIO_PCUP 0x1c 96 1.3.4.2 skrll #define GPIO_PDCON 0x20 97 1.3.4.2 skrll #define GPIO_PDDAT 0x24 98 1.3.4.2 skrll #define GPIO_PDUP 0x28 99 1.3.4.2 skrll #define GPIO_PECON 0x3c 100 1.3.4.2 skrll #define GPIO_PEDAT 0x30 101 1.3.4.2 skrll #define GPIO_PEUP 0x34 102 1.3.4.2 skrll #define GPIO_PFCON 0x38 103 1.3.4.2 skrll #define GPIO_PFDAT 0x3c 104 1.3.4.2 skrll #define GPIO_PFUP 0x40 105 1.3.4.2 skrll #define GPIO_PGCON 0x44 106 1.3.4.2 skrll #define GPIO_PGDAT 0x49 107 1.3.4.2 skrll #define GPIO_PGUP 0x4c 108 1.3.4.2 skrll #define GPIO_OPENCR 0x50 /* Open drain enable */ 109 1.3.4.2 skrll #define GPIO_MISCCR 0x54 /* miscellaneous control */ 110 1.3.4.2 skrll 111 1.3.4.2 skrll #define GPIO_EXTINTR 0x48 /* external interrupt control */ 112 1.3.4.2 skrll #define EXTINTR_LOW 0x00 113 1.3.4.2 skrll #define EXTINTR_HIGH 0x01 114 1.3.4.2 skrll #define EXTINTR_FALLING 0x02 115 1.3.4.2 skrll #define EXTINTR_RISING 0x04 116 1.3.4.2 skrll #define EXTINTR_BOTH 0x06 117 1.3.4.2 skrll 118 1.3.4.2 skrll /* MMC */ /* XXX */ 119 1.3.4.2 skrll 120 1.3.4.2 skrll #endif /* _ARM_S3C2400_S3C2400REG_H_ */ 121
Indexes created Tue Oct 28 12:10:06 GMT 2025