s3c2410.c revision 1.5.2.2
1 1.5.2.2 skrll /* $NetBSD: s3c2410.c,v 1.5.2.2 2004/08/03 10:32:50 skrll Exp $ */ 2 1.5.2.2 skrll 3 1.5.2.2 skrll /* 4 1.5.2.2 skrll * Copyright (c) 2003 Genetec corporation. All rights reserved. 5 1.5.2.2 skrll * Written by Hiroyuki Bessho for Genetec corporation. 6 1.5.2.2 skrll * 7 1.5.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.5.2.2 skrll * modification, are permitted provided that the following conditions 9 1.5.2.2 skrll * are met: 10 1.5.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.5.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.5.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.5.2.2 skrll * 3. The name of Genetec corporation may not be used to endorse 16 1.5.2.2 skrll * or promote products derived from this software without specific prior 17 1.5.2.2 skrll * written permission. 18 1.5.2.2 skrll * 19 1.5.2.2 skrll * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 1.5.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.5.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.5.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 1.5.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.5.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.5.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.5.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.5.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.5.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.5.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 30 1.5.2.2 skrll */ 31 1.5.2.2 skrll 32 1.5.2.2 skrll #include <sys/cdefs.h> 33 1.5.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: s3c2410.c,v 1.5.2.2 2004/08/03 10:32:50 skrll Exp $"); 34 1.5.2.2 skrll 35 1.5.2.2 skrll #include <sys/param.h> 36 1.5.2.2 skrll #include <sys/systm.h> 37 1.5.2.2 skrll #include <sys/device.h> 38 1.5.2.2 skrll #include <sys/kernel.h> 39 1.5.2.2 skrll #include <sys/reboot.h> 40 1.5.2.2 skrll 41 1.5.2.2 skrll #include <machine/cpu.h> 42 1.5.2.2 skrll #include <machine/bus.h> 43 1.5.2.2 skrll 44 1.5.2.2 skrll #include <arm/cpufunc.h> 45 1.5.2.2 skrll #include <arm/mainbus/mainbus.h> 46 1.5.2.2 skrll #include <arm/s3c2xx0/s3c2410reg.h> 47 1.5.2.2 skrll #include <arm/s3c2xx0/s3c2410var.h> 48 1.5.2.2 skrll 49 1.5.2.2 skrll #include "locators.h" 50 1.5.2.2 skrll #include "opt_cpuoptions.h" 51 1.5.2.2 skrll 52 1.5.2.2 skrll /* prototypes */ 53 1.5.2.2 skrll static int s3c2410_match(struct device *, struct cfdata *, void *); 54 1.5.2.2 skrll static void s3c2410_attach(struct device *, struct device *, void *); 55 1.5.2.2 skrll static int s3c2410_search(struct device *, struct cfdata *, void *); 56 1.5.2.2 skrll 57 1.5.2.2 skrll /* attach structures */ 58 1.5.2.2 skrll CFATTACH_DECL(ssio, sizeof(struct s3c24x0_softc), s3c2410_match, s3c2410_attach, 59 1.5.2.2 skrll NULL, NULL); 60 1.5.2.2 skrll 61 1.5.2.2 skrll extern struct bus_space s3c2xx0_bs_tag; 62 1.5.2.2 skrll 63 1.5.2.2 skrll struct s3c2xx0_softc *s3c2xx0_softc; 64 1.5.2.2 skrll 65 1.5.2.2 skrll #ifdef DEBUG_PORTF 66 1.5.2.2 skrll volatile uint8_t *portf; /* for debug */ 67 1.5.2.2 skrll #endif 68 1.5.2.2 skrll 69 1.5.2.2 skrll static int 70 1.5.2.2 skrll s3c2410_print(void *aux, const char *name) 71 1.5.2.2 skrll { 72 1.5.2.2 skrll struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *) aux; 73 1.5.2.2 skrll 74 1.5.2.2 skrll if (sa->sa_size) 75 1.5.2.2 skrll aprint_normal(" addr 0x%lx", sa->sa_addr); 76 1.5.2.2 skrll if (sa->sa_size > 1) 77 1.5.2.2 skrll aprint_normal("-0x%lx", sa->sa_addr + sa->sa_size - 1); 78 1.5.2.2 skrll if (sa->sa_intr != SSIOCF_INTR_DEFAULT) 79 1.5.2.2 skrll aprint_normal(" intr %d", sa->sa_intr); 80 1.5.2.2 skrll if (sa->sa_index != SSIOCF_INDEX_DEFAULT) 81 1.5.2.2 skrll aprint_normal(" unit %d", sa->sa_index); 82 1.5.2.2 skrll 83 1.5.2.2 skrll return (UNCONF); 84 1.5.2.2 skrll } 85 1.5.2.2 skrll 86 1.5.2.2 skrll int 87 1.5.2.2 skrll s3c2410_match(struct device *parent, struct cfdata *match, void *aux) 88 1.5.2.2 skrll { 89 1.5.2.2 skrll return 1; 90 1.5.2.2 skrll } 91 1.5.2.2 skrll 92 1.5.2.2 skrll void 93 1.5.2.2 skrll s3c2410_attach(struct device *parent, struct device *self, void *aux) 94 1.5.2.2 skrll { 95 1.5.2.2 skrll struct s3c24x0_softc *sc = (struct s3c24x0_softc *) self; 96 1.5.2.2 skrll bus_space_tag_t iot; 97 1.5.2.2 skrll const char *which_registers; /* for panic message */ 98 1.5.2.2 skrll 99 1.5.2.2 skrll #define FAIL(which) do { \ 100 1.5.2.2 skrll which_registers=(which); goto abort; }while(/*CONSTCOND*/0) 101 1.5.2.2 skrll 102 1.5.2.2 skrll s3c2xx0_softc = &(sc->sc_sx); 103 1.5.2.2 skrll sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag; 104 1.5.2.2 skrll 105 1.5.2.2 skrll if (bus_space_map(iot, 106 1.5.2.2 skrll S3C2410_INTCTL_BASE, S3C2410_INTCTL_SIZE, 107 1.5.2.2 skrll BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh)) 108 1.5.2.2 skrll FAIL("intc"); 109 1.5.2.2 skrll /* tell register addresses to interrupt handler */ 110 1.5.2.2 skrll s3c2410_intr_init(sc); 111 1.5.2.2 skrll 112 1.5.2.2 skrll /* Map the GPIO registers */ 113 1.5.2.2 skrll if (bus_space_map(iot, S3C2410_GPIO_BASE, S3C2410_GPIO_SIZE, 114 1.5.2.2 skrll 0, &sc->sc_sx.sc_gpio_ioh)) 115 1.5.2.2 skrll FAIL("GPIO"); 116 1.5.2.2 skrll #ifdef DEBUG_PORTF 117 1.5.2.2 skrll { 118 1.5.2.2 skrll extern volatile uint8_t *portf; 119 1.5.2.2 skrll /* make all ports output */ 120 1.5.2.2 skrll bus_space_write_2(iot, sc->sc_sx.sc_gpio_ioh, GPIO_PCONF, 0x5555); 121 1.5.2.2 skrll portf = (volatile uint8_t *) 122 1.5.2.2 skrll ((char *)bus_space_vaddr(iot, sc->sc_sx.sc_gpio_ioh) + GPIO_PDATF); 123 1.5.2.2 skrll } 124 1.5.2.2 skrll #endif 125 1.5.2.2 skrll 126 1.5.2.2 skrll #if 0 127 1.5.2.2 skrll /* Map the DMA controller registers */ 128 1.5.2.2 skrll if (bus_space_map(iot, S3C2410_DMAC_BASE, S3C2410_DMAC_SIZE, 129 1.5.2.2 skrll 0, &sc->sc_sx.sc_dmach)) 130 1.5.2.2 skrll FAIL("DMAC"); 131 1.5.2.2 skrll #endif 132 1.5.2.2 skrll 133 1.5.2.2 skrll /* Memory controller */ 134 1.5.2.2 skrll if (bus_space_map(iot, S3C2410_MEMCTL_BASE, 135 1.5.2.2 skrll S3C24X0_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh)) 136 1.5.2.2 skrll FAIL("MEMC"); 137 1.5.2.2 skrll /* Clock manager */ 138 1.5.2.2 skrll if (bus_space_map(iot, S3C2410_CLKMAN_BASE, 139 1.5.2.2 skrll S3C24X0_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh)) 140 1.5.2.2 skrll FAIL("CLK"); 141 1.5.2.2 skrll 142 1.5.2.2 skrll #if 0 143 1.5.2.2 skrll /* Real time clock */ 144 1.5.2.2 skrll if (bus_space_map(iot, S3C2410_RTC_BASE, 145 1.5.2.2 skrll S3C24X0_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh)) 146 1.5.2.2 skrll FAIL("RTC"); 147 1.5.2.2 skrll #endif 148 1.5.2.2 skrll 149 1.5.2.2 skrll if (bus_space_map(iot, S3C2410_TIMER_BASE, 150 1.5.2.2 skrll S3C24X0_TIMER_SIZE, 0, &sc->sc_timer_ioh)) 151 1.5.2.2 skrll FAIL("TIMER"); 152 1.5.2.2 skrll 153 1.5.2.2 skrll /* calculate current clock frequency */ 154 1.5.2.2 skrll s3c24x0_clock_freq(&sc->sc_sx); 155 1.5.2.2 skrll printf(": fclk %d MHz hclk %d MHz pclk %d MHz", 156 1.5.2.2 skrll sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000, 157 1.5.2.2 skrll sc->sc_sx.sc_pclk / 1000000); 158 1.5.2.2 skrll 159 1.5.2.2 skrll printf("\n"); 160 1.5.2.2 skrll 161 1.5.2.2 skrll /* get busdma tag for the platform */ 162 1.5.2.2 skrll sc->sc_sx.sc_dmat = s3c2xx0_bus_dma_init(&s3c2xx0_bus_dma); 163 1.5.2.2 skrll 164 1.5.2.2 skrll /* 165 1.5.2.2 skrll * Attach devices. 166 1.5.2.2 skrll */ 167 1.5.2.2 skrll config_search(s3c2410_search, self, NULL); 168 1.5.2.2 skrll return; 169 1.5.2.2 skrll 170 1.5.2.2 skrll abort: 171 1.5.2.2 skrll panic("%s: unable to map %s registers", 172 1.5.2.2 skrll self->dv_xname, which_registers); 173 1.5.2.2 skrll 174 1.5.2.2 skrll #undef FAIL 175 1.5.2.2 skrll } 176 1.5.2.2 skrll 177 1.5.2.2 skrll int 178 1.5.2.2 skrll s3c2410_search(struct device * parent, struct cfdata * cf, void *aux) 179 1.5.2.2 skrll { 180 1.5.2.2 skrll struct s3c24x0_softc *sc = (struct s3c24x0_softc *) parent; 181 1.5.2.2 skrll struct s3c2xx0_attach_args aa; 182 1.5.2.2 skrll 183 1.5.2.2 skrll aa.sa_sc = sc; 184 1.5.2.2 skrll aa.sa_iot = sc->sc_sx.sc_iot; 185 1.5.2.2 skrll aa.sa_addr = cf->cf_loc[SSIOCF_ADDR]; 186 1.5.2.2 skrll aa.sa_size = cf->cf_loc[SSIOCF_SIZE]; 187 1.5.2.2 skrll aa.sa_index = cf->cf_loc[SSIOCF_INDEX]; 188 1.5.2.2 skrll aa.sa_intr = cf->cf_loc[SSIOCF_INTR]; 189 1.5.2.2 skrll 190 1.5.2.2 skrll aa.sa_dmat = sc->sc_sx.sc_dmat; 191 1.5.2.2 skrll 192 1.5.2.2 skrll if (config_match(parent, cf, &aa)) 193 1.5.2.2 skrll config_attach(parent, cf, &aa, s3c2410_print); 194 1.5.2.2 skrll 195 1.5.2.2 skrll return 0; 196 1.5.2.2 skrll } 197 1.5.2.2 skrll 198 1.5.2.2 skrll /* 199 1.5.2.2 skrll * fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register. 200 1.5.2.2 skrll */ 201 1.5.2.2 skrll void 202 1.5.2.2 skrll s3c24x0_clock_freq(struct s3c2xx0_softc *sc) 203 1.5.2.2 skrll { 204 1.5.2.2 skrll int mdiv, pdiv, sdiv; 205 1.5.2.2 skrll int pllcon, divn; 206 1.5.2.2 skrll 207 1.5.2.2 skrll pllcon = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, 208 1.5.2.2 skrll CLKMAN_MPLLCON); 209 1.5.2.2 skrll divn = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, 210 1.5.2.2 skrll CLKMAN_CLKDIVN); 211 1.5.2.2 skrll 212 1.5.2.2 skrll mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; 213 1.5.2.2 skrll pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT; 214 1.5.2.2 skrll sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT; 215 1.5.2.2 skrll 216 1.5.2.2 skrll sc->sc_fclk = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / 217 1.5.2.2 skrll ((pdiv + 2) * (1 << sdiv)); 218 1.5.2.2 skrll sc->sc_hclk = sc->sc_fclk; 219 1.5.2.2 skrll if (divn & CLKDIVN_HDIVN) 220 1.5.2.2 skrll sc->sc_hclk /= 2; 221 1.5.2.2 skrll sc->sc_pclk = sc->sc_hclk; 222 1.5.2.2 skrll if (divn & CLKDIVN_PDIVN) 223 1.5.2.2 skrll sc->sc_pclk /= 2; 224 1.5.2.2 skrll } 225 1.5.2.2 skrll 226 1.5.2.2 skrll /* 227 1.5.2.2 skrll * Issue software reset command. 228 1.5.2.2 skrll * called with MMU off. 229 1.5.2.2 skrll * 230 1.5.2.2 skrll * S3C2410 doesn't have sowtware reset bit like S3C2800. 231 1.5.2.2 skrll * use watch dog timer and make it fire immediately. 232 1.5.2.2 skrll */ 233 1.5.2.2 skrll void 234 1.5.2.2 skrll s3c2410_softreset(void) 235 1.5.2.2 skrll { 236 1.5.2.2 skrll disable_interrupts(I32_bit|F32_bit); 237 1.5.2.2 skrll 238 1.5.2.2 skrll *(volatile unsigned int *)(S3C2410_WDT_BASE + WDT_WTCON) 239 1.5.2.2 skrll = (0 << WTCON_PRESCALE_SHIFT) | WTCON_ENABLE | 240 1.5.2.2 skrll WTCON_CLKSEL_16 | WTCON_ENRST; 241 1.5.2.2 skrll } 242 1.5.2.2 skrll 243 1.5.2.2 skrll 244
Indexes created Sun Oct 26 21:10:03 GMT 2025