s3c2410_intr.c revision 1.13
1 /* $NetBSD: s3c2410_intr.c,v 1.13 2011/07/01 20:31:39 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Genetec corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corporation may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * IRQ handler for Samsung S3C2410 processor. 34 * It has integrated interrupt controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.13 2011/07/01 20:31:39 dyoung Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/malloc.h> 43 44 #include <sys/bus.h> 45 #include <machine/intr.h> 46 47 #include <arm/cpufunc.h> 48 49 #include <arm/s3c2xx0/s3c2410reg.h> 50 #include <arm/s3c2xx0/s3c2410var.h> 51 52 /* 53 * interrupt dispatch table. 54 */ 55 56 struct s3c2xx0_intr_dispatch handler[ICU_LEN]; 57 58 59 volatile int intr_mask; 60 #ifdef __HAVE_FAST_SOFTINTS 61 volatile int softint_pending; 62 volatile int soft_intr_mask; 63 #endif 64 volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */ 65 66 /* interrupt masks for each level */ 67 int s3c2xx0_imask[NIPL]; 68 int s3c2xx0_ilevel[ICU_LEN]; 69 #ifdef __HAVE_FAST_SOFTINTS 70 int s3c24x0_soft_imask[NIPL]; 71 #endif 72 73 vaddr_t intctl_base; /* interrupt controller registers */ 74 #define icreg(offset) \ 75 (*(volatile uint32_t *)(intctl_base+(offset))) 76 77 #ifdef __HAVE_FAST_SOFTINTS 78 /* 79 * Map a software interrupt queue to an interrupt priority level. 80 */ 81 static const int si_to_ipl[] = { 82 [SI_SOFTBIO] = IPL_SOFTBIO, 83 [SI_SOFTCLOCK] = IPL_SOFTCLOCK, 84 [SI_SOFTNET] = IPL_SOFTNET, 85 [SI_SOFTSERIAL] = IPL_SOFTSERIAL, 86 }; 87 #endif 88 89 #define PENDING_CLEAR_MASK (~0) 90 91 /* 92 * called from irq_entry. 93 */ 94 void s3c2410_irq_handler(struct clockframe *); 95 void 96 s3c2410_irq_handler(struct clockframe *frame) 97 { 98 uint32_t irqbits; 99 int irqno; 100 int saved_spl_level; 101 102 saved_spl_level = curcpl(); 103 104 #ifdef DIAGNOSTIC 105 if (curcpu()->ci_intr_depth > 10) 106 panic("nested intr too deep"); 107 #endif 108 109 while ((irqbits = icreg(INTCTL_INTPND)) != 0) { 110 111 /* Note: Only one bit in INTPND register is set */ 112 113 irqno = icreg(INTCTL_INTOFFSET); 114 115 #ifdef DIAGNOSTIC 116 if (__predict_false((irqbits & (1<<irqno)) == 0)) { 117 /* This shouldn't happen */ 118 printf("INTOFFSET=%d, INTPND=%x\n", irqno, irqbits); 119 break; 120 } 121 #endif 122 /* raise spl to stop interrupts of lower priorities */ 123 if (saved_spl_level < handler[irqno].level) 124 s3c2xx0_setipl(handler[irqno].level); 125 126 /* clear pending bit */ 127 icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno); 128 icreg(INTCTL_INTPND) = PENDING_CLEAR_MASK & (1 << irqno); 129 130 enable_interrupts(I32_bit); /* allow nested interrupts */ 131 132 (*handler[irqno].func) ( 133 handler[irqno].cookie == 0 134 ? frame : handler[irqno].cookie); 135 136 disable_interrupts(I32_bit); 137 138 /* restore spl to that was when this interrupt happen */ 139 s3c2xx0_setipl(saved_spl_level); 140 141 } 142 143 #ifdef __HAVE_FAST_SOFTINTS 144 cpu_dosoftints(); 145 #endif 146 } 147 148 /* 149 * Handler for main IRQ of cascaded interrupts. 150 */ 151 static int 152 cascade_irq_handler(void *cookie) 153 { 154 int index = (int)cookie - 1; 155 uint32_t irqbits; 156 int irqno, i; 157 int save = disable_interrupts(I32_bit); 158 159 KASSERT(0 <= index && index <= 3); 160 161 irqbits = icreg(INTCTL_SUBSRCPND) & 162 ~icreg(INTCTL_INTSUBMSK) & (0x07 << (3*index)); 163 164 for (irqno = 3*index; irqbits; ++irqno) { 165 if ((irqbits & (1<<irqno)) == 0) 166 continue; 167 168 /* clear pending bit */ 169 irqbits &= ~(1<<irqno); 170 icreg(INTCTL_SUBSRCPND) = (1 << irqno); 171 172 /* allow nested interrupts. SPL is already set 173 * correctly by main handler. */ 174 restore_interrupts(save); 175 176 i = S3C2410_SUBIRQ_MIN + irqno; 177 (* handler[i].func)(handler[i].cookie); 178 179 disable_interrupts(I32_bit); 180 } 181 182 return 1; 183 } 184 185 186 static const uint8_t subirq_to_main[] = { 187 S3C2410_INT_UART0, 188 S3C2410_INT_UART0, 189 S3C2410_INT_UART0, 190 S3C2410_INT_UART1, 191 S3C2410_INT_UART1, 192 S3C2410_INT_UART1, 193 S3C2410_INT_UART2, 194 S3C2410_INT_UART2, 195 S3C2410_INT_UART2, 196 S3C24X0_INT_ADCTC, 197 S3C24X0_INT_ADCTC, 198 }; 199 200 void * 201 s3c24x0_intr_establish(int irqno, int level, int type, 202 int (* func) (void *), void *cookie) 203 { 204 int save; 205 206 if (irqno < 0 || irqno >= ICU_LEN || 207 type < IST_NONE || IST_EDGE_BOTH < type) 208 panic("intr_establish: bogus irq or type"); 209 210 save = disable_interrupts(I32_bit); 211 212 handler[irqno].cookie = cookie; 213 handler[irqno].func = func; 214 handler[irqno].level = level; 215 216 if (irqno >= S3C2410_SUBIRQ_MIN) { 217 /* cascaded interrupts. */ 218 int main_irqno; 219 int i = (irqno - S3C2410_SUBIRQ_MIN); 220 221 main_irqno = subirq_to_main[i]; 222 223 /* establish main irq if first time 224 * be careful that cookie shouldn't be 0 */ 225 if (handler[main_irqno].func != cascade_irq_handler) 226 s3c24x0_intr_establish(main_irqno, level, type, 227 cascade_irq_handler, (void *)((i/3) + 1)); 228 229 /* unmask it in submask register */ 230 icreg(INTCTL_INTSUBMSK) &= ~(1<<i); 231 232 restore_interrupts(save); 233 return &handler[irqno]; 234 } 235 236 s3c2xx0_update_intr_masks(irqno, level); 237 238 /* 239 * set trigger type for external interrupts 0..3 240 */ 241 if (irqno <= S3C24X0_INT_EXT(3)) { 242 /* 243 * Update external interrupt control 244 */ 245 s3c2410_setup_extint(irqno, type); 246 } 247 248 s3c2xx0_setipl(curcpl()); 249 250 restore_interrupts(save); 251 252 return &handler[irqno]; 253 } 254 255 256 static void 257 init_interrupt_masks(void) 258 { 259 int i; 260 261 for (i=0; i < NIPL; ++i) 262 s3c2xx0_imask[i] = 0; 263 264 #ifdef __HAVE_FAST_SOFTINTS 265 s3c24x0_soft_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) | 266 SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) | 267 SI_TO_IRQBIT(SI_SOFT); 268 269 s3c24x0_soft_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) | 270 SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK); 271 272 /* 273 * splsoftclock() is the only interface that users of the 274 * generic software interrupt facility have to block their 275 * soft intrs, so splsoftclock() must also block IPL_SOFT. 276 */ 277 s3c24x0_soft_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) | 278 SI_TO_IRQBIT(SI_SOFTNET); 279 280 /* 281 * splsoftnet() must also block splsoftclock(), since we don't 282 * want timer-driven network events to occur while we're 283 * processing incoming packets. 284 */ 285 s3c24x0_soft_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTSERIAL); 286 287 for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i) 288 s3c24x0_soft_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL); 289 #endif 290 } 291 292 void 293 s3c2410_intr_init(struct s3c24x0_softc *sc) 294 { 295 intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot, 296 sc->sc_sx.sc_intctl_ioh); 297 298 s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK); 299 300 /* clear all pending interrupt */ 301 icreg(INTCTL_SRCPND) = ~0; 302 icreg(INTCTL_INTPND) = ~0; 303 304 /* mask all sub interrupts */ 305 icreg(INTCTL_INTSUBMSK) = 0x7ff; 306 307 init_interrupt_masks(); 308 309 s3c2xx0_intr_init(handler, ICU_LEN); 310 311 } 312 313 314 /* 315 * mask/unmask sub interrupts 316 */ 317 void 318 s3c2410_mask_subinterrupts(int bits) 319 { 320 int psw = disable_interrupts(IF32_bits); 321 icreg(INTCTL_INTSUBMSK) |= bits; 322 restore_interrupts(psw); 323 } 324 325 void 326 s3c2410_unmask_subinterrupts(int bits) 327 { 328 int psw = disable_interrupts(IF32_bits); 329 icreg(INTCTL_INTSUBMSK) &= ~bits; 330 restore_interrupts(psw); 331 } 332 333 /* 334 * Update external interrupt control 335 */ 336 static const u_char s3c24x0_ist[] = { 337 EXTINTR_LOW, /* NONE */ 338 EXTINTR_FALLING, /* PULSE */ 339 EXTINTR_FALLING, /* EDGE */ 340 EXTINTR_LOW, /* LEVEL */ 341 EXTINTR_HIGH, 342 EXTINTR_RISING, 343 EXTINTR_BOTH, 344 }; 345 346 void 347 s3c2410_setup_extint(int extint, int type) 348 { 349 uint32_t reg; 350 u_int trig; 351 int i = extint % 8; 352 int regidx = extint/8; /* GPIO_EXTINT[0:2] */ 353 int save; 354 355 trig = s3c24x0_ist[type]; 356 357 save = disable_interrupts(I32_bit); 358 359 reg = bus_space_read_4(s3c2xx0_softc->sc_iot, 360 s3c2xx0_softc->sc_gpio_ioh, 361 GPIO_EXTINT(regidx)); 362 363 reg = reg & ~(0x07 << (4*i)); 364 reg |= trig << (4*i); 365 366 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, 367 GPIO_EXTINT(regidx), reg); 368 369 restore_interrupts(save); 370 } 371
Indexes created Mon Sep 29 03:10:08 GMT 2025