s3c2410reg.h revision 1.2
1 /* $NetBSD: s3c2410reg.h,v 1.2 2003/08/04 10:24:15 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Genetec corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corporation may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 /* 34 * Samsung S3C2410X processor is ARM920T based integrated CPU 35 * 36 * Reference: 37 * S3C2410X User's Manual 38 */ 39 #ifndef _ARM_S3C2XX0_S3C2410REG_H_ 40 #define _ARM_S3C2XX0_S3C2410REG_H_ 41 42 /* common definitions for S3C2800, S3C2400 and S3C2410 */ 43 #include <arm/s3c2xx0/s3c2xx0reg.h> 44 /* common definitions for S3C2400 and S3C2410 */ 45 #include <arm/s3c2xx0/s3c24x0reg.h> 46 47 /* 48 * Memory Map 49 */ 50 #define S3C2410_BANK_SIZE 0x08000000 51 #define S3C2410_BANK_START(n) (S3C2410_BANK_SIZE*(n)) 52 #define S3C2410_SDRAM_START S3C2410_BANK_START(6) 53 54 /* 55 * Physical address of integrated peripherals 56 */ 57 #define S3C2410_MEMCTL_BASE 0x48000000 /* memory controller */ 58 #define S3C2410_MEMCTL_SIZE 0x34 59 #define S3C2410_USBHC_BASE 0x49000000 /* USB Host controller */ 60 #define S3C2410_USBHC_SIZE 0x5c 61 #define S3C2410_INTCTL_BASE 0x4a000000 /* Interrupt controller */ 62 #define S3C2410_INTCTL_SIZE 0x20 63 #define S3C2410_DMAC_BASE 0x4b000000 64 #define S3C2410_DMAC_SIZE 0xe4 65 #define S3C2410_CLKMAN_BASE 0x4c000000 /* clock & power management */ 66 #define S3C2410_CLKMAN_SIZE 0x18 67 #define S3C2410_LCDC_BASE 0x4d000000 /* LCD controller */ 68 #define S3C2410_LCDC_SIZE 0x64 69 #define S3C2410_NANDFC_BASE 0x4e000000 /* NAND Flash controller */ 70 #define S3C2410_NANDFC_SIZE 0x18 71 #define S3C2410_UART0_BASE 0x50000000 72 #define S3C2410_UART_BASE(n) (S3C2410_UART0_BASE+0x4000*(n)) 73 #define S3C2410_UART_SIZE 0x2c 74 #define S3C2410_TIMER_BASE 0x51000000 75 #define S3C2410_TIMER_SIZE 0x44 76 #define S3C2410_USBDC_BASE 0x5200140 77 #define S3C2410_USBDC_SIZE 0x130 78 #define S3C2410_WDT_BASE 0x53000000 79 #define S3C2410_WDT_SIZE 0x0c 80 #define S3C2410_IIC_BASE 0x54000000 81 #define S3C2410_IIC_SIZE 0x0c 82 #define S3C2410_IIS_BASE 0x55000000 83 #define S3C2410_IIS_SIZE 0x14 84 #define S3C2410_GPIO_BASE 0x56000000 85 #define S3C2410_GPIO_SIZE 0xb4 86 #define S3C2410_ADC_BASE 0x58000000 87 #define S3C2410_ADC_SIZE 0x14 88 #define S3C2410_SPI0_BASE 0x59000000 89 #define S3C2410_SPI1_BASE 0x59000020 90 #define S3C2410_SPI1_SIZE 0x18 91 #define S3C2410_SDI_BASE 0x5a000000 /* SD Interface */ 92 #define S3C2410_SDI_SIZE 0x44 93 94 /* interrupt control (additional defs for 2410) */ 95 #define ICU_LEN (32+11) 96 97 #define INTCTL_SUBSRCPND 0x18 /* sub source pending (2410 only) */ 98 #define INTCTL_INTSUBMSK 0x1c /* sub mask (2410 only) */ 99 100 /* 2410 has more than 32 interrupt sources. These are sub-sources 101 * that are OR-ed into main interrupt sources, and controlled via 102 * SUBSRCPND and SUBSRCMSK registers */ 103 104 #define S3C2410_SUBIRQ_MIN 32 105 #define S3C2410_SUBIRQ_MAX (32+10) 106 107 /* cascaded to INT_ADCTC */ 108 #define S3C2410_INT_ADC (S3C2410_SUBIRQ_MIN+10) /* AD converter */ 109 #define S3C2410_INT_TC (S3C2410_SUBIRQ_MIN+9) /* Touch screen */ 110 /* cascaded to INT_UART2 */ 111 #define S3C2410_INT_ERR2 (S3C2410_SUBIRQ_MIN+8) /* UART2 Error interrupt */ 112 #define S3C2410_INT_TXD2 (S3C2410_SUBIRQ_MIN+7) /* UART2 Tx interrupt */ 113 #define S3C2410_INT_RXD2 (S3C2410_SUBIRQ_MIN+6) /* UART2 Rx interrupt */ 114 /* cascaded to INT_UART1 */ 115 #define S3C2410_INT_ERR1 (S3C2410_SUBIRQ_MIN+5) /* UART1 Error interrupt */ 116 #define S3C2410_INT_TXD1 (S3C2410_SUBIRQ_MIN+4) /* UART1 Tx interrupt */ 117 #define S3C2410_INT_RXD1 (S3C2410_SUBIRQ_MIN+3) /* UART1 Rx interrupt */ 118 /* cascaded to INT_UART0 */ 119 #define S3C2410_INT_ERR0 (S3C2410_SUBIRQ_MIN+2) /* UART0 Error interrupt */ 120 #define S3C2410_INT_TXD0 (S3C2410_SUBIRQ_MIN+1) /* UART0 Tx interrupt */ 121 #define S3C2410_INT_RXD0 (S3C2410_SUBIRQ_MIN+0) /* UART0 Rx interrupt */ 122 123 124 /* Clock control: CLKCON register */ 125 #define CLKCON_SPI (1<<18) 126 #define CLKCON_IIS (1<<17) 127 #define CLKCON_IIC (1<<16) 128 #define CLKCON_ADC (1<<15) 129 #define CLKCON_RTC (1<<14) 130 #define CLKCON_GPIO (1<<13) 131 #define CLKCON_UART2 (1<<12) 132 #define CLKCON_UART1 (1<<11) 133 #define CLKCON_UART0 (1<<10) /* PCLK to UART0 */ 134 #define CLKCON_SDI (1<<9) 135 #define CLKCON_TIMER (1<<8) /* PCLK to TIMER */ 136 #define CLKCON_USBD (1<<7) /* PCLK to USB device controller */ 137 #define CLKCON_USBH (1<<6) /* PCLK to USB host controller */ 138 #define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */ 139 #define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */ 140 #define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */ 141 #define CLKCON_STOP (1<<0) /* 1=transition to STOP mode */ 142 143 /* NAND Flash controller */ 144 #define NANDFC_NFCONF 0x00 /* Configuration */ 145 #define NANDFC_NFCMD 0x04 /* command */ 146 #define NANDFC_NFADDR 0x08 /* address */ 147 #define NANDFC_NFDATA 0x0c /* data */ 148 #define NANDFC_NFSTAT 0x10 /* operation status */ 149 #define NANDFC_NFECC 0x14 /* ecc */ 150 151 /* GPIO */ 152 #define GPIO_PACON 0x00 /* port A configuration */ 153 #define PCON_INPUT 0 /* Input port */ 154 #define PCON_OUTPUT 1 /* Output port */ 155 #define PCON_ALTFUN 2 /* Alternate function */ 156 #define GPIO_PADAT 0x04 /* port A data */ 157 #define GPIO_PBCON 0x10 158 #define GPIO_PBDAT 0x14 159 #define GPIO_PBUP 0x18 160 #define GPIO_PCCON 0x20 161 #define GPIO_PCDAT 0x24 162 #define GPIO_PCUP 0x28 163 #define GPIO_PDCON 0x30 164 #define GPIO_PDDAT 0x34 165 #define GPIO_PDUP 0x38 166 #define GPIO_PECON 0x40 167 #define GPIO_PEDAT 0x44 168 #define GPIO_PEUP 0x48 169 #define GPIO_PFCON 0x50 170 #define GPIO_PFDAT 0x54 171 #define GPIO_PFUP 0x58 172 #define GPIO_PGCON 0x60 173 #define GPIO_PGDAT 0x64 174 #define GPIO_PGUP 0x68 175 #define GPIO_PHCON 0x70 176 #define GPIO_PHDAT 0x74 177 #define GPIO_PHUP 0x78 178 #define GPIO_MISCCR 0x80 /* miscellaneous control */ 179 #define GPIO_DCLKCON 0x84 /* DCLK 0/1 */ 180 #define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */ 181 #define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */ 182 #define GPIO_EINTMASK 0xa4 183 #define GPIO_EINTPEND 0xa8 184 #define GPIO_GSTATUS0 0xac /* external pin status */ 185 #define GPIO_GSTATUS1 0xb0 /* external pin status */ 186 187 #define EXTINTR_LOW 0x00 188 #define EXTINTR_HIGH 0x01 189 #define EXTINTR_FALLING 0x02 190 #define EXTINTR_RISING 0x04 191 #define EXTINTR_BOTH 0x06 192 193 /* SD interface */ 194 /* XXX */ 195 196 #endif /* _ARM_S3C2XX0_S3C2410REG_H_ */ 197
Indexes created Wed Oct 01 19:09:53 GMT 2025