s3c2440_i2s.c revision 1.4.10.1
1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Fleischer <paul (at) xpg.dk> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/malloc.h> 34 #include <sys/kmem.h> 35 36 #include <sys/bus.h> 37 38 #include <arch/arm/s3c2xx0/s3c2440_dma.h> 39 #include <arch/arm/s3c2xx0/s3c2xx0var.h> 40 #include <arch/arm/s3c2xx0/s3c2440reg.h> 41 #include <arch/arm/s3c2xx0/s3c2440_i2s.h> 42 43 /*#define S3C2440_I2S_DEBUG*/ 44 45 #ifdef S3C2440_I2S_DEBUG 46 #define DPRINTF(x) do {printf x; } while (/*CONSTCOND*/0) 47 #else 48 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 49 #endif 50 51 struct s3c2440_i2s_softc { 52 device_t sc_dev; 53 kmutex_t *sc_intr_lock; 54 bus_space_tag_t sc_iot; 55 bus_space_handle_t sc_i2s_ioh; 56 57 int sc_master_clock; 58 int sc_serial_clock; 59 int sc_dir; 60 int sc_sample_width; 61 int sc_bus_format; 62 63 bus_dma_segment_t sc_dr; 64 }; 65 66 static void s3c2440_i2s_xfer_complete(dmac_xfer_t, void *); 67 68 static int s3c2440_i2s_match(device_t, cfdata_t, void *); 69 static void s3c2440_i2s_attach(device_t, device_t , void *); 70 static int s3c2440_i2s_search(device_t, cfdata_t, const int *, void *); 71 static int s3c2440_i2s_print(void *, const char *); 72 static int s3c2440_i2s_init(struct s3c2440_i2s_softc*); 73 74 CFATTACH_DECL_NEW(ssiis, sizeof(struct s3c2440_i2s_softc), s3c2440_i2s_match, 75 s3c2440_i2s_attach, NULL, NULL); 76 77 int 78 s3c2440_i2s_match(device_t parent, cfdata_t match, void *aux) 79 { 80 81 return 1; 82 } 83 84 void 85 s3c2440_i2s_attach(device_t parent, device_t self, void *aux) 86 { 87 struct s3c2440_i2s_softc *sc = device_private(self); 88 DPRINTF(("%s\n", __func__)); 89 90 sc->sc_dev = self; 91 92 s3c2440_i2s_init(sc); 93 94 printf("\n"); 95 96 config_search(self, NULL, 97 CFARG_SUBMATCH, s3c2440_i2s_search, 98 CFARG_IATTR, "ssiis", 99 CFARG_EOL); 100 } 101 102 static int 103 s3c2440_i2s_print(void *aux, const char *name) 104 { 105 return UNCONF; 106 } 107 108 static int 109 s3c2440_i2s_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 110 { 111 struct s3c2440_i2s_attach_args ia; 112 DPRINTF(("%s\n", __func__)); 113 114 ia.i2sa_handle = device_private(parent); 115 116 if (config_match(parent, cf, &ia)) 117 config_attach(parent, cf, &ia, s3c2440_i2s_print); 118 119 return 1; 120 } 121 122 void 123 s3c2440_i2s_set_intr_lock(void *handle, kmutex_t *sc_intr_lock) 124 { 125 struct s3c2440_i2s_softc *sc = handle; 126 127 sc->sc_intr_lock = sc_intr_lock; 128 } 129 130 int 131 s3c2440_i2s_init(struct s3c2440_i2s_softc *i2s_sc) 132 { 133 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 134 uint32_t reg; 135 136 i2s_sc->sc_iot = sc->sc_iot; 137 138 if (bus_space_map(sc->sc_iot, S3C2440_IIS_BASE, S3C24X0_IIS_SIZE, 0, 139 &i2s_sc->sc_i2s_ioh)) { 140 printf("Failed to map I2S registers\n"); 141 return ENOMEM; 142 } 143 144 i2s_sc->sc_master_clock = 0; 145 i2s_sc->sc_serial_clock = 48; 146 i2s_sc->sc_dir = 0; 147 i2s_sc->sc_sample_width = 0; 148 i2s_sc->sc_bus_format = 0; 149 150 reg = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON); 151 bus_space_write_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON, reg | CLKCON_IIS); 152 153 /* Setup GPIO pins to use I2S */ 154 reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON); 155 reg = GPIO_SET_FUNC(reg, 0, 2); 156 reg = GPIO_SET_FUNC(reg, 1, 2); 157 reg = GPIO_SET_FUNC(reg, 2, 2); 158 reg = GPIO_SET_FUNC(reg, 3, 2); 159 reg = GPIO_SET_FUNC(reg, 4, 2); 160 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON, reg); 161 162 /* Disable Pull-up resister for all I2S pins */ 163 reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP); 164 165 reg = GPIO_SET_DATA(reg, 0, 1); 166 reg = GPIO_SET_DATA(reg, 1, 1); 167 reg = GPIO_SET_DATA(reg, 2, 1); 168 reg = GPIO_SET_DATA(reg, 3, 1); 169 reg = GPIO_SET_DATA(reg, 4, 1); 170 171 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP, reg); 172 173 i2s_sc->sc_dr.ds_addr = S3C2440_IIS_BASE + IISFIFO; 174 i2s_sc->sc_dr.ds_len = 4; 175 176 return 0; 177 } 178 179 void 180 s3c2440_i2s_set_direction(void *handle, int direction) 181 { 182 struct s3c2440_i2s_softc *sc = handle; 183 sc->sc_dir = direction; 184 } 185 186 void 187 s3c2440_i2s_set_sample_rate(void *handle, int sample_rate) 188 { 189 struct s3c2440_i2s_softc *sc = handle; 190 int codecClock; 191 int codecClockPrescaler; 192 int pclk = s3c2xx0_softc->sc_pclk; /* Peripherical Clock in Hz*/ 193 194 DPRINTF(("%s\n", __func__)); 195 196 /* TODO: Add selection of 256fs when needed */ 197 sc->sc_master_clock = 384; 198 199 codecClock = sample_rate * sc->sc_master_clock; 200 codecClockPrescaler = pclk/codecClock; 201 202 DPRINTF(("CODEC Clock: %d Hz\n", codecClock)); 203 DPRINTF(("Prescaler: %d\n", codecClockPrescaler)); 204 DPRINTF(("Actual CODEC Clock: %d Hz\n", pclk/(codecClockPrescaler+1))); 205 DPRINTF(("Actual Sampling rate: %d Hz\n", 206 (pclk/(codecClockPrescaler+1))/sc->sc_master_clock)); 207 208 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISPSR, 209 IISPSR_PRESCALER_A(codecClockPrescaler) | 210 IISPSR_PRESCALER_B(codecClockPrescaler)); 211 } 212 213 void 214 s3c2440_i2s_set_sample_width(void *handle, int width) 215 { 216 struct s3c2440_i2s_softc *sc = handle; 217 sc->sc_sample_width = width; 218 } 219 220 void 221 s3c2440_i2s_set_bus_format(void *handle, int format) 222 { 223 struct s3c2440_i2s_softc *sc = handle; 224 225 sc->sc_bus_format = format; 226 } 227 228 int 229 s3c2440_i2s_commit(void *handle) 230 { 231 uint32_t iisfcon, iiscon, iismod; 232 struct s3c2440_i2s_softc *sc = handle; 233 234 DPRINTF(("%s\n", __func__)); 235 236 iisfcon = 0; 237 iiscon = IISCON_IFACE_EN | IISCON_PRESCALER_EN; 238 iismod = 0; 239 240 if ( (sc->sc_dir & S3C2440_I2S_TRANSMIT) ) { 241 iisfcon |= IISFCON_TX_DMA_EN | IISFCON_TX_FIFO_EN; 242 iiscon |= IISCON_TX_DMA_EN; 243 iismod |= IISMOD_MODE_TRANSMIT; 244 } 245 246 if ( (sc->sc_dir & S3C2440_I2S_RECEIVE) ) { 247 iisfcon |= IISFCON_RX_DMA_EN | IISFCON_RX_FIFO_EN; 248 iiscon |= IISCON_RX_DMA_EN; 249 iismod |= IISMOD_MODE_RECEIVE; 250 } 251 252 if (iisfcon == 0) { 253 return EINVAL; 254 } 255 256 257 if (sc->sc_bus_format == S3C2440_I2S_BUS_MSB) 258 iismod |= IISMOD_IFACE_MSB; 259 260 switch (sc->sc_master_clock) { 261 case 256: 262 iismod |= IISMOD_MASTER_FREQ256; 263 break; 264 case 384: 265 iismod |= IISMOD_MASTER_FREQ384; 266 break; 267 default: 268 return EINVAL; 269 270 } 271 272 switch (sc->sc_serial_clock) { 273 case 16: 274 iismod |= IISMOD_SERIAL_FREQ16; 275 break; 276 case 32: 277 iismod |= IISMOD_SERIAL_FREQ32; 278 break; 279 case 48: 280 iismod |= IISMOD_SERIAL_FREQ48; 281 break; 282 default: 283 return EINVAL; 284 } 285 286 if (sc->sc_sample_width == 16) 287 iismod |= IISMOD_16BIT; 288 289 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISFCON, iisfcon); 290 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISMOD, iismod); 291 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISCON, iiscon); 292 293 return 0; 294 } 295 296 int 297 s3c2440_i2s_disable(void *handle) 298 { 299 return 0; 300 } 301 302 int 303 s3c2440_i2s_get_master_clock(void *handle) 304 { 305 struct s3c2440_i2s_softc *sc = handle; 306 return sc->sc_master_clock; 307 } 308 309 int 310 s3c2440_i2s_get_serial_clock(void *handle) 311 { 312 struct s3c2440_i2s_softc *sc = handle; 313 314 return sc->sc_serial_clock; 315 } 316 317 int 318 s3c2440_i2s_alloc(void *handle, 319 int direction, size_t size, int flags, 320 s3c2440_i2s_buf_t *out) 321 { 322 int retval = 0; 323 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 324 s3c2440_i2s_buf_t buf; 325 326 DPRINTF(("%s\n", __func__)); 327 328 *out = kmem_alloc(sizeof(struct s3c2440_i2s_buf), KM_SLEEP); 329 buf = *out; 330 buf->i2b_parent = handle; 331 buf->i2b_size = size; 332 buf->i2b_nsegs = S3C2440_I2S_BUF_MAX_SEGS; 333 buf->i2b_xfer = NULL; 334 buf->i2b_cb = NULL; 335 buf->i2b_cb_cookie = NULL; 336 337 /* We first allocate some DMA-friendly memory for the buffer... */ 338 retval = bus_dmamem_alloc(sc->sc_dmat, buf->i2b_size, NBPG, 0, 339 buf->i2b_segs, buf->i2b_nsegs, &buf->i2b_nsegs, 340 BUS_DMA_WAITOK); 341 if (retval != 0) { 342 printf("%s: Failed to allocate DMA memory\n", __func__); 343 goto cleanup_dealloc; 344 } 345 346 DPRINTF(("%s: Using %d DMA segments\n", __func__, buf->i2b_nsegs)); 347 348 retval = bus_dmamem_map(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs, 349 buf->i2b_size, &buf->i2b_addr, BUS_DMA_WAITOK); 350 351 if (retval != 0) { 352 printf("%s: Failed to map DMA memory\n", __func__); 353 goto cleanup_dealloc_dma; 354 } 355 356 DPRINTF(("%s: Playback DMA buffer mapped at %p\n", __func__, 357 buf->i2b_addr)); 358 359 /* XXX: Not sure if nsegments is really 1...*/ 360 retval = bus_dmamap_create(sc->sc_dmat, buf->i2b_size, 1, 361 buf->i2b_size, 0, BUS_DMA_WAITOK, 362 &buf->i2b_dmamap); 363 if (retval != 0) { 364 printf("%s: Failed to create DMA map\n", __func__); 365 goto cleanup_unmap_dma; 366 } 367 368 DPRINTF(("%s: DMA map created successfully\n", __func__)); 369 370 buf->i2b_xfer = s3c2440_dmac_allocate_xfer(); 371 372 return 0; 373 cleanup_unmap_dma: 374 bus_dmamem_unmap(sc->sc_dmat, &buf->i2b_addr, buf->i2b_size); 375 cleanup_dealloc_dma: 376 bus_dmamem_free(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs); 377 cleanup_dealloc: 378 kmem_free(*out, sizeof(struct s3c2440_i2s_buf)); 379 return retval; 380 } 381 382 void 383 s3c2440_i2s_free(s3c2440_i2s_buf_t buf) 384 { 385 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 386 387 if (buf->i2b_xfer != NULL) { 388 s3c2440_dmac_free_xfer(buf->i2b_xfer); 389 } 390 391 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 392 bus_dmamap_destroy(sc->sc_dmat, buf->i2b_dmamap); 393 bus_dmamem_unmap(sc->sc_dmat, &buf->i2b_addr, buf->i2b_size); 394 bus_dmamem_free(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs); 395 kmem_free(buf, sizeof(struct s3c2440_i2s_buf)); 396 } 397 398 int 399 s3c2440_i2s_output(s3c2440_i2s_buf_t buf, void *block, int bsize, 400 void (*callback)(void*), void *cb_cookie) 401 { 402 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 403 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 404 int retval; 405 dmac_xfer_t xfer = buf->i2b_xfer; 406 407 retval = bus_dmamap_load(sc->sc_dmat, buf->i2b_dmamap, block, 408 bsize, NULL, BUS_DMA_NOWAIT); 409 if (retval != 0) { 410 printf("Failed to load DMA map\n"); 411 return retval; 412 } 413 414 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 415 xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE; 416 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 417 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &i2s->sc_dr; 418 419 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 420 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE; 421 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = buf->i2b_dmamap->dm_nsegs; 422 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = buf->i2b_dmamap->dm_segs; 423 424 xfer->dx_peripheral = DMAC_PERIPH_I2SSDO; 425 426 if (i2s->sc_sample_width == 16) 427 xfer->dx_xfer_width = DMAC_XFER_WIDTH_16BIT; 428 else if (i2s->sc_sample_width == 8) 429 xfer->dx_xfer_width = DMAC_XFER_WIDTH_8BIT; 430 431 xfer->dx_done = s3c2440_i2s_xfer_complete; 432 xfer->dx_cookie = buf; 433 xfer->dx_xfer_mode = DMAC_XFER_MODE_HANDSHAKE; 434 435 buf->i2b_cb = callback; 436 buf->i2b_cb_cookie = cb_cookie; 437 438 s3c2440_dmac_start_xfer(buf->i2b_xfer); 439 440 return 0; 441 } 442 443 int 444 s3c2440_i2s_halt_output(s3c2440_i2s_buf_t buf) 445 { 446 /*int retval;*/ 447 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 448 449 DPRINTF(("Aborting DMA transfer\n")); 450 /*do { 451 retval =*/ s3c2440_dmac_abort_xfer(buf->i2b_xfer); 452 /*} while(retval != 0);*/ 453 DPRINTF(("Aborting DMA transfer: SUCCESS\n")); 454 455 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 456 457 return 0; 458 } 459 460 int 461 s3c2440_i2s_input(s3c2440_i2s_buf_t buf, void *block, int bsize, 462 void (*callback)(void*), void *cb_cookie) 463 { 464 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 465 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 466 int retval; 467 dmac_xfer_t xfer = buf->i2b_xfer; 468 469 retval = bus_dmamap_load(sc->sc_dmat, buf->i2b_dmamap, block, 470 bsize, NULL, BUS_DMA_NOWAIT); 471 if (retval != 0) { 472 printf("Failed to load DMA map\n"); 473 return retval; 474 } 475 476 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 477 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE; 478 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 479 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &i2s->sc_dr; 480 481 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 482 xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE; 483 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = buf->i2b_dmamap->dm_nsegs; 484 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = buf->i2b_dmamap->dm_segs; 485 486 xfer->dx_peripheral = DMAC_PERIPH_I2SSDI; 487 488 if (i2s->sc_sample_width == 16) 489 xfer->dx_xfer_width = DMAC_XFER_WIDTH_16BIT; 490 else if (i2s->sc_sample_width == 8) 491 xfer->dx_xfer_width = DMAC_XFER_WIDTH_8BIT; 492 493 xfer->dx_done = s3c2440_i2s_xfer_complete; 494 xfer->dx_cookie = buf; 495 xfer->dx_xfer_mode = DMAC_XFER_MODE_HANDSHAKE; 496 497 buf->i2b_cb = callback; 498 buf->i2b_cb_cookie = cb_cookie; 499 500 s3c2440_dmac_start_xfer(buf->i2b_xfer); 501 502 return 0; 503 } 504 505 static void 506 s3c2440_i2s_xfer_complete(dmac_xfer_t xfer, void *cookie) 507 { 508 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 509 s3c2440_i2s_buf_t buf = cookie; 510 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 511 512 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 513 514 mutex_spin_enter(i2s->sc_intr_lock); 515 (buf->i2b_cb)(buf->i2b_cb_cookie); 516 mutex_spin_exit(i2s->sc_intr_lock); 517 } 518
Indexes created Tue Oct 21 07:10:13 GMT 2025