s3c2440_i2s.c revision 1.5
1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Fleischer <paul (at) xpg.dk> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/malloc.h> 34 #include <sys/kmem.h> 35 36 #include <sys/bus.h> 37 38 #include <arch/arm/s3c2xx0/s3c2440_dma.h> 39 #include <arch/arm/s3c2xx0/s3c2xx0var.h> 40 #include <arch/arm/s3c2xx0/s3c2440reg.h> 41 #include <arch/arm/s3c2xx0/s3c2440_i2s.h> 42 43 /*#define S3C2440_I2S_DEBUG*/ 44 45 #ifdef S3C2440_I2S_DEBUG 46 #define DPRINTF(x) do {printf x; } while (/*CONSTCOND*/0) 47 #else 48 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 49 #endif 50 51 struct s3c2440_i2s_softc { 52 device_t sc_dev; 53 kmutex_t *sc_intr_lock; 54 bus_space_tag_t sc_iot; 55 bus_space_handle_t sc_i2s_ioh; 56 57 int sc_master_clock; 58 int sc_serial_clock; 59 int sc_dir; 60 int sc_sample_width; 61 int sc_bus_format; 62 63 bus_dma_segment_t sc_dr; 64 }; 65 66 static void s3c2440_i2s_xfer_complete(dmac_xfer_t, void *); 67 68 static int s3c2440_i2s_match(device_t, cfdata_t, void *); 69 static void s3c2440_i2s_attach(device_t, device_t , void *); 70 static int s3c2440_i2s_search(device_t, cfdata_t, const int *, void *); 71 static int s3c2440_i2s_print(void *, const char *); 72 static int s3c2440_i2s_init(struct s3c2440_i2s_softc*); 73 74 CFATTACH_DECL_NEW(ssiis, sizeof(struct s3c2440_i2s_softc), s3c2440_i2s_match, 75 s3c2440_i2s_attach, NULL, NULL); 76 77 int 78 s3c2440_i2s_match(device_t parent, cfdata_t match, void *aux) 79 { 80 81 return 1; 82 } 83 84 void 85 s3c2440_i2s_attach(device_t parent, device_t self, void *aux) 86 { 87 struct s3c2440_i2s_softc *sc = device_private(self); 88 DPRINTF(("%s\n", __func__)); 89 90 sc->sc_dev = self; 91 92 s3c2440_i2s_init(sc); 93 94 printf("\n"); 95 96 config_search(self, NULL, 97 CFARG_SEARCH, s3c2440_i2s_search, 98 CFARG_EOL); 99 } 100 101 static int 102 s3c2440_i2s_print(void *aux, const char *name) 103 { 104 return UNCONF; 105 } 106 107 static int 108 s3c2440_i2s_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 109 { 110 struct s3c2440_i2s_attach_args ia; 111 DPRINTF(("%s\n", __func__)); 112 113 ia.i2sa_handle = device_private(parent); 114 115 if (config_probe(parent, cf, &ia)) 116 config_attach(parent, cf, &ia, s3c2440_i2s_print, CFARG_EOL); 117 118 return 1; 119 } 120 121 void 122 s3c2440_i2s_set_intr_lock(void *handle, kmutex_t *sc_intr_lock) 123 { 124 struct s3c2440_i2s_softc *sc = handle; 125 126 sc->sc_intr_lock = sc_intr_lock; 127 } 128 129 int 130 s3c2440_i2s_init(struct s3c2440_i2s_softc *i2s_sc) 131 { 132 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 133 uint32_t reg; 134 135 i2s_sc->sc_iot = sc->sc_iot; 136 137 if (bus_space_map(sc->sc_iot, S3C2440_IIS_BASE, S3C24X0_IIS_SIZE, 0, 138 &i2s_sc->sc_i2s_ioh)) { 139 printf("Failed to map I2S registers\n"); 140 return ENOMEM; 141 } 142 143 i2s_sc->sc_master_clock = 0; 144 i2s_sc->sc_serial_clock = 48; 145 i2s_sc->sc_dir = 0; 146 i2s_sc->sc_sample_width = 0; 147 i2s_sc->sc_bus_format = 0; 148 149 reg = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON); 150 bus_space_write_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON, reg | CLKCON_IIS); 151 152 /* Setup GPIO pins to use I2S */ 153 reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON); 154 reg = GPIO_SET_FUNC(reg, 0, 2); 155 reg = GPIO_SET_FUNC(reg, 1, 2); 156 reg = GPIO_SET_FUNC(reg, 2, 2); 157 reg = GPIO_SET_FUNC(reg, 3, 2); 158 reg = GPIO_SET_FUNC(reg, 4, 2); 159 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON, reg); 160 161 /* Disable Pull-up resister for all I2S pins */ 162 reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP); 163 164 reg = GPIO_SET_DATA(reg, 0, 1); 165 reg = GPIO_SET_DATA(reg, 1, 1); 166 reg = GPIO_SET_DATA(reg, 2, 1); 167 reg = GPIO_SET_DATA(reg, 3, 1); 168 reg = GPIO_SET_DATA(reg, 4, 1); 169 170 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP, reg); 171 172 i2s_sc->sc_dr.ds_addr = S3C2440_IIS_BASE + IISFIFO; 173 i2s_sc->sc_dr.ds_len = 4; 174 175 return 0; 176 } 177 178 void 179 s3c2440_i2s_set_direction(void *handle, int direction) 180 { 181 struct s3c2440_i2s_softc *sc = handle; 182 sc->sc_dir = direction; 183 } 184 185 void 186 s3c2440_i2s_set_sample_rate(void *handle, int sample_rate) 187 { 188 struct s3c2440_i2s_softc *sc = handle; 189 int codecClock; 190 int codecClockPrescaler; 191 int pclk = s3c2xx0_softc->sc_pclk; /* Peripherical Clock in Hz*/ 192 193 DPRINTF(("%s\n", __func__)); 194 195 /* TODO: Add selection of 256fs when needed */ 196 sc->sc_master_clock = 384; 197 198 codecClock = sample_rate * sc->sc_master_clock; 199 codecClockPrescaler = pclk/codecClock; 200 201 DPRINTF(("CODEC Clock: %d Hz\n", codecClock)); 202 DPRINTF(("Prescaler: %d\n", codecClockPrescaler)); 203 DPRINTF(("Actual CODEC Clock: %d Hz\n", pclk/(codecClockPrescaler+1))); 204 DPRINTF(("Actual Sampling rate: %d Hz\n", 205 (pclk/(codecClockPrescaler+1))/sc->sc_master_clock)); 206 207 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISPSR, 208 IISPSR_PRESCALER_A(codecClockPrescaler) | 209 IISPSR_PRESCALER_B(codecClockPrescaler)); 210 } 211 212 void 213 s3c2440_i2s_set_sample_width(void *handle, int width) 214 { 215 struct s3c2440_i2s_softc *sc = handle; 216 sc->sc_sample_width = width; 217 } 218 219 void 220 s3c2440_i2s_set_bus_format(void *handle, int format) 221 { 222 struct s3c2440_i2s_softc *sc = handle; 223 224 sc->sc_bus_format = format; 225 } 226 227 int 228 s3c2440_i2s_commit(void *handle) 229 { 230 uint32_t iisfcon, iiscon, iismod; 231 struct s3c2440_i2s_softc *sc = handle; 232 233 DPRINTF(("%s\n", __func__)); 234 235 iisfcon = 0; 236 iiscon = IISCON_IFACE_EN | IISCON_PRESCALER_EN; 237 iismod = 0; 238 239 if ( (sc->sc_dir & S3C2440_I2S_TRANSMIT) ) { 240 iisfcon |= IISFCON_TX_DMA_EN | IISFCON_TX_FIFO_EN; 241 iiscon |= IISCON_TX_DMA_EN; 242 iismod |= IISMOD_MODE_TRANSMIT; 243 } 244 245 if ( (sc->sc_dir & S3C2440_I2S_RECEIVE) ) { 246 iisfcon |= IISFCON_RX_DMA_EN | IISFCON_RX_FIFO_EN; 247 iiscon |= IISCON_RX_DMA_EN; 248 iismod |= IISMOD_MODE_RECEIVE; 249 } 250 251 if (iisfcon == 0) { 252 return EINVAL; 253 } 254 255 256 if (sc->sc_bus_format == S3C2440_I2S_BUS_MSB) 257 iismod |= IISMOD_IFACE_MSB; 258 259 switch (sc->sc_master_clock) { 260 case 256: 261 iismod |= IISMOD_MASTER_FREQ256; 262 break; 263 case 384: 264 iismod |= IISMOD_MASTER_FREQ384; 265 break; 266 default: 267 return EINVAL; 268 269 } 270 271 switch (sc->sc_serial_clock) { 272 case 16: 273 iismod |= IISMOD_SERIAL_FREQ16; 274 break; 275 case 32: 276 iismod |= IISMOD_SERIAL_FREQ32; 277 break; 278 case 48: 279 iismod |= IISMOD_SERIAL_FREQ48; 280 break; 281 default: 282 return EINVAL; 283 } 284 285 if (sc->sc_sample_width == 16) 286 iismod |= IISMOD_16BIT; 287 288 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISFCON, iisfcon); 289 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISMOD, iismod); 290 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISCON, iiscon); 291 292 return 0; 293 } 294 295 int 296 s3c2440_i2s_disable(void *handle) 297 { 298 return 0; 299 } 300 301 int 302 s3c2440_i2s_get_master_clock(void *handle) 303 { 304 struct s3c2440_i2s_softc *sc = handle; 305 return sc->sc_master_clock; 306 } 307 308 int 309 s3c2440_i2s_get_serial_clock(void *handle) 310 { 311 struct s3c2440_i2s_softc *sc = handle; 312 313 return sc->sc_serial_clock; 314 } 315 316 int 317 s3c2440_i2s_alloc(void *handle, 318 int direction, size_t size, int flags, 319 s3c2440_i2s_buf_t *out) 320 { 321 int retval = 0; 322 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 323 s3c2440_i2s_buf_t buf; 324 325 DPRINTF(("%s\n", __func__)); 326 327 *out = kmem_alloc(sizeof(struct s3c2440_i2s_buf), KM_SLEEP); 328 buf = *out; 329 buf->i2b_parent = handle; 330 buf->i2b_size = size; 331 buf->i2b_nsegs = S3C2440_I2S_BUF_MAX_SEGS; 332 buf->i2b_xfer = NULL; 333 buf->i2b_cb = NULL; 334 buf->i2b_cb_cookie = NULL; 335 336 /* We first allocate some DMA-friendly memory for the buffer... */ 337 retval = bus_dmamem_alloc(sc->sc_dmat, buf->i2b_size, NBPG, 0, 338 buf->i2b_segs, buf->i2b_nsegs, &buf->i2b_nsegs, 339 BUS_DMA_WAITOK); 340 if (retval != 0) { 341 printf("%s: Failed to allocate DMA memory\n", __func__); 342 goto cleanup_dealloc; 343 } 344 345 DPRINTF(("%s: Using %d DMA segments\n", __func__, buf->i2b_nsegs)); 346 347 retval = bus_dmamem_map(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs, 348 buf->i2b_size, &buf->i2b_addr, BUS_DMA_WAITOK); 349 350 if (retval != 0) { 351 printf("%s: Failed to map DMA memory\n", __func__); 352 goto cleanup_dealloc_dma; 353 } 354 355 DPRINTF(("%s: Playback DMA buffer mapped at %p\n", __func__, 356 buf->i2b_addr)); 357 358 /* XXX: Not sure if nsegments is really 1...*/ 359 retval = bus_dmamap_create(sc->sc_dmat, buf->i2b_size, 1, 360 buf->i2b_size, 0, BUS_DMA_WAITOK, 361 &buf->i2b_dmamap); 362 if (retval != 0) { 363 printf("%s: Failed to create DMA map\n", __func__); 364 goto cleanup_unmap_dma; 365 } 366 367 DPRINTF(("%s: DMA map created successfully\n", __func__)); 368 369 buf->i2b_xfer = s3c2440_dmac_allocate_xfer(); 370 371 return 0; 372 cleanup_unmap_dma: 373 bus_dmamem_unmap(sc->sc_dmat, &buf->i2b_addr, buf->i2b_size); 374 cleanup_dealloc_dma: 375 bus_dmamem_free(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs); 376 cleanup_dealloc: 377 kmem_free(*out, sizeof(struct s3c2440_i2s_buf)); 378 return retval; 379 } 380 381 void 382 s3c2440_i2s_free(s3c2440_i2s_buf_t buf) 383 { 384 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 385 386 if (buf->i2b_xfer != NULL) { 387 s3c2440_dmac_free_xfer(buf->i2b_xfer); 388 } 389 390 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 391 bus_dmamap_destroy(sc->sc_dmat, buf->i2b_dmamap); 392 bus_dmamem_unmap(sc->sc_dmat, &buf->i2b_addr, buf->i2b_size); 393 bus_dmamem_free(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs); 394 kmem_free(buf, sizeof(struct s3c2440_i2s_buf)); 395 } 396 397 int 398 s3c2440_i2s_output(s3c2440_i2s_buf_t buf, void *block, int bsize, 399 void (*callback)(void*), void *cb_cookie) 400 { 401 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 402 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 403 int retval; 404 dmac_xfer_t xfer = buf->i2b_xfer; 405 406 retval = bus_dmamap_load(sc->sc_dmat, buf->i2b_dmamap, block, 407 bsize, NULL, BUS_DMA_NOWAIT); 408 if (retval != 0) { 409 printf("Failed to load DMA map\n"); 410 return retval; 411 } 412 413 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 414 xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE; 415 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 416 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &i2s->sc_dr; 417 418 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 419 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE; 420 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = buf->i2b_dmamap->dm_nsegs; 421 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = buf->i2b_dmamap->dm_segs; 422 423 xfer->dx_peripheral = DMAC_PERIPH_I2SSDO; 424 425 if (i2s->sc_sample_width == 16) 426 xfer->dx_xfer_width = DMAC_XFER_WIDTH_16BIT; 427 else if (i2s->sc_sample_width == 8) 428 xfer->dx_xfer_width = DMAC_XFER_WIDTH_8BIT; 429 430 xfer->dx_done = s3c2440_i2s_xfer_complete; 431 xfer->dx_cookie = buf; 432 xfer->dx_xfer_mode = DMAC_XFER_MODE_HANDSHAKE; 433 434 buf->i2b_cb = callback; 435 buf->i2b_cb_cookie = cb_cookie; 436 437 s3c2440_dmac_start_xfer(buf->i2b_xfer); 438 439 return 0; 440 } 441 442 int 443 s3c2440_i2s_halt_output(s3c2440_i2s_buf_t buf) 444 { 445 /*int retval;*/ 446 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 447 448 DPRINTF(("Aborting DMA transfer\n")); 449 /*do { 450 retval =*/ s3c2440_dmac_abort_xfer(buf->i2b_xfer); 451 /*} while(retval != 0);*/ 452 DPRINTF(("Aborting DMA transfer: SUCCESS\n")); 453 454 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 455 456 return 0; 457 } 458 459 int 460 s3c2440_i2s_input(s3c2440_i2s_buf_t buf, void *block, int bsize, 461 void (*callback)(void*), void *cb_cookie) 462 { 463 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 464 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 465 int retval; 466 dmac_xfer_t xfer = buf->i2b_xfer; 467 468 retval = bus_dmamap_load(sc->sc_dmat, buf->i2b_dmamap, block, 469 bsize, NULL, BUS_DMA_NOWAIT); 470 if (retval != 0) { 471 printf("Failed to load DMA map\n"); 472 return retval; 473 } 474 475 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 476 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE; 477 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 478 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &i2s->sc_dr; 479 480 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 481 xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE; 482 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = buf->i2b_dmamap->dm_nsegs; 483 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = buf->i2b_dmamap->dm_segs; 484 485 xfer->dx_peripheral = DMAC_PERIPH_I2SSDI; 486 487 if (i2s->sc_sample_width == 16) 488 xfer->dx_xfer_width = DMAC_XFER_WIDTH_16BIT; 489 else if (i2s->sc_sample_width == 8) 490 xfer->dx_xfer_width = DMAC_XFER_WIDTH_8BIT; 491 492 xfer->dx_done = s3c2440_i2s_xfer_complete; 493 xfer->dx_cookie = buf; 494 xfer->dx_xfer_mode = DMAC_XFER_MODE_HANDSHAKE; 495 496 buf->i2b_cb = callback; 497 buf->i2b_cb_cookie = cb_cookie; 498 499 s3c2440_dmac_start_xfer(buf->i2b_xfer); 500 501 return 0; 502 } 503 504 static void 505 s3c2440_i2s_xfer_complete(dmac_xfer_t xfer, void *cookie) 506 { 507 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 508 s3c2440_i2s_buf_t buf = cookie; 509 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 510 511 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 512 513 mutex_spin_enter(i2s->sc_intr_lock); 514 (buf->i2b_cb)(buf->i2b_cb_cookie); 515 mutex_spin_exit(i2s->sc_intr_lock); 516 } 517
Indexes created Mon Sep 29 18:09:42 GMT 2025