s3c2440_i2s.c revision 1.6
1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Fleischer <paul (at) xpg.dk> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/malloc.h> 34 #include <sys/kmem.h> 35 36 #include <sys/bus.h> 37 38 #include <arch/arm/s3c2xx0/s3c2440_dma.h> 39 #include <arch/arm/s3c2xx0/s3c2xx0var.h> 40 #include <arch/arm/s3c2xx0/s3c2440reg.h> 41 #include <arch/arm/s3c2xx0/s3c2440_i2s.h> 42 43 /*#define S3C2440_I2S_DEBUG*/ 44 45 #ifdef S3C2440_I2S_DEBUG 46 #define DPRINTF(x) do {printf x; } while (/*CONSTCOND*/0) 47 #else 48 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 49 #endif 50 51 struct s3c2440_i2s_softc { 52 device_t sc_dev; 53 kmutex_t *sc_intr_lock; 54 bus_space_tag_t sc_iot; 55 bus_space_handle_t sc_i2s_ioh; 56 57 int sc_master_clock; 58 int sc_serial_clock; 59 int sc_dir; 60 int sc_sample_width; 61 int sc_bus_format; 62 63 bus_dma_segment_t sc_dr; 64 }; 65 66 static void s3c2440_i2s_xfer_complete(dmac_xfer_t, void *); 67 68 static int s3c2440_i2s_match(device_t, cfdata_t, void *); 69 static void s3c2440_i2s_attach(device_t, device_t , void *); 70 static int s3c2440_i2s_search(device_t, cfdata_t, const int *, void *); 71 static int s3c2440_i2s_print(void *, const char *); 72 static int s3c2440_i2s_init(struct s3c2440_i2s_softc*); 73 74 CFATTACH_DECL_NEW(ssiis, sizeof(struct s3c2440_i2s_softc), s3c2440_i2s_match, 75 s3c2440_i2s_attach, NULL, NULL); 76 77 int 78 s3c2440_i2s_match(device_t parent, cfdata_t match, void *aux) 79 { 80 81 return 1; 82 } 83 84 void 85 s3c2440_i2s_attach(device_t parent, device_t self, void *aux) 86 { 87 struct s3c2440_i2s_softc *sc = device_private(self); 88 DPRINTF(("%s\n", __func__)); 89 90 sc->sc_dev = self; 91 92 s3c2440_i2s_init(sc); 93 94 printf("\n"); 95 96 config_search(self, NULL, 97 CFARGS(.search = s3c2440_i2s_search)); 98 } 99 100 static int 101 s3c2440_i2s_print(void *aux, const char *name) 102 { 103 return UNCONF; 104 } 105 106 static int 107 s3c2440_i2s_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 108 { 109 struct s3c2440_i2s_attach_args ia; 110 DPRINTF(("%s\n", __func__)); 111 112 ia.i2sa_handle = device_private(parent); 113 114 if (config_probe(parent, cf, &ia)) 115 config_attach(parent, cf, &ia, s3c2440_i2s_print, CFARGS_NONE); 116 117 return 1; 118 } 119 120 void 121 s3c2440_i2s_set_intr_lock(void *handle, kmutex_t *sc_intr_lock) 122 { 123 struct s3c2440_i2s_softc *sc = handle; 124 125 sc->sc_intr_lock = sc_intr_lock; 126 } 127 128 int 129 s3c2440_i2s_init(struct s3c2440_i2s_softc *i2s_sc) 130 { 131 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 132 uint32_t reg; 133 134 i2s_sc->sc_iot = sc->sc_iot; 135 136 if (bus_space_map(sc->sc_iot, S3C2440_IIS_BASE, S3C24X0_IIS_SIZE, 0, 137 &i2s_sc->sc_i2s_ioh)) { 138 printf("Failed to map I2S registers\n"); 139 return ENOMEM; 140 } 141 142 i2s_sc->sc_master_clock = 0; 143 i2s_sc->sc_serial_clock = 48; 144 i2s_sc->sc_dir = 0; 145 i2s_sc->sc_sample_width = 0; 146 i2s_sc->sc_bus_format = 0; 147 148 reg = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON); 149 bus_space_write_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON, reg | CLKCON_IIS); 150 151 /* Setup GPIO pins to use I2S */ 152 reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON); 153 reg = GPIO_SET_FUNC(reg, 0, 2); 154 reg = GPIO_SET_FUNC(reg, 1, 2); 155 reg = GPIO_SET_FUNC(reg, 2, 2); 156 reg = GPIO_SET_FUNC(reg, 3, 2); 157 reg = GPIO_SET_FUNC(reg, 4, 2); 158 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON, reg); 159 160 /* Disable Pull-up resister for all I2S pins */ 161 reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP); 162 163 reg = GPIO_SET_DATA(reg, 0, 1); 164 reg = GPIO_SET_DATA(reg, 1, 1); 165 reg = GPIO_SET_DATA(reg, 2, 1); 166 reg = GPIO_SET_DATA(reg, 3, 1); 167 reg = GPIO_SET_DATA(reg, 4, 1); 168 169 bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP, reg); 170 171 i2s_sc->sc_dr.ds_addr = S3C2440_IIS_BASE + IISFIFO; 172 i2s_sc->sc_dr.ds_len = 4; 173 174 return 0; 175 } 176 177 void 178 s3c2440_i2s_set_direction(void *handle, int direction) 179 { 180 struct s3c2440_i2s_softc *sc = handle; 181 sc->sc_dir = direction; 182 } 183 184 void 185 s3c2440_i2s_set_sample_rate(void *handle, int sample_rate) 186 { 187 struct s3c2440_i2s_softc *sc = handle; 188 int codecClock; 189 int codecClockPrescaler; 190 int pclk = s3c2xx0_softc->sc_pclk; /* Peripherical Clock in Hz*/ 191 192 DPRINTF(("%s\n", __func__)); 193 194 /* TODO: Add selection of 256fs when needed */ 195 sc->sc_master_clock = 384; 196 197 codecClock = sample_rate * sc->sc_master_clock; 198 codecClockPrescaler = pclk/codecClock; 199 200 DPRINTF(("CODEC Clock: %d Hz\n", codecClock)); 201 DPRINTF(("Prescaler: %d\n", codecClockPrescaler)); 202 DPRINTF(("Actual CODEC Clock: %d Hz\n", pclk/(codecClockPrescaler+1))); 203 DPRINTF(("Actual Sampling rate: %d Hz\n", 204 (pclk/(codecClockPrescaler+1))/sc->sc_master_clock)); 205 206 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISPSR, 207 IISPSR_PRESCALER_A(codecClockPrescaler) | 208 IISPSR_PRESCALER_B(codecClockPrescaler)); 209 } 210 211 void 212 s3c2440_i2s_set_sample_width(void *handle, int width) 213 { 214 struct s3c2440_i2s_softc *sc = handle; 215 sc->sc_sample_width = width; 216 } 217 218 void 219 s3c2440_i2s_set_bus_format(void *handle, int format) 220 { 221 struct s3c2440_i2s_softc *sc = handle; 222 223 sc->sc_bus_format = format; 224 } 225 226 int 227 s3c2440_i2s_commit(void *handle) 228 { 229 uint32_t iisfcon, iiscon, iismod; 230 struct s3c2440_i2s_softc *sc = handle; 231 232 DPRINTF(("%s\n", __func__)); 233 234 iisfcon = 0; 235 iiscon = IISCON_IFACE_EN | IISCON_PRESCALER_EN; 236 iismod = 0; 237 238 if ( (sc->sc_dir & S3C2440_I2S_TRANSMIT) ) { 239 iisfcon |= IISFCON_TX_DMA_EN | IISFCON_TX_FIFO_EN; 240 iiscon |= IISCON_TX_DMA_EN; 241 iismod |= IISMOD_MODE_TRANSMIT; 242 } 243 244 if ( (sc->sc_dir & S3C2440_I2S_RECEIVE) ) { 245 iisfcon |= IISFCON_RX_DMA_EN | IISFCON_RX_FIFO_EN; 246 iiscon |= IISCON_RX_DMA_EN; 247 iismod |= IISMOD_MODE_RECEIVE; 248 } 249 250 if (iisfcon == 0) { 251 return EINVAL; 252 } 253 254 255 if (sc->sc_bus_format == S3C2440_I2S_BUS_MSB) 256 iismod |= IISMOD_IFACE_MSB; 257 258 switch (sc->sc_master_clock) { 259 case 256: 260 iismod |= IISMOD_MASTER_FREQ256; 261 break; 262 case 384: 263 iismod |= IISMOD_MASTER_FREQ384; 264 break; 265 default: 266 return EINVAL; 267 268 } 269 270 switch (sc->sc_serial_clock) { 271 case 16: 272 iismod |= IISMOD_SERIAL_FREQ16; 273 break; 274 case 32: 275 iismod |= IISMOD_SERIAL_FREQ32; 276 break; 277 case 48: 278 iismod |= IISMOD_SERIAL_FREQ48; 279 break; 280 default: 281 return EINVAL; 282 } 283 284 if (sc->sc_sample_width == 16) 285 iismod |= IISMOD_16BIT; 286 287 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISFCON, iisfcon); 288 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISMOD, iismod); 289 bus_space_write_4(sc->sc_iot, sc->sc_i2s_ioh, IISCON, iiscon); 290 291 return 0; 292 } 293 294 int 295 s3c2440_i2s_disable(void *handle) 296 { 297 return 0; 298 } 299 300 int 301 s3c2440_i2s_get_master_clock(void *handle) 302 { 303 struct s3c2440_i2s_softc *sc = handle; 304 return sc->sc_master_clock; 305 } 306 307 int 308 s3c2440_i2s_get_serial_clock(void *handle) 309 { 310 struct s3c2440_i2s_softc *sc = handle; 311 312 return sc->sc_serial_clock; 313 } 314 315 int 316 s3c2440_i2s_alloc(void *handle, 317 int direction, size_t size, int flags, 318 s3c2440_i2s_buf_t *out) 319 { 320 int retval = 0; 321 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 322 s3c2440_i2s_buf_t buf; 323 324 DPRINTF(("%s\n", __func__)); 325 326 *out = kmem_alloc(sizeof(struct s3c2440_i2s_buf), KM_SLEEP); 327 buf = *out; 328 buf->i2b_parent = handle; 329 buf->i2b_size = size; 330 buf->i2b_nsegs = S3C2440_I2S_BUF_MAX_SEGS; 331 buf->i2b_xfer = NULL; 332 buf->i2b_cb = NULL; 333 buf->i2b_cb_cookie = NULL; 334 335 /* We first allocate some DMA-friendly memory for the buffer... */ 336 retval = bus_dmamem_alloc(sc->sc_dmat, buf->i2b_size, NBPG, 0, 337 buf->i2b_segs, buf->i2b_nsegs, &buf->i2b_nsegs, 338 BUS_DMA_WAITOK); 339 if (retval != 0) { 340 printf("%s: Failed to allocate DMA memory\n", __func__); 341 goto cleanup_dealloc; 342 } 343 344 DPRINTF(("%s: Using %d DMA segments\n", __func__, buf->i2b_nsegs)); 345 346 retval = bus_dmamem_map(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs, 347 buf->i2b_size, &buf->i2b_addr, BUS_DMA_WAITOK); 348 349 if (retval != 0) { 350 printf("%s: Failed to map DMA memory\n", __func__); 351 goto cleanup_dealloc_dma; 352 } 353 354 DPRINTF(("%s: Playback DMA buffer mapped at %p\n", __func__, 355 buf->i2b_addr)); 356 357 /* XXX: Not sure if nsegments is really 1...*/ 358 retval = bus_dmamap_create(sc->sc_dmat, buf->i2b_size, 1, 359 buf->i2b_size, 0, BUS_DMA_WAITOK, 360 &buf->i2b_dmamap); 361 if (retval != 0) { 362 printf("%s: Failed to create DMA map\n", __func__); 363 goto cleanup_unmap_dma; 364 } 365 366 DPRINTF(("%s: DMA map created successfully\n", __func__)); 367 368 buf->i2b_xfer = s3c2440_dmac_allocate_xfer(); 369 370 return 0; 371 cleanup_unmap_dma: 372 bus_dmamem_unmap(sc->sc_dmat, &buf->i2b_addr, buf->i2b_size); 373 cleanup_dealloc_dma: 374 bus_dmamem_free(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs); 375 cleanup_dealloc: 376 kmem_free(*out, sizeof(struct s3c2440_i2s_buf)); 377 return retval; 378 } 379 380 void 381 s3c2440_i2s_free(s3c2440_i2s_buf_t buf) 382 { 383 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 384 385 if (buf->i2b_xfer != NULL) { 386 s3c2440_dmac_free_xfer(buf->i2b_xfer); 387 } 388 389 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 390 bus_dmamap_destroy(sc->sc_dmat, buf->i2b_dmamap); 391 bus_dmamem_unmap(sc->sc_dmat, &buf->i2b_addr, buf->i2b_size); 392 bus_dmamem_free(sc->sc_dmat, buf->i2b_segs, buf->i2b_nsegs); 393 kmem_free(buf, sizeof(struct s3c2440_i2s_buf)); 394 } 395 396 int 397 s3c2440_i2s_output(s3c2440_i2s_buf_t buf, void *block, int bsize, 398 void (*callback)(void*), void *cb_cookie) 399 { 400 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 401 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 402 int retval; 403 dmac_xfer_t xfer = buf->i2b_xfer; 404 405 retval = bus_dmamap_load(sc->sc_dmat, buf->i2b_dmamap, block, 406 bsize, NULL, BUS_DMA_NOWAIT); 407 if (retval != 0) { 408 printf("Failed to load DMA map\n"); 409 return retval; 410 } 411 412 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 413 xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE; 414 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 415 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &i2s->sc_dr; 416 417 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 418 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE; 419 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = buf->i2b_dmamap->dm_nsegs; 420 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = buf->i2b_dmamap->dm_segs; 421 422 xfer->dx_peripheral = DMAC_PERIPH_I2SSDO; 423 424 if (i2s->sc_sample_width == 16) 425 xfer->dx_xfer_width = DMAC_XFER_WIDTH_16BIT; 426 else if (i2s->sc_sample_width == 8) 427 xfer->dx_xfer_width = DMAC_XFER_WIDTH_8BIT; 428 429 xfer->dx_done = s3c2440_i2s_xfer_complete; 430 xfer->dx_cookie = buf; 431 xfer->dx_xfer_mode = DMAC_XFER_MODE_HANDSHAKE; 432 433 buf->i2b_cb = callback; 434 buf->i2b_cb_cookie = cb_cookie; 435 436 s3c2440_dmac_start_xfer(buf->i2b_xfer); 437 438 return 0; 439 } 440 441 int 442 s3c2440_i2s_halt_output(s3c2440_i2s_buf_t buf) 443 { 444 /*int retval;*/ 445 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 446 447 DPRINTF(("Aborting DMA transfer\n")); 448 /*do { 449 retval =*/ s3c2440_dmac_abort_xfer(buf->i2b_xfer); 450 /*} while(retval != 0);*/ 451 DPRINTF(("Aborting DMA transfer: SUCCESS\n")); 452 453 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 454 455 return 0; 456 } 457 458 int 459 s3c2440_i2s_input(s3c2440_i2s_buf_t buf, void *block, int bsize, 460 void (*callback)(void*), void *cb_cookie) 461 { 462 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 463 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 464 int retval; 465 dmac_xfer_t xfer = buf->i2b_xfer; 466 467 retval = bus_dmamap_load(sc->sc_dmat, buf->i2b_dmamap, block, 468 bsize, NULL, BUS_DMA_NOWAIT); 469 if (retval != 0) { 470 printf("Failed to load DMA map\n"); 471 return retval; 472 } 473 474 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 475 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE; 476 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 477 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &i2s->sc_dr; 478 479 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 480 xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE; 481 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = buf->i2b_dmamap->dm_nsegs; 482 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = buf->i2b_dmamap->dm_segs; 483 484 xfer->dx_peripheral = DMAC_PERIPH_I2SSDI; 485 486 if (i2s->sc_sample_width == 16) 487 xfer->dx_xfer_width = DMAC_XFER_WIDTH_16BIT; 488 else if (i2s->sc_sample_width == 8) 489 xfer->dx_xfer_width = DMAC_XFER_WIDTH_8BIT; 490 491 xfer->dx_done = s3c2440_i2s_xfer_complete; 492 xfer->dx_cookie = buf; 493 xfer->dx_xfer_mode = DMAC_XFER_MODE_HANDSHAKE; 494 495 buf->i2b_cb = callback; 496 buf->i2b_cb_cookie = cb_cookie; 497 498 s3c2440_dmac_start_xfer(buf->i2b_xfer); 499 500 return 0; 501 } 502 503 static void 504 s3c2440_i2s_xfer_complete(dmac_xfer_t xfer, void *cookie) 505 { 506 struct s3c2xx0_softc *sc = s3c2xx0_softc; /* Shortcut */ 507 s3c2440_i2s_buf_t buf = cookie; 508 struct s3c2440_i2s_softc *i2s = buf->i2b_parent; 509 510 bus_dmamap_unload(sc->sc_dmat, buf->i2b_dmamap); 511 512 mutex_spin_enter(i2s->sc_intr_lock); 513 (buf->i2b_cb)(buf->i2b_cb_cookie); 514 mutex_spin_exit(i2s->sc_intr_lock); 515 } 516
Indexes created Wed Oct 15 16:09:53 GMT 2025