s3c2440_sdi.c revision 1.1.6.2
1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Fleischer <paul (at) xpg.dk> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 31 #include <sys/param.h> 32 #include <sys/kernel.h> 33 #include <sys/systm.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> /* For M_NOWAIT*/ 36 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <sys/bus.h> 41 #include <machine/cpu.h> 42 43 #include <arm/s3c2xx0/s3c24x0var.h> 44 #include <arm/s3c2xx0/s3c2440var.h> 45 #include <arm/s3c2xx0/s3c24x0reg.h> 46 #include <arm/s3c2xx0/s3c2440reg.h> 47 #include <arm/s3c2xx0/s3c2440_dma.h> 48 49 //#include <arm/s3c2xx0/s3c2440_sdi.h> 50 51 #include <dev/sdmmc/sdmmcchip.h> 52 #include <dev/sdmmc/sdmmcvar.h> 53 54 #include <uvm/uvm_extern.h> 55 /*#define SSSDI_DEBUG*/ 56 #ifdef SSSDI_DEBUG 57 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 58 #else 59 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 60 #endif 61 62 struct sssdi_softc { 63 device_t dev; 64 65 bus_space_tag_t iot; 66 67 bus_space_handle_t ioh; 68 bus_space_handle_t card_ioh; /* Card detect I/O*/ 69 70 device_t sdmmc; 71 72 uint32_t caps; 73 74 int width; /* Transfer width */ 75 void *sc_ih; /* SSSDI Interrupt handler */ 76 77 struct kmutex intr_mtx; 78 struct kcondvar intr_cv; 79 uint32_t intr_status; /* Set by the interrupt handler */ 80 81 dmac_xfer_t sc_xfer; 82 83 bus_dma_segment_t sc_dr; 84 }; 85 86 /* Basic driver stuff */ 87 static int sssdi_match(struct device *, struct cfdata *, void *); 88 static void sssdi_attach(struct device *, struct device *, void *); 89 //static int sssdi_search(struct device *, struct cfdata *, const int *, void *); 90 91 CFATTACH_DECL_NEW(sssdi, sizeof(struct sssdi_softc), sssdi_match, sssdi_attach, 92 NULL, NULL); 93 94 /* SD/MMC chip functions */ 95 static int sssdi_host_reset(sdmmc_chipset_handle_t); 96 static uint32_t sssdi_host_ocr(sdmmc_chipset_handle_t); 97 static int sssdi_maxblklen(sdmmc_chipset_handle_t); 98 static int sssdi_card_detect(sdmmc_chipset_handle_t); 99 static int sssdi_write_protect(sdmmc_chipset_handle_t); 100 static int sssdi_bus_power(sdmmc_chipset_handle_t, uint32_t); 101 static int sssdi_bus_clock(sdmmc_chipset_handle_t, int); 102 static int sssdi_bus_width(sdmmc_chipset_handle_t, int); 103 static int sssdi_bus_rod(sdmmc_chipset_handle_t, int); 104 static void sssdi_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 105 static void sssdi_card_enable_intr(sdmmc_chipset_handle_t, int); 106 static void sssdi_card_intr_ack(sdmmc_chipset_handle_t); 107 108 /* Interrupt Handlers */ 109 int sssdi_intr(void *arg); 110 int sssdi_intr_card(void *arg); 111 112 /* Interrupt helper functions */ 113 static void sssdi_enable_intr(struct sssdi_softc *, uint32_t ); 114 void sssdi_disable_intr(struct sssdi_softc *sc, uint32_t i); 115 void sssdi_clear_intr(struct sssdi_softc *sc); 116 static int sssdi_wait_intr(struct sssdi_softc *sc, uint32_t mask, int timeout); 117 118 /* Programmed I/O transfer helpers */ 119 void sssdi_perform_pio_read(struct sssdi_softc *sc, struct sdmmc_command *cmd); 120 void sssdi_perform_pio_write(struct sssdi_softc *sc, struct sdmmc_command *cmd); 121 122 /* Interrupt helper defines */ 123 #define SDI_CMD_SENT SDIINTMASK_CMD_SENT 124 #define SDI_CMD_TIMEOUT SDIINTMASK_CMD_TIMEOUT 125 #define SDI_RESP_FIN SDIINTMASK_RESP 126 #define SDI_FIFO_RX_FULL SDIINTMASK_RF_FULL 127 #define SDI_FIFO_RX_LAST SDIINTMASK_RF_LAST 128 #define SDI_FIFO_TX_EMPTY SDIINTMASK_TF_EMPTY 129 #define SDI_DATA_FIN SDIINTMASK_DATA_FIN 130 #define SDI_DATA_TIMEOUT SDIINTMASK_DATA_TIMEOUT 131 132 /* Constants */ 133 #define SDI_DMA_WAIT_TIME 5000 /* ms */ 134 #define SDI_CMD_WAIT_TIME 5000 /* ms */ 135 136 /* SDMMC function structure */ 137 struct sdmmc_chip_functions sssdi_functions = { 138 /* host controller reset */ 139 sssdi_host_reset, 140 141 /* host capabilities */ 142 sssdi_host_ocr, 143 sssdi_maxblklen, 144 145 /* card detection */ 146 sssdi_card_detect, 147 148 /* write protect */ 149 sssdi_write_protect, 150 151 /* bus power, clock frequency and width */ 152 sssdi_bus_power, 153 sssdi_bus_clock, 154 sssdi_bus_width, 155 sssdi_bus_rod, 156 157 /* command execution */ 158 sssdi_exec_command, 159 160 /* card interrupt */ 161 sssdi_card_enable_intr, 162 sssdi_card_intr_ack 163 }; 164 165 int 166 sssdi_match(struct device *parent, struct cfdata *match, void *aux) 167 { 168 /* struct s3c2xx0_attach_args *sa = aux;*/ 169 170 /* Not sure how to match here, maybe CPU type? */ 171 return 1; 172 } 173 174 void 175 sssdi_attach(struct device *parent, struct device *self, void *aux) 176 { 177 struct sssdi_softc *sc = device_private(self); 178 struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *)aux; 179 struct sdmmcbus_attach_args saa; 180 bus_space_tag_t iot = sa->sa_iot; 181 uint32_t data; 182 183 sc->dev = self; 184 sc->iot = iot; 185 186 if (bus_space_map(iot, S3C2440_SDI_BASE, S3C2440_SDI_SIZE, 0, &sc->ioh) ) { 187 printf(": failed to map registers"); 188 return; 189 } 190 191 if (bus_space_map(iot, S3C2440_GPIO_BASE, S3C2440_GPIO_SIZE, 0, &sc->card_ioh) ) { 192 printf(": failed to map GPIO memory for card detection"); 193 return; 194 } 195 196 /* Set GPG8 to EINT[16], as it is the card detect line. */ 197 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PGCON); 198 data = GPIO_SET_FUNC(data, 8, 0x2); 199 bus_space_write_4(sc->iot, sc->card_ioh, GPIO_PGCON, data); 200 201 /* Set GPH8 to input, as it is used to detect write protection. */ 202 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PHCON); 203 data = GPIO_SET_FUNC(data, 8, 0x00); 204 bus_space_write_4(sc->iot, sc->card_ioh, GPIO_PHCON, data); 205 206 mutex_init(&sc->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 207 208 cv_init(&sc->intr_cv, "s3c2440_sdiintr"); 209 sc->intr_status = 0; 210 sc->caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA; 211 212 memset(&saa, 0, sizeof(saa)); 213 saa.saa_busname = "sdmmc"; 214 saa.saa_sct = &sssdi_functions; 215 saa.saa_sch = sc; 216 saa.saa_dmat = sa->sa_dmat; 217 saa.saa_clkmin = s3c2xx0_softc->sc_pclk / 256; 218 saa.saa_clkmax = s3c2xx0_softc->sc_pclk / 1; /* PCLK/1 or PCLK/2 depending on how the spec is read */ 219 saa.saa_caps = sc->caps; 220 221 /* Attach our interrupt handler */ 222 sc->sc_ih = s3c24x0_intr_establish(S3C2410_INT_SDI, IPL_SDMMC, IST_EDGE_RISING, sssdi_intr, sc); 223 224 /* Attach interrupt handler to detect change in card status */ 225 s3c2440_extint_establish(16, IPL_SDMMC, IST_EDGE_BOTH, sssdi_intr_card, sc); 226 227 data = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON); 228 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON, data | CLKCON_SDI); 229 230 (void) sssdi_host_reset(sc); 231 232 printf("\n"); 233 234 /* Attach to the generic SD/MMC bus */ 235 /* Is it a good idea to get the private parts of sdmmc ? */ 236 sc->sdmmc = config_found(sc->dev, &saa, NULL); 237 238 sc->sc_xfer = s3c2440_dmac_allocate_xfer(M_NOWAIT); 239 sc->sc_dr.ds_addr = S3C2440_SDI_BASE+SDI_DAT_LI_W; 240 sc->sc_dr.ds_len = 4; 241 } 242 243 int 244 sssdi_host_reset(sdmmc_chipset_handle_t sch) 245 { 246 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 247 248 /* Note that we do not enable the clock just yet. */ 249 bus_space_write_4(sc->iot, sc->ioh, SDI_CON, SDICON_SD_RESET | 250 SDICON_CTYP_SD | SDICON_RCV_IO_INT); 251 /* bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, SDICMDSTA_RSP_CRC | SDICMDSTA_CMD_SENT | 252 SDICMDSTA_CMD_TIMEOUT | SDICMDSTA_RSP_FIN);*/ 253 254 sssdi_clear_intr(sc); 255 sssdi_enable_intr(sc, SDI_CMD_SENT | SDI_CMD_TIMEOUT | SDI_DATA_TIMEOUT 256 | SDI_RESP_FIN); 257 258 return 0; 259 } 260 261 uint32_t 262 sssdi_host_ocr(sdmmc_chipset_handle_t sch) 263 { 264 /* This really ought to be made configurable, I guess... */ 265 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 266 } 267 268 int 269 sssdi_maxblklen(sdmmc_chipset_handle_t sch) 270 { 271 /* The S3C2440 user's manual mentions 4095 as a maximum */ 272 return 4095; 273 } 274 275 int 276 sssdi_card_detect(sdmmc_chipset_handle_t sch) 277 { 278 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 279 uint32_t data; 280 281 DPRINTF(("sssdi_card_detect\n")); 282 283 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PGDAT); 284 285 /* GPIO Port G, pin 8 is high when card is inserted. */ 286 if ( (data & (1<<8)) == 0) { 287 return 1; /* Card Present */ 288 } else { 289 return 0; /* No Card */ 290 } 291 } 292 293 int 294 sssdi_write_protect(sdmmc_chipset_handle_t sch) 295 { 296 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 297 uint32_t data; 298 299 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PHDAT); 300 301 302 /* If GPIO Port H Pin 8 is high, the card is write protected. */ 303 if ( (data & (1<<8)) ) { 304 return 1; /* Write protected */ 305 } else { 306 return 0; /* Writable */ 307 } 308 } 309 310 int 311 sssdi_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 312 { 313 /* Do nothing, we can't adjust the bus power */ 314 return 0; 315 } 316 317 int 318 sssdi_bus_clock(sdmmc_chipset_handle_t sch, int freq) 319 { 320 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 321 int div; 322 int clock_set = 0; 323 int control; 324 int pclk = s3c2xx0_softc->sc_pclk/1000; /*Peripheral bus clock in KHz*/ 325 326 /* Round peripheral bus clock down to nearest MHz */ 327 pclk = (pclk / 1000) * 1000; 328 329 control = bus_space_read_4(sc->iot, sc->ioh, SDI_CON); 330 bus_space_write_4(sc->iot, sc->ioh, SDI_CON, control & ~SDICON_ENCLK); 331 332 DPRINTF(("sssdi_bus_clock (freq: %d KHz)\n", freq)); 333 334 /* If the frequency is zero just keep the clock disabled */ 335 if (freq == 0) 336 return 0; 337 338 for (div = 1; div <= 256; div++) { 339 if ( pclk / div <= freq) { 340 DPRINTF(("Using divisor %d: %d/%d = %d\n", div, pclk, 341 div, pclk/div)); 342 clock_set = 1; 343 bus_space_write_1(sc->iot, sc->ioh, SDI_PRE, div-1); 344 break; 345 } 346 } 347 348 if (clock_set) { 349 bus_space_write_4(sc->iot, sc->ioh, 350 SDI_CON, control | SDICON_ENCLK); 351 if (div-1 == bus_space_read_4(sc->iot, sc->ioh, SDI_PRE)) { 352 /* Clock successfully set, TODO: how do we fail?! */ 353 } 354 355 /* We do not need to wait here, as the sdmmc code will do that 356 for us. */ 357 return 0; 358 } else { 359 return 1; 360 } 361 } 362 363 int 364 sssdi_bus_width(sdmmc_chipset_handle_t sch, int width) 365 { 366 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 367 368 sc->width = width; 369 return 0; 370 } 371 372 int 373 sssdi_bus_rod(sdmmc_chipset_handle_t sch, int on) 374 { 375 return -1; 376 } 377 378 #define SSSDI_TRANSFER_NONE 0 379 #define SSSDI_TRANSFER_READ 1 380 #define SSSDI_TRANSFER_WRITE 2 381 382 void 383 sssdi_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 384 { 385 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 386 uint32_t cmd_control; 387 int status = 0; 388 uint32_t data_status; 389 int transfer = SSSDI_TRANSFER_NONE; 390 dmac_xfer_t xfer; 391 392 /* Reset all status registers prior to sending a command */ 393 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_FSTA, 0xFFFFFFFF); 394 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_STA, 0xFFFFFFFF); 395 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, 0xFFFFFFFF); 396 397 /* Set the argument */ 398 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_ARG, cmd->c_arg); 399 400 /* Prepare the value for the command control register */ 401 cmd_control = (cmd->c_opcode & SDICMDCON_CMD_MASK) | 402 SDICMDCON_HOST_CMD | SDICMDCON_CMST; 403 if (cmd->c_flags & SCF_RSP_PRESENT) 404 cmd_control |= SDICMDCON_WAIT_RSP; 405 if (cmd->c_flags & SCF_RSP_136) 406 cmd_control |= SDICMDCON_LONG_RSP; 407 408 if (cmd->c_datalen > 0 && cmd->c_data != NULL) { 409 /* TODO: Ensure that the above condition matches the semantics 410 of SDICMDCON_WITH_DATA*/ 411 DPRINTF(("DATA, datalen: %d, blk_size: %d\n", cmd->c_datalen, 412 cmd->c_blklen)); 413 cmd_control |= SDICMDCON_WITH_DATA; 414 } 415 416 /* Unfortunately we have to set the ABORT_CMD bit when using CMD12 and 417 CMD52. 418 CMD12 is MMC_STOP_TRANSMISSION. I currently do not know what CMD52 419 is, but it is related to SDIO. 420 */ 421 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) { 422 cmd_control |= SDICMDCON_ABORT_CMD; 423 } 424 425 /* Prepare SDI for data transfer */ 426 bus_space_write_4(sc->iot, sc->ioh, SDI_BSIZE, cmd->c_blklen); 427 428 /* Set maximum transfer timeout */ 429 bus_space_write_4(sc->iot, sc->ioh, SDI_DTIMER, 0x007FFFFF); 430 431 /* Set the timeout as low as possible to trigger timeouts for debugging purposes */ 432 /*bus_space_write_4(sc->iot, sc->ioh, SDI_DTIMER, 0x00005000);*/ 433 434 if ( (cmd->c_flags & SCF_CMD_READ) && 435 (cmd_control & SDICMDCON_WITH_DATA)) { 436 uint32_t data_control; 437 DPRINTF(("Reading %d bytes\n", cmd->c_datalen)); 438 transfer = SSSDI_TRANSFER_READ; 439 440 data_control = SDIDATCON_DATMODE_RECEIVE | SDIDATCON_RACMD | 441 SDIDATCON_DTST | SDIDATCON_BLKMODE | 442 ((cmd->c_datalen / cmd->c_blklen) & SDIDATCON_BLKNUM_MASK) | 443 SDIDATCON_DATA_WORD; 444 445 if (sc->caps & SMC_CAPS_DMA) { 446 data_control |= SDIDATCON_ENDMA; 447 xfer = sc->sc_xfer; 448 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 449 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE; 450 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 451 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr; 452 453 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 454 xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE; 455 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = cmd->c_dmamap->dm_nsegs; 456 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = cmd->c_dmamap->dm_segs; 457 458 /* Let the SD/MMC peripheral control the DMA transfer */ 459 xfer->dx_peripheral = DMAC_PERIPH_SDI; 460 xfer->dx_xfer_width = DMAC_XFER_WIDTH_32BIT; 461 } 462 if (sc->width == 4) { 463 data_control |= SDIDATCON_WIDEBUS; 464 } 465 466 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_CON, data_control); 467 } else if (cmd_control & SDICMDCON_WITH_DATA) { 468 /* Write data */ 469 470 uint32_t data_control; 471 DPRINTF(("Writing %d bytes\n", cmd->c_datalen)); 472 DPRINTF(("Requesting %d blocks\n", 473 cmd->c_datalen / cmd->c_blklen)); 474 transfer = SSSDI_TRANSFER_WRITE; 475 data_control = SDIDATCON_DATMODE_TRANSMIT | SDIDATCON_BLKMODE | 476 SDIDATCON_TARSP | SDIDATCON_DTST | 477 ((cmd->c_datalen / cmd->c_blklen) & SDIDATCON_BLKNUM_MASK) | 478 SDIDATCON_DATA_WORD; 479 480 if (sc->caps & SMC_CAPS_DMA) { 481 data_control |= SDIDATCON_ENDMA; 482 xfer = sc->sc_xfer; 483 484 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 485 xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE; 486 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 487 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr; 488 489 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 490 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE; 491 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = cmd->c_dmamap->dm_nsegs; 492 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = cmd->c_dmamap->dm_segs; 493 494 /* Let the SD/MMC peripheral control the DMA transfer */ 495 xfer->dx_peripheral = DMAC_PERIPH_SDI; 496 xfer->dx_xfer_width = DMAC_XFER_WIDTH_32BIT; 497 } 498 if (sc->width == 4) { 499 data_control |= SDIDATCON_WIDEBUS; 500 } 501 502 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_CON, data_control); 503 } 504 505 /* Send command to SDI */ 506 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_CON, cmd_control); 507 508 /* Wait for command sent acknowledgement, timeout set to 5000ms */ 509 status = sssdi_wait_intr(sc, SDI_CMD_SENT | SDI_CMD_TIMEOUT, mstohz(SDI_CMD_WAIT_TIME)); 510 511 if (status & SDI_CMD_TIMEOUT) { 512 DPRINTF(("Timeout waiting for command acknowledgement\n")); 513 cmd->c_error = ETIMEDOUT; 514 goto out; 515 } else if (status & SDICMDSTA_CMD_SENT) { 516 /* Interrupt handler has acknowledged already, we do not need 517 to do anything further here */ 518 } 519 520 if (!(cmd_control & SDICMDCON_WAIT_RSP)) { 521 cmd->c_flags |= SCF_ITSDONE; 522 goto out; 523 } 524 525 DPRINTF(("waiting for response\n")); 526 527 status = sssdi_wait_intr(sc, SDI_RESP_FIN | SDI_DATA_TIMEOUT, 100); 528 if (status & SDI_CMD_TIMEOUT || status & SDI_DATA_TIMEOUT) { 529 cmd->c_error = ETIMEDOUT; 530 DPRINTF(("Timeout waiting for response\n")); 531 goto out; 532 } 533 DPRINTF(("Got Response\n")); 534 535 536 if (cmd->c_flags & SCF_RSP_136 ) { 537 uint32_t w[4]; 538 539 /* We store the response least significant word first */ 540 w[0] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP3); 541 w[1] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP2); 542 w[2] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP1); 543 w[3] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP0); 544 545 /* The sdmmc subsystem expects that the response is delivered 546 without the lower 8 bits (CRC + '1' bit) */ 547 cmd->c_resp[0] = (w[0] >> 8) | ((w[1] & 0xFF) << 24); 548 cmd->c_resp[1] = (w[1] >> 8) | ((w[2] & 0XFF) << 24); 549 cmd->c_resp[2] = (w[2] >> 8) | ((w[3] & 0XFF) << 24); 550 cmd->c_resp[3] = (w[3] >> 8); 551 552 } else { 553 cmd->c_resp[0] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP0); 554 cmd->c_resp[1] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP1); 555 } 556 557 DPRINTF(("Response: %X %X %X %X\n", 558 cmd->c_resp[0], 559 cmd->c_resp[1], 560 cmd->c_resp[2], 561 cmd->c_resp[3])); 562 563 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_CNT); 564 565 DPRINTF(("Remaining bytes of current block: %d\n", 566 SDIDATCNT_BLK_CNT(status))); 567 DPRINTF(("Remaining Block Number : %d\n", 568 SDIDATCNT_BLK_NUM_CNT(status))); 569 570 data_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_STA); 571 #ifdef SSSDI_DEBUG 572 printf("SDI Data Status Register Before xfer: 0x%X\n", data_status); 573 #endif 574 if (transfer == SSSDI_TRANSFER_READ) { 575 DPRINTF(("Waiting for transfer to complete\n")); 576 577 if (sc->sc_xfer != NULL ) { 578 int dma_error = 0; 579 /* It might not be very efficient to delay the start of 580 the DMA transfer until now, but it works :-). 581 */ 582 s3c2440_dmac_start_xfer(sc->sc_xfer); 583 584 /* Wait until the transfer has completed, timeout is 585 500ms */ 586 dma_error = s3c2440_dmac_wait_xfer(sc->sc_xfer, mstohz(SDI_DMA_WAIT_TIME)); 587 if (dma_error != 0) { 588 //s3c2440_dma_xfer_abort(sc->dma_xfer, mstohz(100)); /* XXX: Handle timeout during abort */ 589 cmd->c_error = dma_error; 590 DPRINTF(("DMA xfer failed: %d\n", dma_error)); 591 goto out; 592 } 593 } else { 594 DPRINTF(("PIO READ\n")); 595 sssdi_perform_pio_read(sc, cmd); 596 } 597 } else if (transfer == SSSDI_TRANSFER_WRITE) { 598 DPRINTF(("Waiting for WRITE transfer to complete\n")); 599 600 if (sc->sc_xfer != NULL) { 601 int dma_error = 0; 602 s3c2440_dmac_start_xfer(sc->sc_xfer); 603 604 dma_error = s3c2440_dmac_wait_xfer(sc->sc_xfer, mstohz(SDI_DMA_WAIT_TIME)); 605 if (dma_error != 0) { 606 //s3c2440_dma_xfer_abort(sc->dma_xfer, mstohz(100)); /* XXX: Handle timeout during abort*/ 607 cmd->c_error = dma_error; 608 DPRINTF(("DMA xfer failed: %d\n", dma_error)); 609 goto out; 610 } 611 } else { 612 DPRINTF(("PIO WRITE\n")); 613 sssdi_perform_pio_write(sc, cmd); 614 } 615 616 if (cmd->c_error == ETIMEDOUT) 617 goto out; 618 619 DPRINTF(("Waiting for transfer to complete\n")); 620 status = sssdi_wait_intr(sc, SDI_DATA_FIN | SDI_DATA_TIMEOUT, 1000); 621 if (status & SDI_CMD_TIMEOUT || status & SDI_DATA_TIMEOUT) { 622 cmd->c_error = ETIMEDOUT; 623 DPRINTF(("Timeout waiting for data to complete\n")); 624 goto out; 625 } 626 DPRINTF(("Done\n")); 627 628 } 629 630 631 /* Response has been received, and any data transfer needed has been 632 performed */ 633 cmd->c_flags |= SCF_ITSDONE; 634 635 out: 636 637 #ifdef SSSDI_DEBUG 638 data_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_STA); 639 printf("SDI Data Status Register after execute: 0x%X\n", data_status); 640 #endif 641 642 /* Clear status register. Their are cleared on the 643 next sssdi_exec_command */ 644 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, 0xFFFFFFFF); 645 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_CON, 0x0); 646 } 647 648 void sssdi_perform_pio_read(struct sssdi_softc *sc, struct sdmmc_command *cmd) 649 { 650 uint32_t status; 651 uint32_t fifo_status; 652 int count; 653 uint32_t written; 654 uint32_t *dest = (uint32_t*)cmd->c_data; 655 656 written = 0; 657 658 while (written < cmd->c_datalen ) { 659 /* Wait until the FIFO is full or has the final data. 660 In the latter case it might not get filled. */ 661 status = sssdi_wait_intr(sc, SDI_FIFO_RX_FULL | SDI_FIFO_RX_LAST, 1000); 662 663 fifo_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_FSTA); 664 count = SDIDATFSTA_FFCNT(fifo_status); 665 666 for(int i=0; i<count; i+=4) { 667 uint32_t buf; 668 669 buf = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_LI_W); 670 *dest = buf; 671 written += 4; 672 dest++; 673 } 674 } 675 } 676 677 void 678 sssdi_perform_pio_write(struct sssdi_softc *sc, struct sdmmc_command *cmd) 679 { 680 uint32_t status; 681 uint32_t fifo_status; 682 int count; 683 uint32_t written; 684 uint32_t *dest = (uint32_t*)cmd->c_data; 685 686 written = 0; 687 688 while (written < cmd->c_datalen ) { 689 /* Wait until the FIFO is full or has the final data. 690 In the latter case it might not get filled. */ 691 DPRINTF(("Waiting for FIFO to become empty\n")); 692 status = sssdi_wait_intr(sc, SDI_FIFO_TX_EMPTY, 1000); 693 694 fifo_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_FSTA); 695 DPRINTF(("PIO Write FIFO Status: 0x%X\n", fifo_status)); 696 count = 64-SDIDATFSTA_FFCNT(fifo_status); 697 698 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_CNT); 699 DPRINTF(("Remaining bytes of current block: %d\n", 700 SDIDATCNT_BLK_CNT(status))); 701 DPRINTF(("Remaining Block Number : %d\n", 702 SDIDATCNT_BLK_NUM_CNT(status))); 703 704 705 status = bus_space_read_4(sc->iot,sc->ioh, SDI_DAT_STA); 706 DPRINTF(("PIO Write Data Status: 0x%X\n", status)); 707 708 if (status & SDIDATSTA_DATA_TIMEOUT) { 709 cmd->c_error = ETIMEDOUT; 710 /* Acknowledge the timeout*/ 711 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_STA, 712 SDIDATSTA_DATA_TIMEOUT); 713 printf("%s: Data timeout\n", device_xname(sc->dev)); 714 break; 715 } 716 717 DPRINTF(("Filling FIFO with %d bytes\n", count)); 718 for(int i=0; i<count; i+=4) { 719 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_LI_W, *dest); 720 written += 4; 721 dest++; 722 } 723 } 724 } 725 726 727 void 728 sssdi_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 729 { 730 printf("sssdi_card_enable_intr not implemented\n"); 731 } 732 733 void 734 sssdi_card_intr_ack(sdmmc_chipset_handle_t sch) 735 { 736 printf("sssdi_card_intr_ack not implemented\n"); 737 } 738 739 int 740 sssdi_intr(void *arg) 741 { 742 struct sssdi_softc *sc = (struct sssdi_softc*)arg; 743 uint32_t status; 744 uint32_t ack_status; 745 746 /* Start by dealing with Command Status */ 747 ack_status = 0; 748 status = bus_space_read_4(sc->iot, sc->ioh, SDI_CMD_STA); 749 750 if (status & SDICMDSTA_CMD_TIMEOUT) { 751 ack_status |= SDICMDSTA_CMD_TIMEOUT; 752 sc->intr_status |= SDI_CMD_TIMEOUT; 753 /*sssdi_disable_intr(sc, SDI_CMD_TIMEOUT);*/ 754 } 755 if (status & SDICMDSTA_CMD_SENT) { 756 ack_status |= SDICMDSTA_CMD_SENT; 757 sc->intr_status |= SDI_CMD_SENT; 758 /* sssdi_disable_intr(sc, SDI_CMD_SENT);*/ 759 } 760 if (status & SDICMDSTA_RSP_FIN) { 761 ack_status |= SDICMDSTA_RSP_FIN; 762 sc->intr_status |= SDI_RESP_FIN; 763 /* sssdi_disable_intr(sc, SDI_RESP_FIN);*/ 764 } 765 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, ack_status); 766 767 /* Next: FIFO Status */ 768 ack_status = 0; 769 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_FSTA); 770 if (status & SDIDATFSTA_RF_FULL) { 771 ack_status |= SDIDATFSTA_RF_FULL; 772 sc->intr_status |= SDI_FIFO_RX_FULL; 773 sssdi_disable_intr(sc, SDI_FIFO_RX_FULL); 774 } 775 if (status & SDIDATFSTA_RF_LAST) { 776 ack_status |= SDIDATFSTA_RF_LAST | SDIDATFSTA_RESET; 777 sc->intr_status |= SDI_FIFO_RX_LAST; 778 sssdi_disable_intr(sc, SDI_FIFO_RX_LAST); 779 } 780 if (status & SDIDATFSTA_TF_EMPTY) { 781 ack_status |= SDIDATFSTA_TF_EMPTY; 782 sc->intr_status |= SDI_FIFO_TX_EMPTY; 783 sssdi_disable_intr(sc, SDI_FIFO_TX_EMPTY); 784 } 785 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_FSTA, ack_status); 786 787 ack_status = 0; 788 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_STA); 789 if (status & SDIDATSTA_DATA_FIN) { 790 DPRINTF(("sssdi_intr: DATA FINISHED\n")); 791 ack_status |= SDIDATSTA_DATA_FIN; 792 sc->intr_status |= SDI_DATA_FIN; 793 sssdi_disable_intr(sc, SDI_DATA_FIN); 794 } 795 if (status & SDIDATSTA_DATA_TIMEOUT) { 796 printf("sssdi_intr: DATA TIMEOUT\n"); 797 ack_status |= SDIDATSTA_DATA_TIMEOUT; 798 sc->intr_status |= SDI_DATA_TIMEOUT; 799 /* Data timeout interrupt is always enabled, thus 800 we do not disable it when we have received one. */ 801 /*sssdi_disable_intr(sc, SDI_DATA_TIMEOUT);*/ 802 803 if (sc->sc_xfer != NULL) { 804 s3c2440_dmac_abort_xfer(sc->sc_xfer); 805 } 806 } 807 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_STA, ack_status); 808 809 mutex_enter(&sc->intr_mtx); 810 cv_broadcast(&sc->intr_cv); 811 mutex_exit(&sc->intr_mtx); 812 813 return 1; 814 } 815 816 int 817 sssdi_intr_card(void *arg) 818 { 819 struct sssdi_softc *sc = (struct sssdi_softc*)arg; 820 821 /* TODO: If card was removed then abort any current command */ 822 823 sdmmc_needs_discover(sc->sdmmc); 824 825 return 1; /* handled */ 826 } 827 828 static void 829 sssdi_enable_intr(struct sssdi_softc *sc, uint32_t i) 830 { 831 uint32_t v = bus_space_read_4(sc->iot, sc->ioh, SDI_INT_MASK); 832 bus_space_write_4(sc->iot, sc->ioh, SDI_INT_MASK, v | i ); 833 } 834 835 void 836 sssdi_disable_intr(struct sssdi_softc *sc, uint32_t i) 837 { 838 uint32_t v = bus_space_read_4(sc->iot, sc->ioh, SDI_INT_MASK); 839 bus_space_write_4(sc->iot, sc->ioh, SDI_INT_MASK, v & ~i ); 840 } 841 842 void 843 sssdi_clear_intr(struct sssdi_softc *sc) 844 { 845 bus_space_write_4(sc->iot, sc->ioh, SDI_INT_MASK, 0x0); 846 } 847 848 static int 849 sssdi_wait_intr(struct sssdi_softc *sc, uint32_t mask, int timeout) 850 { 851 uint32_t status; 852 853 /* Wait until the command has been sent */ 854 mutex_enter(&sc->intr_mtx); 855 sssdi_enable_intr(sc, mask); 856 status = sc->intr_status & mask; 857 while(status == 0) { 858 859 if (cv_timedwait(&sc->intr_cv, &sc->intr_mtx, timeout) == 860 EWOULDBLOCK ) { 861 DPRINTF(("Timed out waiting for interrupt from SDI controller\n")); 862 status |= SDI_CMD_TIMEOUT; 863 break; 864 } 865 866 status = sc->intr_status & mask; 867 } 868 869 sc->intr_status &= ~status; 870 mutex_exit(&sc->intr_mtx); 871 872 return status; 873 } 874
Indexes created Mon Oct 20 03:09:53 GMT 2025