s3c2440_sdi.c revision 1.3
1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Fleischer <paul (at) xpg.dk> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 31 #include <sys/param.h> 32 #include <sys/kernel.h> 33 #include <sys/systm.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> /* For M_NOWAIT*/ 36 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <sys/bus.h> 41 #include <machine/cpu.h> 42 43 #include <arm/s3c2xx0/s3c24x0var.h> 44 #include <arm/s3c2xx0/s3c2440var.h> 45 #include <arm/s3c2xx0/s3c24x0reg.h> 46 #include <arm/s3c2xx0/s3c2440reg.h> 47 #include <arm/s3c2xx0/s3c2440_dma.h> 48 49 //#include <arm/s3c2xx0/s3c2440_sdi.h> 50 51 #include <dev/sdmmc/sdmmcchip.h> 52 #include <dev/sdmmc/sdmmcvar.h> 53 54 #include <uvm/uvm_extern.h> 55 /*#define SSSDI_DEBUG*/ 56 #ifdef SSSDI_DEBUG 57 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 58 #else 59 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 60 #endif 61 62 struct sssdi_softc { 63 device_t dev; 64 65 bus_space_tag_t iot; 66 67 bus_space_handle_t ioh; 68 bus_space_handle_t card_ioh; /* Card detect I/O*/ 69 70 device_t sdmmc; 71 72 uint32_t caps; 73 74 int width; /* Transfer width */ 75 void *sc_ih; /* SSSDI Interrupt handler */ 76 77 struct kmutex intr_mtx; 78 struct kcondvar intr_cv; 79 uint32_t intr_status; /* Set by the interrupt handler */ 80 81 dmac_xfer_t sc_xfer; 82 83 bus_dma_segment_t sc_dr; 84 }; 85 86 /* Basic driver stuff */ 87 static int sssdi_match(device_t, cfdata_t, void *); 88 static void sssdi_attach(device_t, device_t, void *); 89 90 CFATTACH_DECL_NEW(sssdi, sizeof(struct sssdi_softc), sssdi_match, sssdi_attach, 91 NULL, NULL); 92 93 /* SD/MMC chip functions */ 94 static int sssdi_host_reset(sdmmc_chipset_handle_t); 95 static uint32_t sssdi_host_ocr(sdmmc_chipset_handle_t); 96 static int sssdi_maxblklen(sdmmc_chipset_handle_t); 97 static int sssdi_card_detect(sdmmc_chipset_handle_t); 98 static int sssdi_write_protect(sdmmc_chipset_handle_t); 99 static int sssdi_bus_power(sdmmc_chipset_handle_t, uint32_t); 100 static int sssdi_bus_clock(sdmmc_chipset_handle_t, int); 101 static int sssdi_bus_width(sdmmc_chipset_handle_t, int); 102 static int sssdi_bus_rod(sdmmc_chipset_handle_t, int); 103 static void sssdi_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 104 static void sssdi_card_enable_intr(sdmmc_chipset_handle_t, int); 105 static void sssdi_card_intr_ack(sdmmc_chipset_handle_t); 106 107 /* Interrupt Handlers */ 108 int sssdi_intr(void *arg); 109 int sssdi_intr_card(void *arg); 110 111 /* Interrupt helper functions */ 112 static void sssdi_enable_intr(struct sssdi_softc *, uint32_t ); 113 void sssdi_disable_intr(struct sssdi_softc *sc, uint32_t i); 114 void sssdi_clear_intr(struct sssdi_softc *sc); 115 static int sssdi_wait_intr(struct sssdi_softc *sc, uint32_t mask, int timeout); 116 117 /* Programmed I/O transfer helpers */ 118 void sssdi_perform_pio_read(struct sssdi_softc *sc, struct sdmmc_command *cmd); 119 void sssdi_perform_pio_write(struct sssdi_softc *sc, struct sdmmc_command *cmd); 120 121 /* Interrupt helper defines */ 122 #define SDI_CMD_SENT SDIINTMASK_CMD_SENT 123 #define SDI_CMD_TIMEOUT SDIINTMASK_CMD_TIMEOUT 124 #define SDI_RESP_FIN SDIINTMASK_RESP 125 #define SDI_FIFO_RX_FULL SDIINTMASK_RF_FULL 126 #define SDI_FIFO_RX_LAST SDIINTMASK_RF_LAST 127 #define SDI_FIFO_TX_EMPTY SDIINTMASK_TF_EMPTY 128 #define SDI_DATA_FIN SDIINTMASK_DATA_FIN 129 #define SDI_DATA_TIMEOUT SDIINTMASK_DATA_TIMEOUT 130 131 /* Constants */ 132 #define SDI_DMA_WAIT_TIME 5000 /* ms */ 133 #define SDI_CMD_WAIT_TIME 5000 /* ms */ 134 135 /* SDMMC function structure */ 136 struct sdmmc_chip_functions sssdi_functions = { 137 /* host controller reset */ 138 sssdi_host_reset, 139 140 /* host capabilities */ 141 sssdi_host_ocr, 142 sssdi_maxblklen, 143 144 /* card detection */ 145 sssdi_card_detect, 146 147 /* write protect */ 148 sssdi_write_protect, 149 150 /* bus power, clock frequency and width */ 151 sssdi_bus_power, 152 sssdi_bus_clock, 153 sssdi_bus_width, 154 sssdi_bus_rod, 155 156 /* command execution */ 157 sssdi_exec_command, 158 159 /* card interrupt */ 160 sssdi_card_enable_intr, 161 sssdi_card_intr_ack 162 }; 163 164 int 165 sssdi_match(device_t parent, cfdata_t match, void *aux) 166 { 167 /* struct s3c2xx0_attach_args *sa = aux;*/ 168 169 /* Not sure how to match here, maybe CPU type? */ 170 return 1; 171 } 172 173 void 174 sssdi_attach(device_t parent, device_t self, void *aux) 175 { 176 struct sssdi_softc *sc = device_private(self); 177 struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *)aux; 178 struct sdmmcbus_attach_args saa; 179 bus_space_tag_t iot = sa->sa_iot; 180 uint32_t data; 181 182 sc->dev = self; 183 sc->iot = iot; 184 185 if (bus_space_map(iot, S3C2440_SDI_BASE, S3C2440_SDI_SIZE, 0, &sc->ioh) ) { 186 printf(": failed to map registers"); 187 return; 188 } 189 190 if (bus_space_map(iot, S3C2440_GPIO_BASE, S3C2440_GPIO_SIZE, 0, &sc->card_ioh) ) { 191 printf(": failed to map GPIO memory for card detection"); 192 return; 193 } 194 195 /* Set GPG8 to EINT[16], as it is the card detect line. */ 196 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PGCON); 197 data = GPIO_SET_FUNC(data, 8, 0x2); 198 bus_space_write_4(sc->iot, sc->card_ioh, GPIO_PGCON, data); 199 200 /* Set GPH8 to input, as it is used to detect write protection. */ 201 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PHCON); 202 data = GPIO_SET_FUNC(data, 8, 0x00); 203 bus_space_write_4(sc->iot, sc->card_ioh, GPIO_PHCON, data); 204 205 mutex_init(&sc->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 206 207 cv_init(&sc->intr_cv, "s3c2440_sdiintr"); 208 sc->intr_status = 0; 209 sc->caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA; 210 211 memset(&saa, 0, sizeof(saa)); 212 saa.saa_busname = "sdmmc"; 213 saa.saa_sct = &sssdi_functions; 214 saa.saa_sch = sc; 215 saa.saa_dmat = sa->sa_dmat; 216 saa.saa_clkmin = s3c2xx0_softc->sc_pclk / 256; 217 saa.saa_clkmax = s3c2xx0_softc->sc_pclk / 1; /* PCLK/1 or PCLK/2 depending on how the spec is read */ 218 saa.saa_caps = sc->caps; 219 220 /* Attach our interrupt handler */ 221 sc->sc_ih = s3c24x0_intr_establish(S3C2410_INT_SDI, IPL_SDMMC, IST_EDGE_RISING, sssdi_intr, sc); 222 223 /* Attach interrupt handler to detect change in card status */ 224 s3c2440_extint_establish(16, IPL_SDMMC, IST_EDGE_BOTH, sssdi_intr_card, sc); 225 226 data = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON); 227 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON, data | CLKCON_SDI); 228 229 (void) sssdi_host_reset(sc); 230 231 printf("\n"); 232 233 /* Attach to the generic SD/MMC bus */ 234 /* Is it a good idea to get the private parts of sdmmc ? */ 235 sc->sdmmc = config_found(sc->dev, &saa, NULL); 236 237 sc->sc_xfer = s3c2440_dmac_allocate_xfer(M_NOWAIT); 238 sc->sc_dr.ds_addr = S3C2440_SDI_BASE+SDI_DAT_LI_W; 239 sc->sc_dr.ds_len = 4; 240 } 241 242 int 243 sssdi_host_reset(sdmmc_chipset_handle_t sch) 244 { 245 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 246 247 /* Note that we do not enable the clock just yet. */ 248 bus_space_write_4(sc->iot, sc->ioh, SDI_CON, SDICON_SD_RESET | 249 SDICON_CTYP_SD | SDICON_RCV_IO_INT); 250 /* bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, SDICMDSTA_RSP_CRC | SDICMDSTA_CMD_SENT | 251 SDICMDSTA_CMD_TIMEOUT | SDICMDSTA_RSP_FIN);*/ 252 253 sssdi_clear_intr(sc); 254 sssdi_enable_intr(sc, SDI_CMD_SENT | SDI_CMD_TIMEOUT | SDI_DATA_TIMEOUT 255 | SDI_RESP_FIN); 256 257 return 0; 258 } 259 260 uint32_t 261 sssdi_host_ocr(sdmmc_chipset_handle_t sch) 262 { 263 /* This really ought to be made configurable, I guess... */ 264 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 265 } 266 267 int 268 sssdi_maxblklen(sdmmc_chipset_handle_t sch) 269 { 270 /* The S3C2440 user's manual mentions 4095 as a maximum */ 271 return 4095; 272 } 273 274 int 275 sssdi_card_detect(sdmmc_chipset_handle_t sch) 276 { 277 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 278 uint32_t data; 279 280 DPRINTF(("sssdi_card_detect\n")); 281 282 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PGDAT); 283 284 /* GPIO Port G, pin 8 is high when card is inserted. */ 285 if ( (data & (1<<8)) == 0) { 286 return 1; /* Card Present */ 287 } else { 288 return 0; /* No Card */ 289 } 290 } 291 292 int 293 sssdi_write_protect(sdmmc_chipset_handle_t sch) 294 { 295 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 296 uint32_t data; 297 298 data = bus_space_read_4(sc->iot, sc->card_ioh, GPIO_PHDAT); 299 300 301 /* If GPIO Port H Pin 8 is high, the card is write protected. */ 302 if ( (data & (1<<8)) ) { 303 return 1; /* Write protected */ 304 } else { 305 return 0; /* Writable */ 306 } 307 } 308 309 int 310 sssdi_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 311 { 312 /* Do nothing, we can't adjust the bus power */ 313 return 0; 314 } 315 316 int 317 sssdi_bus_clock(sdmmc_chipset_handle_t sch, int freq) 318 { 319 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 320 int div; 321 int clock_set = 0; 322 int control; 323 int pclk = s3c2xx0_softc->sc_pclk/1000; /*Peripheral bus clock in KHz*/ 324 325 /* Round peripheral bus clock down to nearest MHz */ 326 pclk = (pclk / 1000) * 1000; 327 328 control = bus_space_read_4(sc->iot, sc->ioh, SDI_CON); 329 bus_space_write_4(sc->iot, sc->ioh, SDI_CON, control & ~SDICON_ENCLK); 330 331 DPRINTF(("sssdi_bus_clock (freq: %d KHz)\n", freq)); 332 333 /* If the frequency is zero just keep the clock disabled */ 334 if (freq == 0) 335 return 0; 336 337 for (div = 1; div <= 256; div++) { 338 if ( pclk / div <= freq) { 339 DPRINTF(("Using divisor %d: %d/%d = %d\n", div, pclk, 340 div, pclk/div)); 341 clock_set = 1; 342 bus_space_write_1(sc->iot, sc->ioh, SDI_PRE, div-1); 343 break; 344 } 345 } 346 347 if (clock_set) { 348 bus_space_write_4(sc->iot, sc->ioh, 349 SDI_CON, control | SDICON_ENCLK); 350 if (div-1 == bus_space_read_4(sc->iot, sc->ioh, SDI_PRE)) { 351 /* Clock successfully set, TODO: how do we fail?! */ 352 } 353 354 /* We do not need to wait here, as the sdmmc code will do that 355 for us. */ 356 return 0; 357 } else { 358 return 1; 359 } 360 } 361 362 int 363 sssdi_bus_width(sdmmc_chipset_handle_t sch, int width) 364 { 365 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 366 367 sc->width = width; 368 return 0; 369 } 370 371 int 372 sssdi_bus_rod(sdmmc_chipset_handle_t sch, int on) 373 { 374 return -1; 375 } 376 377 #define SSSDI_TRANSFER_NONE 0 378 #define SSSDI_TRANSFER_READ 1 379 #define SSSDI_TRANSFER_WRITE 2 380 381 void 382 sssdi_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 383 { 384 struct sssdi_softc *sc = (struct sssdi_softc*)sch; 385 uint32_t cmd_control; 386 int status = 0; 387 #ifdef SSSDI_DEBUG 388 uint32_t data_status; 389 #endif 390 int transfer = SSSDI_TRANSFER_NONE; 391 dmac_xfer_t xfer; 392 393 /* Reset all status registers prior to sending a command */ 394 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_FSTA, 0xFFFFFFFF); 395 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_STA, 0xFFFFFFFF); 396 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, 0xFFFFFFFF); 397 398 /* Set the argument */ 399 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_ARG, cmd->c_arg); 400 401 /* Prepare the value for the command control register */ 402 cmd_control = (cmd->c_opcode & SDICMDCON_CMD_MASK) | 403 SDICMDCON_HOST_CMD | SDICMDCON_CMST; 404 if (cmd->c_flags & SCF_RSP_PRESENT) 405 cmd_control |= SDICMDCON_WAIT_RSP; 406 if (cmd->c_flags & SCF_RSP_136) 407 cmd_control |= SDICMDCON_LONG_RSP; 408 409 if (cmd->c_datalen > 0 && cmd->c_data != NULL) { 410 /* TODO: Ensure that the above condition matches the semantics 411 of SDICMDCON_WITH_DATA*/ 412 DPRINTF(("DATA, datalen: %d, blk_size: %d\n", cmd->c_datalen, 413 cmd->c_blklen)); 414 cmd_control |= SDICMDCON_WITH_DATA; 415 } 416 417 /* Unfortunately we have to set the ABORT_CMD bit when using CMD12 and 418 CMD52. 419 CMD12 is MMC_STOP_TRANSMISSION. I currently do not know what CMD52 420 is, but it is related to SDIO. 421 */ 422 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) { 423 cmd_control |= SDICMDCON_ABORT_CMD; 424 } 425 426 /* Prepare SDI for data transfer */ 427 bus_space_write_4(sc->iot, sc->ioh, SDI_BSIZE, cmd->c_blklen); 428 429 /* Set maximum transfer timeout */ 430 bus_space_write_4(sc->iot, sc->ioh, SDI_DTIMER, 0x007FFFFF); 431 432 /* Set the timeout as low as possible to trigger timeouts for debugging purposes */ 433 /*bus_space_write_4(sc->iot, sc->ioh, SDI_DTIMER, 0x00005000);*/ 434 435 if ( (cmd->c_flags & SCF_CMD_READ) && 436 (cmd_control & SDICMDCON_WITH_DATA)) { 437 uint32_t data_control; 438 DPRINTF(("Reading %d bytes\n", cmd->c_datalen)); 439 transfer = SSSDI_TRANSFER_READ; 440 441 data_control = SDIDATCON_DATMODE_RECEIVE | SDIDATCON_RACMD | 442 SDIDATCON_DTST | SDIDATCON_BLKMODE | 443 ((cmd->c_datalen / cmd->c_blklen) & SDIDATCON_BLKNUM_MASK) | 444 SDIDATCON_DATA_WORD; 445 446 if (sc->caps & SMC_CAPS_DMA) { 447 data_control |= SDIDATCON_ENDMA; 448 xfer = sc->sc_xfer; 449 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 450 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = FALSE; 451 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1; 452 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr; 453 454 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 455 xfer->dx_desc[DMAC_DESC_DST].xd_increment = TRUE; 456 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = cmd->c_dmamap->dm_nsegs; 457 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = cmd->c_dmamap->dm_segs; 458 459 /* Let the SD/MMC peripheral control the DMA transfer */ 460 xfer->dx_peripheral = DMAC_PERIPH_SDI; 461 xfer->dx_xfer_width = DMAC_XFER_WIDTH_32BIT; 462 } 463 if (sc->width == 4) { 464 data_control |= SDIDATCON_WIDEBUS; 465 } 466 467 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_CON, data_control); 468 } else if (cmd_control & SDICMDCON_WITH_DATA) { 469 /* Write data */ 470 471 uint32_t data_control; 472 DPRINTF(("Writing %d bytes\n", cmd->c_datalen)); 473 DPRINTF(("Requesting %d blocks\n", 474 cmd->c_datalen / cmd->c_blklen)); 475 transfer = SSSDI_TRANSFER_WRITE; 476 data_control = SDIDATCON_DATMODE_TRANSMIT | SDIDATCON_BLKMODE | 477 SDIDATCON_TARSP | SDIDATCON_DTST | 478 ((cmd->c_datalen / cmd->c_blklen) & SDIDATCON_BLKNUM_MASK) | 479 SDIDATCON_DATA_WORD; 480 481 if (sc->caps & SMC_CAPS_DMA) { 482 data_control |= SDIDATCON_ENDMA; 483 xfer = sc->sc_xfer; 484 485 xfer->dx_desc[DMAC_DESC_DST].xd_bus_type = DMAC_BUS_TYPE_PERIPHERAL; 486 xfer->dx_desc[DMAC_DESC_DST].xd_increment = FALSE; 487 xfer->dx_desc[DMAC_DESC_DST].xd_nsegs = 1; 488 xfer->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr; 489 490 xfer->dx_desc[DMAC_DESC_SRC].xd_bus_type = DMAC_BUS_TYPE_SYSTEM; 491 xfer->dx_desc[DMAC_DESC_SRC].xd_increment = TRUE; 492 xfer->dx_desc[DMAC_DESC_SRC].xd_nsegs = cmd->c_dmamap->dm_nsegs; 493 xfer->dx_desc[DMAC_DESC_SRC].xd_dma_segs = cmd->c_dmamap->dm_segs; 494 495 /* Let the SD/MMC peripheral control the DMA transfer */ 496 xfer->dx_peripheral = DMAC_PERIPH_SDI; 497 xfer->dx_xfer_width = DMAC_XFER_WIDTH_32BIT; 498 } 499 if (sc->width == 4) { 500 data_control |= SDIDATCON_WIDEBUS; 501 } 502 503 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_CON, data_control); 504 } 505 506 /* Send command to SDI */ 507 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_CON, cmd_control); 508 509 /* Wait for command sent acknowledgement, timeout set to 5000ms */ 510 status = sssdi_wait_intr(sc, SDI_CMD_SENT | SDI_CMD_TIMEOUT, mstohz(SDI_CMD_WAIT_TIME)); 511 512 if (status & SDI_CMD_TIMEOUT) { 513 DPRINTF(("Timeout waiting for command acknowledgement\n")); 514 cmd->c_error = ETIMEDOUT; 515 goto out; 516 } else if (status & SDICMDSTA_CMD_SENT) { 517 /* Interrupt handler has acknowledged already, we do not need 518 to do anything further here */ 519 } 520 521 if (!(cmd_control & SDICMDCON_WAIT_RSP)) { 522 cmd->c_flags |= SCF_ITSDONE; 523 goto out; 524 } 525 526 DPRINTF(("waiting for response\n")); 527 528 status = sssdi_wait_intr(sc, SDI_RESP_FIN | SDI_DATA_TIMEOUT, 100); 529 if (status & SDI_CMD_TIMEOUT || status & SDI_DATA_TIMEOUT) { 530 cmd->c_error = ETIMEDOUT; 531 DPRINTF(("Timeout waiting for response\n")); 532 goto out; 533 } 534 DPRINTF(("Got Response\n")); 535 536 537 if (cmd->c_flags & SCF_RSP_136 ) { 538 uint32_t w[4]; 539 540 /* We store the response least significant word first */ 541 w[0] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP3); 542 w[1] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP2); 543 w[2] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP1); 544 w[3] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP0); 545 546 /* The sdmmc subsystem expects that the response is delivered 547 without the lower 8 bits (CRC + '1' bit) */ 548 cmd->c_resp[0] = (w[0] >> 8) | ((w[1] & 0xFF) << 24); 549 cmd->c_resp[1] = (w[1] >> 8) | ((w[2] & 0XFF) << 24); 550 cmd->c_resp[2] = (w[2] >> 8) | ((w[3] & 0XFF) << 24); 551 cmd->c_resp[3] = (w[3] >> 8); 552 553 } else { 554 cmd->c_resp[0] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP0); 555 cmd->c_resp[1] = bus_space_read_4(sc->iot, sc->ioh, SDI_RSP1); 556 } 557 558 DPRINTF(("Response: %X %X %X %X\n", 559 cmd->c_resp[0], 560 cmd->c_resp[1], 561 cmd->c_resp[2], 562 cmd->c_resp[3])); 563 564 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_CNT); 565 566 DPRINTF(("Remaining bytes of current block: %d\n", 567 SDIDATCNT_BLK_CNT(status))); 568 DPRINTF(("Remaining Block Number : %d\n", 569 SDIDATCNT_BLK_NUM_CNT(status))); 570 571 #ifdef SSSDI_DEBUG 572 data_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_STA); 573 printf("SDI Data Status Register Before xfer: 0x%X\n", data_status); 574 #endif 575 if (transfer == SSSDI_TRANSFER_READ) { 576 DPRINTF(("Waiting for transfer to complete\n")); 577 578 if (sc->sc_xfer != NULL ) { 579 int dma_error = 0; 580 /* It might not be very efficient to delay the start of 581 the DMA transfer until now, but it works :-). 582 */ 583 s3c2440_dmac_start_xfer(sc->sc_xfer); 584 585 /* Wait until the transfer has completed, timeout is 586 500ms */ 587 dma_error = s3c2440_dmac_wait_xfer(sc->sc_xfer, mstohz(SDI_DMA_WAIT_TIME)); 588 if (dma_error != 0) { 589 //s3c2440_dma_xfer_abort(sc->dma_xfer, mstohz(100)); /* XXX: Handle timeout during abort */ 590 cmd->c_error = dma_error; 591 DPRINTF(("DMA xfer failed: %d\n", dma_error)); 592 goto out; 593 } 594 } else { 595 DPRINTF(("PIO READ\n")); 596 sssdi_perform_pio_read(sc, cmd); 597 } 598 } else if (transfer == SSSDI_TRANSFER_WRITE) { 599 DPRINTF(("Waiting for WRITE transfer to complete\n")); 600 601 if (sc->sc_xfer != NULL) { 602 int dma_error = 0; 603 s3c2440_dmac_start_xfer(sc->sc_xfer); 604 605 dma_error = s3c2440_dmac_wait_xfer(sc->sc_xfer, mstohz(SDI_DMA_WAIT_TIME)); 606 if (dma_error != 0) { 607 //s3c2440_dma_xfer_abort(sc->dma_xfer, mstohz(100)); /* XXX: Handle timeout during abort*/ 608 cmd->c_error = dma_error; 609 DPRINTF(("DMA xfer failed: %d\n", dma_error)); 610 goto out; 611 } 612 } else { 613 DPRINTF(("PIO WRITE\n")); 614 sssdi_perform_pio_write(sc, cmd); 615 } 616 617 if (cmd->c_error == ETIMEDOUT) 618 goto out; 619 620 DPRINTF(("Waiting for transfer to complete\n")); 621 status = sssdi_wait_intr(sc, SDI_DATA_FIN | SDI_DATA_TIMEOUT, 1000); 622 if (status & SDI_CMD_TIMEOUT || status & SDI_DATA_TIMEOUT) { 623 cmd->c_error = ETIMEDOUT; 624 DPRINTF(("Timeout waiting for data to complete\n")); 625 goto out; 626 } 627 DPRINTF(("Done\n")); 628 629 } 630 631 632 /* Response has been received, and any data transfer needed has been 633 performed */ 634 cmd->c_flags |= SCF_ITSDONE; 635 636 out: 637 638 #ifdef SSSDI_DEBUG 639 data_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_STA); 640 printf("SDI Data Status Register after execute: 0x%X\n", data_status); 641 #endif 642 643 /* Clear status register. Their are cleared on the 644 next sssdi_exec_command */ 645 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, 0xFFFFFFFF); 646 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_CON, 0x0); 647 } 648 649 void sssdi_perform_pio_read(struct sssdi_softc *sc, struct sdmmc_command *cmd) 650 { 651 uint32_t fifo_status; 652 int count; 653 uint32_t written; 654 uint32_t *dest = (uint32_t*)cmd->c_data; 655 656 written = 0; 657 658 while (written < cmd->c_datalen ) { 659 /* Wait until the FIFO is full or has the final data. 660 In the latter case it might not get filled. */ 661 sssdi_wait_intr(sc, SDI_FIFO_RX_FULL | SDI_FIFO_RX_LAST, 1000); 662 663 fifo_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_FSTA); 664 count = SDIDATFSTA_FFCNT(fifo_status); 665 666 for(int i=0; i<count; i+=4) { 667 uint32_t buf; 668 669 buf = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_LI_W); 670 *dest = buf; 671 written += 4; 672 dest++; 673 } 674 } 675 } 676 677 void 678 sssdi_perform_pio_write(struct sssdi_softc *sc, struct sdmmc_command *cmd) 679 { 680 uint32_t status; 681 uint32_t fifo_status; 682 int count; 683 uint32_t written; 684 uint32_t *dest = (uint32_t*)cmd->c_data; 685 686 written = 0; 687 688 while (written < cmd->c_datalen ) { 689 /* Wait until the FIFO is full or has the final data. 690 In the latter case it might not get filled. */ 691 DPRINTF(("Waiting for FIFO to become empty\n")); 692 status = sssdi_wait_intr(sc, SDI_FIFO_TX_EMPTY, 1000); 693 694 fifo_status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_FSTA); 695 DPRINTF(("PIO Write FIFO Status: 0x%X\n", fifo_status)); 696 count = 64-SDIDATFSTA_FFCNT(fifo_status); 697 698 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_CNT); 699 DPRINTF(("Remaining bytes of current block: %d\n", 700 SDIDATCNT_BLK_CNT(status))); 701 DPRINTF(("Remaining Block Number : %d\n", 702 SDIDATCNT_BLK_NUM_CNT(status))); 703 704 705 status = bus_space_read_4(sc->iot,sc->ioh, SDI_DAT_STA); 706 DPRINTF(("PIO Write Data Status: 0x%X\n", status)); 707 708 if (status & SDIDATSTA_DATA_TIMEOUT) { 709 cmd->c_error = ETIMEDOUT; 710 /* Acknowledge the timeout*/ 711 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_STA, 712 SDIDATSTA_DATA_TIMEOUT); 713 printf("%s: Data timeout\n", device_xname(sc->dev)); 714 break; 715 } 716 717 DPRINTF(("Filling FIFO with %d bytes\n", count)); 718 for(int i=0; i<count; i+=4) { 719 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_LI_W, *dest); 720 written += 4; 721 dest++; 722 } 723 } 724 } 725 726 727 void 728 sssdi_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 729 { 730 printf("sssdi_card_enable_intr not implemented\n"); 731 } 732 733 void 734 sssdi_card_intr_ack(sdmmc_chipset_handle_t sch) 735 { 736 printf("sssdi_card_intr_ack not implemented\n"); 737 } 738 739 int 740 sssdi_intr(void *arg) 741 { 742 struct sssdi_softc *sc = (struct sssdi_softc*)arg; 743 uint32_t status; 744 uint32_t ack_status; 745 746 /* Start by dealing with Command Status */ 747 ack_status = 0; 748 status = bus_space_read_4(sc->iot, sc->ioh, SDI_CMD_STA); 749 750 if (status & SDICMDSTA_CMD_TIMEOUT) { 751 ack_status |= SDICMDSTA_CMD_TIMEOUT; 752 sc->intr_status |= SDI_CMD_TIMEOUT; 753 /*sssdi_disable_intr(sc, SDI_CMD_TIMEOUT);*/ 754 } 755 if (status & SDICMDSTA_CMD_SENT) { 756 ack_status |= SDICMDSTA_CMD_SENT; 757 sc->intr_status |= SDI_CMD_SENT; 758 /* sssdi_disable_intr(sc, SDI_CMD_SENT);*/ 759 } 760 if (status & SDICMDSTA_RSP_FIN) { 761 ack_status |= SDICMDSTA_RSP_FIN; 762 sc->intr_status |= SDI_RESP_FIN; 763 /* sssdi_disable_intr(sc, SDI_RESP_FIN);*/ 764 } 765 bus_space_write_4(sc->iot, sc->ioh, SDI_CMD_STA, ack_status); 766 767 /* Next: FIFO Status */ 768 ack_status = 0; 769 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_FSTA); 770 if (status & SDIDATFSTA_RF_FULL) { 771 ack_status |= SDIDATFSTA_RF_FULL; 772 sc->intr_status |= SDI_FIFO_RX_FULL; 773 sssdi_disable_intr(sc, SDI_FIFO_RX_FULL); 774 } 775 if (status & SDIDATFSTA_RF_LAST) { 776 ack_status |= SDIDATFSTA_RF_LAST | SDIDATFSTA_RESET; 777 sc->intr_status |= SDI_FIFO_RX_LAST; 778 sssdi_disable_intr(sc, SDI_FIFO_RX_LAST); 779 } 780 if (status & SDIDATFSTA_TF_EMPTY) { 781 ack_status |= SDIDATFSTA_TF_EMPTY; 782 sc->intr_status |= SDI_FIFO_TX_EMPTY; 783 sssdi_disable_intr(sc, SDI_FIFO_TX_EMPTY); 784 } 785 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_FSTA, ack_status); 786 787 ack_status = 0; 788 status = bus_space_read_4(sc->iot, sc->ioh, SDI_DAT_STA); 789 if (status & SDIDATSTA_DATA_FIN) { 790 DPRINTF(("sssdi_intr: DATA FINISHED\n")); 791 ack_status |= SDIDATSTA_DATA_FIN; 792 sc->intr_status |= SDI_DATA_FIN; 793 sssdi_disable_intr(sc, SDI_DATA_FIN); 794 } 795 if (status & SDIDATSTA_DATA_TIMEOUT) { 796 printf("sssdi_intr: DATA TIMEOUT\n"); 797 ack_status |= SDIDATSTA_DATA_TIMEOUT; 798 sc->intr_status |= SDI_DATA_TIMEOUT; 799 /* Data timeout interrupt is always enabled, thus 800 we do not disable it when we have received one. */ 801 /*sssdi_disable_intr(sc, SDI_DATA_TIMEOUT);*/ 802 803 if (sc->sc_xfer != NULL) { 804 s3c2440_dmac_abort_xfer(sc->sc_xfer); 805 } 806 } 807 bus_space_write_4(sc->iot, sc->ioh, SDI_DAT_STA, ack_status); 808 809 mutex_enter(&sc->intr_mtx); 810 cv_broadcast(&sc->intr_cv); 811 mutex_exit(&sc->intr_mtx); 812 813 return 1; 814 } 815 816 int 817 sssdi_intr_card(void *arg) 818 { 819 struct sssdi_softc *sc = (struct sssdi_softc*)arg; 820 821 /* TODO: If card was removed then abort any current command */ 822 823 sdmmc_needs_discover(sc->sdmmc); 824 825 return 1; /* handled */ 826 } 827 828 static void 829 sssdi_enable_intr(struct sssdi_softc *sc, uint32_t i) 830 { 831 uint32_t v = bus_space_read_4(sc->iot, sc->ioh, SDI_INT_MASK); 832 bus_space_write_4(sc->iot, sc->ioh, SDI_INT_MASK, v | i ); 833 } 834 835 void 836 sssdi_disable_intr(struct sssdi_softc *sc, uint32_t i) 837 { 838 uint32_t v = bus_space_read_4(sc->iot, sc->ioh, SDI_INT_MASK); 839 bus_space_write_4(sc->iot, sc->ioh, SDI_INT_MASK, v & ~i ); 840 } 841 842 void 843 sssdi_clear_intr(struct sssdi_softc *sc) 844 { 845 bus_space_write_4(sc->iot, sc->ioh, SDI_INT_MASK, 0x0); 846 } 847 848 static int 849 sssdi_wait_intr(struct sssdi_softc *sc, uint32_t mask, int timeout) 850 { 851 uint32_t status; 852 853 /* Wait until the command has been sent */ 854 mutex_enter(&sc->intr_mtx); 855 sssdi_enable_intr(sc, mask); 856 status = sc->intr_status & mask; 857 while(status == 0) { 858 859 if (cv_timedwait(&sc->intr_cv, &sc->intr_mtx, timeout) == 860 EWOULDBLOCK ) { 861 DPRINTF(("Timed out waiting for interrupt from SDI controller\n")); 862 status |= SDI_CMD_TIMEOUT; 863 break; 864 } 865 866 status = sc->intr_status & mask; 867 } 868 869 sc->intr_status &= ~status; 870 mutex_exit(&sc->intr_mtx); 871 872 return status; 873 } 874
Indexes created Tue Sep 30 07:10:03 GMT 2025