s3c24x0_clk.c revision 1.12
1 /* $NetBSD: s3c24x0_clk.c,v 1.12 2012/01/30 03:28:33 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Genetec corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corporation may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: s3c24x0_clk.c,v 1.12 2012/01/30 03:28:33 nisimura Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/atomic.h> 39 #include <sys/time.h> 40 #include <sys/timetc.h> 41 42 #include <sys/bus.h> 43 #include <machine/intr.h> 44 #include <arm/cpufunc.h> 45 46 #include <arm/s3c2xx0/s3c24x0reg.h> 47 #include <arm/s3c2xx0/s3c24x0var.h> 48 49 50 #ifndef STATHZ 51 #define STATHZ 64 52 #endif 53 54 #define TIMER_FREQUENCY(pclk) ((pclk)/16) /* divider=1/16 */ 55 56 static unsigned int timer4_reload_value; 57 static unsigned int timer4_prescaler; 58 static unsigned int timer4_mseccount; 59 60 #define usec_to_counter(t) \ 61 ((timer4_mseccount*(t))/1000) 62 63 #define counter_to_usec(c,pclk) \ 64 (((c)*timer4_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000)) 65 66 static u_int s3c24x0_get_timecount(struct timecounter *); 67 68 static struct timecounter s3c24x0_timecounter = { 69 s3c24x0_get_timecount, /* get_timecount */ 70 0, /* no poll_pps */ 71 0xfff, /* counter_mask */ 72 0, /* frequency */ 73 "s3c234x0", /* name */ 74 100, /* quality */ 75 NULL, /* prev */ 76 NULL, /* next */ 77 }; 78 79 static volatile uint32_t s3c24x0_base; 80 81 static u_int 82 s3c24x0_get_timecount(struct timecounter *tc) 83 { 84 struct s3c24x0_softc *sc = (struct s3c24x0_softc *) s3c2xx0_softc; 85 int save, int_pend0, int_pend1, count; 86 87 save = disable_interrupts(I32_bit); 88 89 again: 90 int_pend0 = S3C24X0_INT_TIMER4 & 91 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 92 INTCTL_SRCPND); 93 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh, 94 TIMER_TCNTO(4)); 95 96 for (;;) { 97 98 int_pend1 = S3C24X0_INT_TIMER4 & 99 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 100 INTCTL_SRCPND); 101 if( int_pend0 == int_pend1 ) 102 break; 103 104 /* 105 * Down counter reached to zero while we were reading 106 * timer values. do it again to get consistent values. 107 */ 108 int_pend0 = int_pend1; 109 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh, 110 TIMER_TCNTO(4)); 111 } 112 113 if (__predict_false(count > timer4_reload_value)) { 114 /* 115 * Buggy Hardware Warning --- sometimes timer counter 116 * reads bogus value like 0xffff. I guess it happens when 117 * the timer is reloaded. 118 */ 119 printf("Bogus value from timer counter: %d\n", count); 120 goto again; 121 } 122 123 restore_interrupts(save); 124 125 if (int_pend1) { 126 count -= timer4_reload_value; 127 } 128 129 //printf("delta: %u\n", (s3c24x0_base - count)); 130 return s3c24x0_base - count; 131 } 132 133 static inline int 134 read_timer(struct s3c24x0_softc *sc) 135 { 136 int count; 137 138 do { 139 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh, 140 TIMER_TCNTO(4)); 141 } while ( __predict_false(count > timer4_reload_value) ); 142 143 return count; 144 } 145 146 /* 147 * delay: 148 * 149 * Delay for at least N microseconds. 150 */ 151 void 152 delay(u_int n) 153 { 154 struct s3c24x0_softc *sc = (struct s3c24x0_softc *) s3c2xx0_softc; 155 int v0, v1, delta; 156 u_int ucnt; 157 158 if ( timer4_reload_value == 0 ){ 159 /* not initialized yet */ 160 while ( n-- > 0 ){ 161 int m; 162 163 for (m=0; m<100; ++m ) 164 ; 165 } 166 return; 167 } 168 169 /* read down counter */ 170 v0 = read_timer(sc); 171 172 ucnt = usec_to_counter(n); 173 174 while( ucnt > 0 ) { 175 v1 = read_timer(sc); 176 delta = v0 - v1; 177 if ( delta < 0 ) 178 delta += timer4_reload_value; 179 #ifdef DEBUG 180 if (delta < 0 || delta > timer4_reload_value) 181 panic("wrong value from timer counter"); 182 #endif 183 184 if((u_int)delta < ucnt){ 185 ucnt -= (u_int)delta; 186 v0 = v1; 187 } 188 else { 189 ucnt = 0; 190 } 191 } 192 /*NOTREACHED*/ 193 } 194 195 void 196 setstatclockrate(int newhz) 197 { 198 } 199 200 static int 201 hardintr(void *arg) 202 { 203 atomic_add_32(&s3c24x0_base, timer4_reload_value); 204 205 hardclock((struct clockframe *)arg); 206 207 return 1; 208 } 209 210 static int 211 statintr(void *arg) 212 { 213 statclock((struct clockframe *)arg); 214 215 return 1; 216 } 217 218 void 219 cpu_initclocks(void) 220 { 221 struct s3c24x0_softc *sc = (struct s3c24x0_softc *)s3c2xx0_softc; 222 long tc; 223 int prescaler, h; 224 int pclk = s3c2xx0_softc->sc_pclk; 225 bus_space_tag_t iot = sc->sc_sx.sc_iot; 226 bus_space_handle_t ioh = sc->sc_timer_ioh; 227 uint32_t reg; 228 229 stathz = STATHZ; 230 profhz = stathz; 231 232 #define time_constant(hz) (TIMER_FREQUENCY(pclk) /(hz)/ prescaler) 233 #define calc_time_constant(hz) \ 234 do { \ 235 prescaler = 1; \ 236 do { \ 237 ++prescaler; \ 238 tc = time_constant(hz); \ 239 } while( tc > 65536 ); \ 240 } while(0) 241 242 243 /* Use the channels 4 and 3 for hardclock and statclock, respectively */ 244 245 /* stop all timers */ 246 bus_space_write_4(iot, ioh, TIMER_TCON, 0); 247 248 /* calc suitable prescaler value */ 249 h = MIN(hz,stathz); 250 calc_time_constant(h); 251 252 timer4_prescaler = prescaler; 253 timer4_reload_value = TIMER_FREQUENCY(pclk) / hz / prescaler; 254 timer4_mseccount = TIMER_FREQUENCY(pclk)/timer4_prescaler/1000 ; 255 256 bus_space_write_4(iot, ioh, TIMER_TCNTB(4), 257 /*((prescaler - 1) << 16) |*/ (timer4_reload_value )); 258 259 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n", 260 hz, stathz, pclk, prescaler, tc); 261 262 bus_space_write_4(iot, ioh, TIMER_TCNTB(3), 263 /*((prescaler - 1) << 16) |*/ (time_constant(stathz))); 264 265 s3c24x0_intr_establish(S3C24X0_INT_TIMER4, IPL_CLOCK, 266 IST_NONE, hardintr, 0); 267 s3c24x0_intr_establish(S3C24X0_INT_TIMER3, IPL_HIGH, 268 IST_NONE, statintr, 0); 269 270 /* set prescaler1 */ 271 reg = bus_space_read_4(iot, ioh, TIMER_TCFG0); 272 bus_space_write_4(iot, ioh, TIMER_TCFG0, 273 (reg & ~0xff00) | ((prescaler-1) << 8)); 274 275 /* divider 1/16 for ch #3 and #4 */ 276 reg = bus_space_read_4(iot, ioh, TIMER_TCFG1); 277 bus_space_write_4(iot, ioh, TIMER_TCFG1, 278 (reg & ~(TCFG1_MUX_MASK(3)|TCFG1_MUX_MASK(4))) | 279 (TCFG1_MUX_DIV16 << TCFG1_MUX_SHIFT(3)) | 280 (TCFG1_MUX_DIV16 << TCFG1_MUX_SHIFT(4)) ); 281 282 283 /* start timers */ 284 reg = bus_space_read_4(iot, ioh, TIMER_TCON); 285 reg &= ~(TCON_MASK(3)|TCON_MASK(4)); 286 287 s3c24x0_base = timer4_reload_value; 288 289 /* load the time constant */ 290 bus_space_write_4(iot, ioh, TIMER_TCON, reg | 291 TCON_MANUALUPDATE(3) | TCON_MANUALUPDATE(4)); 292 /* set auto reload and start */ 293 bus_space_write_4(iot, ioh, TIMER_TCON, reg | 294 TCON_AUTORELOAD(3) | TCON_START(3) | 295 TCON_AUTORELOAD(4) | TCON_START(4) ); 296 297 s3c24x0_timecounter.tc_frequency = TIMER_FREQUENCY(pclk) / timer4_prescaler; 298 tc_init(&s3c24x0_timecounter); 299 } 300 301 302 #if 0 303 /* test routine for delay() */ 304 305 void delay_test(void); 306 void 307 delay_test(void) 308 { 309 struct s3c2xx0_softc *sc = s3c2xx0_softc; 310 volatile int *pdatc = (volatile int *) 311 ((char *)bus_space_vaddr(sc->sc_iot, sc->sc_gpio_ioh) + GPIO_PDATC); 312 static const int d[] = {0, 1, 5, 10, 50, 100, 500, 1000, -1}; 313 int i; 314 int v = *pdatc & ~0x07; 315 316 for (;;) { 317 *pdatc = v | 2; 318 319 for (i=0; d[i] >= 0; ++i) { 320 *pdatc = v | 3; 321 delay(d[i]); 322 *pdatc = v | 2; 323 } 324 *pdatc = v; 325 } 326 } 327 #endif 328 329
Indexes created Wed Oct 01 15:09:59 GMT 2025