s3c24x0_lcd.c revision 1.10
1 /* $NetBSD: s3c24x0_lcd.c,v 1.10 2012/10/27 17:17:40 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec Corporation may not be used to endorse or 16 * promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Support S3C24[10]0's integrated LCD controller. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: s3c24x0_lcd.c,v 1.10 2012/10/27 17:17:40 chs Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/conf.h> 42 #include <sys/uio.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> /* for cold */ 45 46 #include <uvm/uvm_extern.h> 47 48 #include <dev/cons.h> 49 #include <dev/wscons/wsconsio.h> 50 #include <dev/wscons/wsdisplayvar.h> 51 #include <dev/wscons/wscons_callbacks.h> 52 #include <dev/rasops/rasops.h> 53 #include <dev/wsfont/wsfont.h> 54 55 #include <dev/hpc/hpcfbio.h> 56 57 #include <sys/bus.h> 58 #include <machine/cpu.h> 59 #include <arm/cpufunc.h> 60 61 #include <arm/s3c2xx0/s3c24x0var.h> 62 #include <arm/s3c2xx0/s3c24x0reg.h> 63 #include <arm/s3c2xx0/s3c24x0_lcd.h> 64 65 #include "wsdisplay.h" 66 67 int lcdintr(void *); 68 static void init_palette(struct s3c24x0_lcd_softc *, 69 struct s3c24x0_lcd_screen *); 70 71 #ifdef LCD_DEBUG 72 static void 73 dump_lcdcon(const char *title, bus_space_tag_t iot, bus_space_handle_t ioh) 74 { 75 int i; 76 77 printf("%s\n", title); 78 for(i=LCDC_LCDCON1; i <= LCDC_LCDSADDR3; i+=4) { 79 if (i%16 == 0) 80 printf("\n%03x: ", i); 81 printf("%08x ", bus_space_read_4(iot, ioh, i)); 82 } 83 84 printf("\n"); 85 } 86 87 void draw_test_pattern(struct s3c24x0_lcd_softc *, 88 struct s3c24x0_lcd_screen *scr); 89 90 #endif 91 92 void 93 s3c24x0_set_lcd_panel_info(struct s3c24x0_lcd_softc *sc, 94 const struct s3c24x0_lcd_panel_info *info) 95 { 96 bus_space_tag_t iot = sc->iot; 97 bus_space_handle_t ioh = sc->ioh; 98 uint32_t reg; 99 int clkval; 100 int tft = s3c24x0_lcd_panel_tft(info); 101 int hclk = s3c2xx0_softc->sc_hclk; 102 103 sc->panel_info = info; 104 105 /* Set LCDCON1. BPPMODE and ENVID are set later */ 106 if (tft) 107 clkval = (hclk / info->pixel_clock / 2) - 1; 108 else { 109 /* STN display */ 110 clkval = max(2, hclk / info->pixel_clock / 2); 111 } 112 113 reg = (info->lcdcon1 & ~LCDCON1_CLKVAL_MASK) | 114 (clkval << LCDCON1_CLKVAL_SHIFT); 115 reg &= ~LCDCON1_ENVID; 116 bus_space_write_4(iot, ioh, LCDC_LCDCON1, reg); 117 118 #if 0 119 printf("hclk=%d pixel clock=%d, clkval = %x lcdcon1=%x\n", 120 hclk, info->pixel_clock, clkval, reg); 121 #endif 122 123 bus_space_write_4(iot, ioh, LCDC_LCDCON2, info->lcdcon2); 124 bus_space_write_4(iot, ioh, LCDC_LCDCON3, info->lcdcon3); 125 bus_space_write_4(iot, ioh, LCDC_LCDCON4, info->lcdcon4); 126 bus_space_write_4(iot, ioh, LCDC_LCDCON5, info->lcdcon5); 127 bus_space_write_4(iot, ioh, LCDC_LPCSEL, info->lpcsel); 128 } 129 130 void 131 s3c24x0_lcd_attach_sub(struct s3c24x0_lcd_softc *sc, 132 struct s3c2xx0_attach_args *sa, 133 const struct s3c24x0_lcd_panel_info *panel_info) 134 { 135 bus_space_tag_t iot = sa->sa_iot; 136 bus_space_handle_t ioh; 137 int error; 138 139 sc->n_screens = 0; 140 LIST_INIT(&sc->screens); 141 142 /* map controller registers */ 143 error = bus_space_map(iot, sa->sa_addr, S3C24X0_LCDC_SIZE, 0, &ioh); 144 if (error) { 145 printf(": failed to map registers %d", error); 146 return; 147 } 148 149 sc->iot = iot; 150 sc->ioh = ioh; 151 sc->dma_tag = sa->sa_dmat; 152 153 #ifdef notyet 154 sc->ih = s3c24x0_intr_establish(sa->sa_intr, IPL_BIO, lcdintr, sc); 155 if (sc->ih == NULL) 156 printf("%s: unable to establish interrupt at irq %d", 157 device_xname(sc->dev), sa->sa_intr); 158 #endif 159 160 /* mask LCD interrupts */ 161 bus_space_write_4(iot, ioh, LCDC_LCDINTMSK, LCDINT_FICNT|LCDINT_FRSYN); 162 163 /* Initialize controller registers based on panel geometry*/ 164 s3c24x0_set_lcd_panel_info(sc, panel_info); 165 166 /* XXX: enable clock to LCD controller */ 167 } 168 169 170 #ifdef notyet 171 int 172 lcdintr(void *arg) 173 { 174 struct s3c24x0_lcd_softc *sc = arg; 175 bus_space_tag_t iot = sc->iot; 176 bus_space_handle_t ioh = sc->ioh; 177 178 static uint32_t status; 179 180 return 1; 181 } 182 #endif 183 184 int 185 s3c24x0_lcd_start_dma(struct s3c24x0_lcd_softc *sc, 186 struct s3c24x0_lcd_screen *scr) 187 { 188 bus_space_tag_t iot = sc->iot; 189 bus_space_handle_t ioh = sc->ioh; 190 const struct s3c24x0_lcd_panel_info *info = sc->panel_info; 191 int tft = s3c24x0_lcd_panel_tft(info); 192 int dual_panel = 193 (info->lcdcon1 & LCDCON1_PNRMODE_MASK) == LCDCON1_PNRMODE_DUALSTN4; 194 uint32_t lcdcon1, val; 195 paddr_t pa; 196 int depth = scr->depth; 197 int stride = scr->stride; 198 int panel_height = info->panel_height; 199 int panel_width = info->panel_width; 200 int offsize; 201 202 switch (depth) { 203 case 1: val = LCDCON1_BPPMODE_STN1; break; 204 case 2: val = LCDCON1_BPPMODE_STN2; break; 205 case 4: val = LCDCON1_BPPMODE_STN4; break; 206 case 8: val = LCDCON1_BPPMODE_STN8; break; 207 case 12: 208 if (tft) 209 return -1; 210 val = LCDCON1_BPPMODE_STN12; 211 break; 212 case 16: 213 if (!tft) 214 return -1; 215 val = LCDCON1_BPPMODE_TFT16; 216 break; 217 case 24: 218 if (!tft) 219 return -1; 220 val = LCDCON1_BPPMODE_TFT24; 221 break; 222 default: 223 return -1; 224 } 225 226 if (tft) 227 val |= LCDCON1_BPPMODE_TFTX; 228 229 lcdcon1 = bus_space_read_4(iot, ioh, LCDC_LCDCON1); 230 lcdcon1 &= ~(LCDCON1_BPPMODE_MASK|LCDCON1_ENVID); 231 lcdcon1 |= val; 232 bus_space_write_4(iot, ioh, LCDC_LCDCON1, lcdcon1); 233 234 /* Adjust LCDCON3.HOZVAL to meet with restriction */ 235 val = roundup(panel_width, 16 / depth); 236 bus_space_write_4(iot, ioh, LCDC_LCDCON3, 237 (info->lcdcon3 & ~LCDCON3_HOZVAL_MASK) | 238 (val - 1) << LCDCON3_HOZVAL_SHIFT); 239 240 pa = scr->segs[0].ds_addr; 241 bus_space_write_4(iot, ioh, LCDC_LCDSADDR1, pa >> 1); 242 243 if (dual_panel) { 244 /* XXX */ 245 } 246 else { 247 pa += stride * panel_height; 248 bus_space_write_4(iot, ioh, LCDC_LCDSADDR2, pa >> 1); 249 } 250 251 offsize = stride / sizeof (uint16_t) - (panel_width * depth / 16); 252 bus_space_write_4(iot, ioh, LCDC_LCDSADDR3, 253 (offsize << LCDSADDR3_OFFSIZE_SHIFT) | 254 (panel_width * depth / 16)); 255 256 /* set byte- or halfword- swap based on the depth */ 257 val = bus_space_read_4(iot, ioh, LCDC_LCDCON5); 258 val &= ~(LCDCON5_BSWP|LCDCON5_HWSWP); 259 switch(depth) { 260 case 2: 261 case 4: 262 case 8: 263 val |= LCDCON5_BSWP; 264 break; 265 case 16: 266 val |= LCDCON5_HWSWP; 267 break; 268 } 269 bus_space_write_4(iot, ioh, LCDC_LCDCON5, val); 270 271 272 init_palette(sc, scr); 273 274 #if 0 275 bus_space_write_4(iot, ioh, LCDC_TPAL, TPAL_TPALEN| 276 (0xff<<TPAL_BLUE_SHIFT)); 277 #endif 278 279 /* Enable LCDC */ 280 bus_space_write_4(iot, ioh, LCDC_LCDCON1, lcdcon1 | LCDCON1_ENVID); 281 282 sc->lcd_on = 1; 283 284 #ifdef LCD_DEBUG 285 dump_lcdcon(__func__, iot, ioh); 286 #endif 287 288 return 0; 289 } 290 291 void 292 s3c24x0_lcd_power(struct s3c24x0_lcd_softc *sc, int on) 293 { 294 bus_space_tag_t iot = sc->iot; 295 bus_space_handle_t ioh = sc->ioh; 296 uint32_t reg; 297 298 reg = bus_space_read_4(iot, ioh, LCDC_LCDCON5); 299 300 if (on) 301 reg |= LCDCON5_PWREN; 302 else 303 reg &= ~LCDCON5_PWREN; 304 305 bus_space_write_4(iot, ioh, LCDC_LCDCON5, reg); 306 } 307 308 struct s3c24x0_lcd_screen * 309 s3c24x0_lcd_new_screen(struct s3c24x0_lcd_softc *sc, 310 int virtual_width, int virtual_height, int depth) 311 { 312 struct s3c24x0_lcd_screen *scr = NULL; 313 int width, height; 314 bus_size_t size; 315 int error, pallet_size; 316 int busdma_flag = (cold ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 317 BUS_DMA_WRITE; 318 paddr_t align; 319 const struct s3c24x0_lcd_panel_info *panel_info = sc->panel_info; 320 321 322 #if 0 /* Does this make any sense? */ 323 #ifdef DIAGNOSTIC 324 if (size > 1 << 22) { 325 aprint_error_dev(sc->dev, "too big screen size\n"); 326 return NULL; 327 } 328 #endif 329 #endif 330 331 width = panel_info->panel_width; 332 height = panel_info->panel_height; 333 pallet_size = 0; 334 335 switch (depth) { 336 case 1: case 2: case 4: case 8: 337 virtual_width = roundup(virtual_width, 16 / depth); 338 break; 339 case 16: 340 break; 341 case 12: case 24: 342 default: 343 aprint_error("%s: Unknown depth (%d)\n", 344 device_xname(sc->sc_dev), depth); 345 return NULL; 346 } 347 348 scr = malloc(sizeof *scr, M_DEVBUF, 349 M_ZERO | (cold ? M_NOWAIT : M_WAITOK)); 350 351 if (scr == NULL) 352 return NULL; 353 354 scr->nsegs = 0; 355 scr->depth = depth; 356 scr->stride = virtual_width * depth / 8; 357 scr->buf_size = size = scr->stride * virtual_height; 358 scr->buf_va = NULL; 359 360 /* calculate the alignment for LCD frame buffer. 361 the buffer can't across 4MB boundary */ 362 align = 1 << 20; 363 while (align < size) 364 align <<= 1; 365 366 printf("%s: Allocating LCD frame buffer of size %ld\n", 367 device_xname(sc->sc_dev), size); 368 369 error = bus_dmamem_alloc(sc->dma_tag, size, align, 0, 370 scr->segs, 1, &(scr->nsegs), busdma_flag); 371 372 if (error || scr->nsegs != 1) 373 goto bad; 374 375 error = bus_dmamem_map(sc->dma_tag, scr->segs, scr->nsegs, 376 size, (void **)&(scr->buf_va), busdma_flag | BUS_DMA_COHERENT); 377 if (error) 378 goto bad; 379 380 381 memset (scr->buf_va, 0, scr->buf_size); 382 383 /* map memory for DMA */ 384 if (bus_dmamap_create(sc->dma_tag, 1024*1024*2, 1, 385 1024*1024*2, 0, busdma_flag, &scr->dma)) 386 goto bad; 387 error = bus_dmamap_load(sc->dma_tag, scr->dma, 388 scr->buf_va, size, NULL, busdma_flag); 389 if (error) 390 goto bad; 391 392 LIST_INSERT_HEAD(&(sc->screens), scr, link); 393 sc->n_screens++; 394 395 #ifdef LCD_DEBUG 396 draw_test_pattern(sc, scr); 397 dump_lcdcon(__func__, sc->iot, sc->ioh); 398 #endif 399 return scr; 400 401 bad: 402 if (scr) { 403 if (scr->buf_va) 404 bus_dmamem_unmap(sc->dma_tag, scr->buf_va, size); 405 if (scr->nsegs) 406 bus_dmamem_free(sc->dma_tag, scr->segs, scr->nsegs); 407 free(scr, M_DEVBUF); 408 } 409 return NULL; 410 } 411 412 413 #define _rgb(r,g,b) (((r)<<11) | ((g)<<5) | b) 414 #define rgb(r,g,b) _rgb((r)>>1,g,(b)>>1) 415 416 #define L 0x30 /* low intensity */ 417 #define H 0x3f /* hight intensity */ 418 419 static const uint16_t basic_color_map[] = { 420 rgb( 0, 0, 0), /* black */ 421 rgb( L, 0, 0), /* red */ 422 rgb( 0, L, 0), /* green */ 423 rgb( L, L, 0), /* brown */ 424 rgb( 0, 0, L), /* blue */ 425 rgb( L, 0, L), /* magenta */ 426 rgb( 0, L, L), /* cyan */ 427 _rgb(0x1c,0x38,0x1c), /* white */ 428 429 rgb( L, L, L), /* black */ 430 rgb( H, 0, 0), /* red */ 431 rgb( 0, H, 0), /* green */ 432 rgb( H, H, 0), /* brown */ 433 rgb( 0, 0, H), /* blue */ 434 rgb( H, 0, H), /* magenta */ 435 rgb( 0, H, H), /* cyan */ 436 rgb( H, H, H), /* white */ 437 }; 438 439 #define COLORMAP_LEN (sizeof basic_color_map / sizeof basic_color_map[0]) 440 441 #undef H 442 #undef L 443 444 static void 445 init_palette(struct s3c24x0_lcd_softc *sc, struct s3c24x0_lcd_screen *scr) 446 { 447 int depth = scr->depth; 448 bus_space_tag_t iot = sc->iot; 449 bus_space_handle_t ioh = sc->ioh; 450 int i; 451 452 i = 0; 453 454 switch(depth) { 455 default: 456 case 16: /* not using palette */ 457 return; 458 case 8: 459 while (i < COLORMAP_LEN) { 460 bus_space_write_4(iot, ioh, LCDC_PALETTE + 4*i, 461 basic_color_map[i]); 462 ++i; 463 } 464 break; 465 case 4: 466 case 2: 467 /* XXX */ 468 break; 469 case 1: 470 bus_space_write_4(iot, ioh, LCDC_PALETTE + 4 * i, 471 basic_color_map[i]); /* black */ 472 ++i; 473 bus_space_write_4(iot, ioh, LCDC_PALETTE + 4 * i, 474 basic_color_map[7]); /* white */ 475 break; 476 } 477 478 #ifdef DIAGNOSTIC 479 /* Fill unused entries */ 480 for ( ; i < 256; ++i ) 481 bus_space_write_4(iot, ioh, LCDC_PALETTE + 4 * i, 482 basic_color_map[1]); /* red */ 483 #endif 484 } 485 486 487 #if NWSDISPLAY > 0 488 489 static void 490 s3c24x0_lcd_stop_dma(struct s3c24x0_lcd_softc *sc) 491 { 492 /* Stop LCD output */ 493 bus_space_write_4(sc->iot, sc->ioh, LCDC_LCDCON1, 494 ~LCDCON1_ENVID & 495 bus_space_read_4(sc->iot, sc->ioh, LCDC_LCDCON1)); 496 497 498 sc->lcd_on = 0; 499 } 500 501 int 502 s3c24x0_lcd_show_screen(void *v, void *cookie, int waitok, 503 void (*cb)(void *, int, int), void *cbarg) 504 { 505 struct s3c24x0_lcd_softc *sc = v; 506 struct s3c24x0_lcd_screen *scr = cookie, *old; 507 508 /* XXX: make sure the clock is provided for LCD controller */ 509 510 old = sc->active; 511 if (old == scr && sc->lcd_on) 512 return 0; 513 514 if (old) 515 s3c24x0_lcd_stop_dma(sc); 516 517 s3c24x0_lcd_start_dma(sc, scr); 518 sc->active = scr; 519 s3c24x0_lcd_power(sc, 1); 520 521 /* XXX: callback */ 522 523 return 0; 524 } 525 526 int 527 s3c24x0_lcd_alloc_screen(void *v, const struct wsscreen_descr *_type, 528 void **cookiep, int *curxp, int *curyp, long *attrp) 529 { 530 struct s3c24x0_lcd_softc *sc = v; 531 struct s3c24x0_lcd_screen *scr; 532 const struct s3c24x0_wsscreen_descr *type = 533 (const struct s3c24x0_wsscreen_descr *)_type; 534 535 int width, height; 536 537 width = type->c.ncols * type->c.fontwidth; 538 height = type->c.nrows * type->c.fontwidth; 539 540 if (width < sc->panel_info->panel_width) 541 width = sc->panel_info->panel_width; 542 if (height < sc->panel_info->panel_height) 543 height = sc->panel_info->panel_height; 544 545 546 scr = s3c24x0_lcd_new_screen(sc, width, height, type->depth); 547 if (scr == NULL) 548 return -1; 549 550 /* 551 * initialize raster operation for this screen. 552 */ 553 scr->rinfo.ri_flg = 0; 554 scr->rinfo.ri_depth = type->depth; 555 scr->rinfo.ri_bits = scr->buf_va; 556 scr->rinfo.ri_width = width; 557 scr->rinfo.ri_height = height; 558 scr->rinfo.ri_stride = scr->stride; 559 560 if (type->c.fontwidth || type->c.fontheight) { 561 /* 562 * find a font with specified size 563 */ 564 int cookie; 565 566 wsfont_init(); 567 568 cookie = wsfont_find(NULL, type->c.fontwidth, 569 type->c.fontheight, 0, WSDISPLAY_FONTORDER_L2R, 570 WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP); 571 572 if (cookie > 0) { 573 if (wsfont_lock(cookie, &scr->rinfo.ri_font)) 574 scr->rinfo.ri_wsfcookie = cookie; 575 } 576 } 577 578 rasops_init(&scr->rinfo, type->c.nrows, type->c.ncols); 579 580 (* scr->rinfo.ri_ops.allocattr)(&scr->rinfo, 0, 0, 0, attrp); 581 582 if (type->c.nrows != scr->rinfo.ri_rows || 583 type->c.ncols != scr->rinfo.ri_cols) { 584 585 aprint_error("%s: can't allocate a screen with requested size:" 586 "%d x %d -> %d x %d\n", 587 device_xname(sc->sc_dev), 588 type->c.ncols, type->c.nrows, 589 scr->rinfo.ri_cols, scr->rinfo.ri_rows); 590 } 591 592 *cookiep = scr; 593 *curxp = 0; 594 *curyp = 0; 595 596 return 0; 597 } 598 599 600 void 601 s3c24x0_lcd_free_screen(void *v, void *cookie) 602 { 603 struct s3c24x0_lcd_softc *sc = v; 604 struct s3c24x0_lcd_screen *scr = cookie; 605 606 LIST_REMOVE(scr, link); 607 sc->n_screens--; 608 if (scr == sc->active) { 609 sc->active = NULL; 610 611 /* XXX: We need a good procedure to shutdown the LCD. */ 612 613 s3c24x0_lcd_stop_dma(sc); 614 s3c24x0_lcd_power(sc, 0); 615 } 616 617 if (scr->buf_va) 618 bus_dmamem_unmap(sc->dma_tag, scr->buf_va, scr->map_size); 619 620 if (scr->nsegs > 0) 621 bus_dmamem_free(sc->dma_tag, scr->segs, scr->nsegs); 622 623 free(scr, M_DEVBUF); 624 } 625 626 int 627 s3c24x0_lcd_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 628 struct lwp *l) 629 { 630 struct s3c24x0_lcd_softc *sc = v; 631 struct wsdisplay_fbinfo *wsdisp_info; 632 struct s3c24x0_lcd_screen *scr; 633 634 635 switch (cmd) { 636 case WSDISPLAYIO_GTYPE: 637 *(u_int *)data = WSDISPLAY_TYPE_UNKNOWN; /* XXX */ 638 return 0; 639 640 case WSDISPLAYIO_GINFO: 641 wsdisp_info = (struct wsdisplay_fbinfo *)data; 642 643 wsdisp_info->height = sc->panel_info->panel_height; 644 wsdisp_info->width = sc->panel_info->panel_width; 645 wsdisp_info->depth = 16; /* XXX */ 646 wsdisp_info->cmsize = 0; 647 return 0; 648 649 case WSDISPLAYIO_LINEBYTES: 650 *(u_int *)data = sc->panel_info->panel_width * (16/8); 651 return 0; 652 653 case WSDISPLAYIO_GETCMAP: 654 case WSDISPLAYIO_PUTCMAP: 655 return EPASSTHROUGH; /* XXX Colormap */ 656 657 case WSDISPLAYIO_SVIDEO: 658 if (*(int *)data == WSDISPLAYIO_VIDEO_ON) { 659 scr = sc->active; 660 if (scr == NULL) 661 scr = LIST_FIRST(&sc->screens); 662 663 if (scr == NULL) 664 return ENXIO; 665 666 s3c24x0_lcd_show_screen(sc, scr, 1, NULL, NULL); 667 } 668 else { 669 s3c24x0_lcd_stop_dma(sc); 670 s3c24x0_lcd_power(sc, 0); 671 } 672 return 0; 673 674 case WSDISPLAYIO_GVIDEO: 675 *(u_int *)data = sc->lcd_on; 676 return 0; 677 678 /* XXX: Hack to support /usr/sbin/tpctl */ 679 case HPCFBIO_GCONF: 680 { 681 struct hpcfb_fbconf *fbconf = (struct hpcfb_fbconf*)data; 682 if (fbconf->hf_conf_index != 0 && 683 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) 684 return EINVAL; 685 686 fbconf->hf_nconfs = 1; 687 fbconf->hf_class = HPCFB_CLASS_RGBCOLOR; 688 strncpy(fbconf->hf_name, "S3C24X0 LCD", HPCFB_MAXNAMELEN); 689 strncpy(fbconf->hf_conf_name, "default", HPCFB_MAXNAMELEN); 690 fbconf->hf_height = sc->panel_info->panel_height; 691 fbconf->hf_width = sc->panel_info->panel_width; 692 fbconf->hf_baseaddr = 0x0; 693 fbconf->hf_offset = 0x0; 694 fbconf->hf_bytes_per_line = sc->panel_info->panel_width * (16/8); 695 fbconf->hf_nplanes = 0; 696 fbconf->hf_bytes_per_plane = 0; 697 fbconf->hf_pack_width = 16; 698 fbconf->hf_pixels_per_pack = 1; 699 fbconf->hf_pixel_width = 16; 700 701 fbconf->hf_access_flags = 0; 702 fbconf->hf_order_flags = HPCFB_REVORDER_WORD; 703 fbconf->hf_reg_offset = 0x0; 704 705 fbconf->hf_u.hf_rgb.hf_red_width = 5; 706 fbconf->hf_u.hf_rgb.hf_red_shift = 11; 707 fbconf->hf_u.hf_rgb.hf_green_width = 6; 708 fbconf->hf_u.hf_rgb.hf_green_shift = 5; 709 fbconf->hf_u.hf_rgb.hf_blue_width = 5; 710 fbconf->hf_u.hf_rgb.hf_blue_shift = 0; 711 712 fbconf->hf_ext_size = 0; 713 fbconf->hf_ext_data = NULL; 714 715 return 0; 716 } 717 718 case WSDISPLAYIO_GCURPOS: 719 case WSDISPLAYIO_SCURPOS: 720 case WSDISPLAYIO_GCURMAX: 721 case WSDISPLAYIO_GCURSOR: 722 case WSDISPLAYIO_SCURSOR: 723 return EPASSTHROUGH; /* XXX */ 724 } 725 726 return EPASSTHROUGH; 727 } 728 729 paddr_t 730 s3c24x0_lcd_mmap(void *v, void *vs, off_t offset, int prot) 731 { 732 struct s3c24x0_lcd_softc *sc = v; 733 struct s3c24x0_lcd_screen *screen = sc->active; /* ??? */ 734 paddr_t ret; 735 736 /* printf("s3c24x0_lcd_mmap: screen: %p, offset: %ld\n", screen, (long)offset);*/ 737 738 if (screen == NULL) 739 return -1; 740 741 ret = bus_dmamem_mmap(sc->dma_tag, screen->segs, screen->nsegs, 742 offset, prot, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 743 /* printf("s3c24x0_lcd_mmap: ret: %lx\n", ret);*/ 744 return ret; 745 return -1; 746 } 747 748 749 static void 750 s3c24x0_lcd_cursor(void *cookie, int on, int row, int col) 751 { 752 struct s3c24x0_lcd_screen *scr = cookie; 753 754 (* scr->rinfo.ri_ops.cursor)(&scr->rinfo, on, row, col); 755 } 756 757 static int 758 s3c24x0_lcd_mapchar(void *cookie, int c, unsigned int *cp) 759 { 760 struct s3c24x0_lcd_screen *scr = cookie; 761 762 return (* scr->rinfo.ri_ops.mapchar)(&scr->rinfo, c, cp); 763 } 764 765 static void 766 s3c24x0_lcd_putchar(void *cookie, int row, int col, u_int uc, long attr) 767 { 768 struct s3c24x0_lcd_screen *scr = cookie; 769 770 (* scr->rinfo.ri_ops.putchar)(&scr->rinfo, 771 row, col, uc, attr); 772 } 773 774 static void 775 s3c24x0_lcd_copycols(void *cookie, int row, int src, int dst, int num) 776 { 777 struct s3c24x0_lcd_screen *scr = cookie; 778 779 (* scr->rinfo.ri_ops.copycols)(&scr->rinfo, 780 row, src, dst, num); 781 } 782 783 static void 784 s3c24x0_lcd_erasecols(void *cookie, int row, int col, int num, long attr) 785 { 786 struct s3c24x0_lcd_screen *scr = cookie; 787 788 (* scr->rinfo.ri_ops.erasecols)(&scr->rinfo, 789 row, col, num, attr); 790 } 791 792 static void 793 s3c24x0_lcd_copyrows(void *cookie, int src, int dst, int num) 794 { 795 struct s3c24x0_lcd_screen *scr = cookie; 796 797 (* scr->rinfo.ri_ops.copyrows)(&scr->rinfo, 798 src, dst, num); 799 } 800 801 static void 802 s3c24x0_lcd_eraserows(void *cookie, int row, int num, long attr) 803 { 804 struct s3c24x0_lcd_screen *scr = cookie; 805 806 (* scr->rinfo.ri_ops.eraserows)(&scr->rinfo, 807 row, num, attr); 808 } 809 810 static int 811 s3c24x0_lcd_alloc_attr(void *cookie, int fg, int bg, int flg, long *attr) 812 { 813 struct s3c24x0_lcd_screen *scr = cookie; 814 815 return (* scr->rinfo.ri_ops.allocattr)(&scr->rinfo, 816 fg, bg, flg, attr); 817 } 818 819 820 const struct wsdisplay_emulops s3c24x0_lcd_emulops = { 821 s3c24x0_lcd_cursor, 822 s3c24x0_lcd_mapchar, 823 s3c24x0_lcd_putchar, 824 s3c24x0_lcd_copycols, 825 s3c24x0_lcd_erasecols, 826 s3c24x0_lcd_copyrows, 827 s3c24x0_lcd_eraserows, 828 s3c24x0_lcd_alloc_attr 829 }; 830 831 #endif /* NWSDISPLAY > 0 */ 832
Indexes created Thu Oct 02 14:10:14 GMT 2025