s3c24x0reg.h revision 1.2
1 /* $NetBSD: s3c24x0reg.h,v 1.2 2003/08/04 12:19:38 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Genetec corporation All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corporation may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 /* 34 * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU 35 * 36 * Reference: 37 * S3C2410X User's Manual 38 * S3C2400 User's Manual 39 */ 40 #ifndef _ARM_S3C2XX0_S3C24X0REG_H_ 41 #define _ARM_S3C2XX0_S3C24X0REG_H_ 42 43 /* Memory controller */ 44 #define MEMCTL_BWSCON 0x00 /* Bus width and wait status */ 45 #define BWSCON_DW0_SHIFT 1 /* bank0 is odd */ 46 #define BWSCON_BANK_SHIFT(n) (4*(n)) /* for bank 1..7 */ 47 #define BWSCON_DW_MASK 0x03 48 #define BWSCON_DW_8 0 49 #define BWSCON_DW_16 1 50 #define BWSCON_DW_32 2 51 #define BWSCON_WS 0x04 /* WAIT enable for the bank */ 52 #define BWSCON_ST 0x08 /* SRAM use UB/LB for the bank */ 53 54 #define MEMCTL_BANKCON0 0x04 /* Boot ROM control */ 55 #define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */) 56 #define BANKCON_MT_SHIFT 15 57 #define BANKCON_MT_ROM (0<<BANKCON_MT_SHIFT) 58 #define BANKCON_MT_DRAM (3<<BANKCON_MT_SHIFT) 59 #define BANKCON_TACS_SHIFT 13 /* address set-up time to nGCS */ 60 #define BANKCON_TCOS_SHIFT 11 /* CS set-up to nOE */ 61 #define BANKCON_TACC_SHIFT 8 /* CS set-up to nOE */ 62 #define BANKCON_TOCH_SHIFT 6 /* CS hold time from OE */ 63 #define BANKCON_TCAH_SHIFT 4 /* address hold time from OE */ 64 #define BANKCON_TACP_SHIFT 2 /* page mode access cycle */ 65 #define BANKCON_TACP_2 (0<<BANKCON_TACP_SHIFT) 66 #define BANKCON_TACP_3 (1<<BANKCON_TACP_SHIFT) 67 #define BANKCON_TACP_4 (2<<BANKCON_TACP_SHIFT) 68 #define BANKCON_TACP_6 (3<<BANKCON_TACP_SHIFT) 69 #define BANKCON_PMC_4 (1<<0) 70 #define BANKCON_PMC_8 (2<<0) 71 #define BANKCON_PMC_16 (3<<0) 72 #define BANKCON_TRCD_2 (0<<2) /* RAS to CAS delay */ 73 #define BANKCON_TRCD_3 (1<<2) 74 #define BANKCON_TRCD_4 (2<<2) 75 #define BANKCON_SCAN_8 (0<<0) /* Column address number */ 76 #define BANKCON_SCAN_9 (1<<0) 77 #define BANKCON_SCAN_10 (2<<0) 78 #define MEMCTL_REFRESH 0x24 /* DRAM?SDRAM Refresh */ 79 #define REFRESH_REFEN (1<<23) 80 #define REFRESH_TREFMD (1<<22) /* 1=self refresh */ 81 #define REFRESH_TRP_2 (0<<20) 82 #define REFRESH_TRP_3 (1<<20) 83 #define REFRESH_TRP_4 (2<<20) 84 #define REFRESH_TRC_4 (0<<18) 85 #define REFRESH_TRC_5 (1<<18) 86 #define REFRESH_TRC_6 (2<<18) 87 #define REFRESH_TRC_7 (3<<18) 88 #define REFRESH_COUNTER_MASK 0x3ff 89 #define MEMCTL_BANKSIZE 0x28 /* Flexible Bank size */ 90 #define MEMCTL_MRSRB6 0x2c /* SDRAM Mode register */ 91 #define MEMCTL_MRSRB7 0x30 92 #define MRSR_CL_SHIFT 4 /* CAS Latency */ 93 94 /* USB Host controller */ 95 /* XXX */ 96 97 /* Interrupt controller */ 98 #define INTCTL_PRIORITY 0x0c /* IRQ Priority control */ 99 #define INTCTL_INTPND 0x10 /* Interrupt request status */ 100 #define INTCTL_INTOFFSET 0x14 /* Interrupt request source */ 101 102 /* Interrupt source */ 103 #define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410 */ 104 #define S3C24X0_INT_RTC 30 /* RTC alarm */ 105 #define S3C2400_INT_UTXD1 29 /* UART1 Tx INT (2400 only) */ 106 #define S3C2410_INT_SPI1 29 /* SPI 1 (2410 only) */ 107 #define S3C2400_INT_UTXD0 28 /* UART0 Tx INT (2400 only) */ 108 #define S3C2410_INT_UART0 28 /* UART0 (2410 only) */ 109 #define S3C24X0_INT_IIC 27 110 #define S3C24X0_INT_USBH 26 /* USB Host */ 111 #define S3C24X0_INT_USBD 25 /* USB Device */ 112 #define S3C2400_INT_URXD1 24 /* UART1 Rx INT (2400 only) */ 113 #define S3C2400_INT_URXD0 23 /* UART0 Rx INT (2400 only) */ 114 #define S3C2410_INT_UART1 23 /* UART0 (2410 only) */ 115 #define S3C24X0_INT_SPI0 22 /* SPI 0 */ 116 #define S3C2400_INT_MMC 21 117 #define S3C2410_INT_SDI 21 118 #define S3C24X0_INT_DMA3 20 119 #define S3C24X0_INT_DMA2 19 120 #define S3C24X0_INT_DMA1 18 121 #define S3C24X0_INT_DMA0 17 122 #define S3C2410_INT_LCD 16 123 124 #define S3C2400_INT_UERR 15 /* UART 0/1 Error int (2400) */ 125 #define S3C2410_INT_UART2 15 /* UART2 int (2410) */ 126 #define S3C24X0_INT_TIMER4 14 127 #define S3C24X0_INT_TIMER3 13 128 #define S3C24X0_INT_TIMER2 12 129 #define S3C24X0_INT_TIMER1 11 130 #define S3C24X0_INT_TIMER0 10 131 #define S3C24X0_INT_TIMER(n) (10+(n)) /* External interrupt [4:0] */ 132 #define S3C24X0_INT_WDT 9 /* Watch dog timer */ 133 #define S3C24X0_INT_TICK 8 134 #define S3C2410_INT_BFLT 7 /* Battery fault */ 135 #define S3C2410_INT_8_23 5 /* Ext int 8..23 */ 136 #define S3C2410_INT_4_7 4 /* Ext int 8..23 */ 137 #define S3C24X0_INT_EXT(n) (n) /* External interrupt [7:0] for 2400, 138 * [3:0] for 2410 */ 139 /* DMA controller */ 140 /* XXX */ 141 142 /* Clock & power manager */ 143 #define CLKMAN_LOCKTIME 0x00 /* PLL lock time */ 144 #define CLKMAN_MPLLCON 0x04 /* MPLL control */ 145 #define CLKMAN_UPLLCON 0x08 /* UPLL control */ 146 #define PLLCON_MDIV_SHIFT 12 147 #define PLLCON_MDIV_MASK (0xff<<PLLCON_MDIV_SHIFT) 148 #define PLLCON_PDIV_SHIFT 4 149 #define PLLCON_PDIV_MASK (0x3f<<PLLCON_PDIV_SHIFT) 150 #define PLLCON_SDIV_SHIFT 0 151 #define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT) 152 #define CLKMAN_CLKCON 0x0c 153 154 #define CLKMAN_CLKSLOW 0x10 /* slow clock controll */ 155 #define CLKSLOW_UCLK (1<<7) /* 1=UPLL off */ 156 #define CLKSLOW_MPLL (1<<5) /* 1=PLL off */ 157 #define CLKSLOW_SLOW (1<<4) /* 1: Enable SLOW mode */ 158 #define CLKSLOW_VAL_MASK 0x0f /* divider value for slow clock */ 159 160 #define CLKMAN_CLKDIVN 0x14 /* Software reset control */ 161 #define CLKDIVN_HDIVN (1<<1) 162 #define CLKDIVN_PDIVN (1<<0) 163 164 165 /* LCD controller */ 166 /* XXX */ 167 168 /* Timer */ 169 #define TIMER_TCFG0 0x00 /* Timer configuration */ 170 #define TIMER_TCFG1 0x04 171 #define TCFG1_MUX_SHIFT(n) (4*(n)) 172 #define TCFG1_MUX_MASK(n) (0x0f << TCFG1_MUX_SHIFT(n)) 173 #define TCFG1_MUX_DIV2 0 174 #define TCFG1_MUX_DIV4 1 175 #define TCFG1_MUX_DIV8 2 176 #define TCFG1_MUX_DIV16 3 177 #define TCFG1_MUX_EXT 4 178 #define TIMER_TCON 0x08 /* control */ 179 #define TCON_SHIFT(n) (4 * ((n)==0 ? 0 : (n)+1)) 180 #define TCON_START(n) (1 << TCON_SHIFT(n)) 181 #define TCON_MANUALUPDATE(n) (1 << (TCON_SHIFT(n) + 1)) 182 #define TCON_INVERTER(n) (1 << (TCON_SHIFT(n) + 2)) 183 #define __TCON_AUTORELOAD(n) (1 << (TCON_SHIFT(n) + 3)) /* n=0..3 */ 184 #define TCON_AUTORELOAD4 (1<<22) /* stupid hardware design */ 185 #define TCON_AUTORELOAD(n) ((n)==4 ? TCON_AUTORELOAD4 : __TCON_AUTORELOAD(n)) 186 #define TCON_MASK(n) (0x0f << TCON_SHIFT(n)) 187 #define TIMER_TB(n) (0x0c+0x0c*(n)) /* count buffer */ 188 #define TIMER_TCMPB(n) (0x10+0x0c*(n)) /* compare buffer 0 */ 189 #define TIMER_TO(n) (0x14+0x0c*(n)) /* count observation 0 */ 190 191 /* UART */ 192 /* diffs to s3c2800 */ 193 #define UMCON_AFC (1<<4) /* auto flow control */ 194 #define UMSTAT_DCTS (1<<2) /* CTS change */ 195 #define ULCON_IR (1<<6) 196 #define ULCON_PARITY_SHIFT 3 197 198 /* USB device */ 199 /* XXX */ 200 201 /* Watch dog timer */ 202 #define WDT_WTCON 0x00 /* WDT mode */ 203 #define WTCON_PRESCALE_SHIFT 8 204 #define WTCON_PRESCALE (0xff<<WTCON_PRESCALE_SHIFT) 205 #define WTCON_ENABLE (1<<5) 206 #define WTCON_CLKSEL (3<<3) 207 #define WTCON_CLKSEL_16 (0<<3) 208 #define WTCON_CLKSEL_32 (1<<3) 209 #define WTCON_CLKSEL_64 (2<<3) 210 #define WTCON_CLKSEL_128 (3<<3) 211 #define WTCON_ENINT (1<<2) 212 #define WTCON_ENRST (1<<0) 213 214 #define WTCON_WDTSTOP 0 215 216 #define WDT_WTDAT 0x04 /* timer data */ 217 #define WDT_WTCNT 0x08 /* timer count */ 218 219 /* IIC */ /* XXX */ 220 221 /* IIS */ /* XXX */ 222 223 /* RTC */ /* XXX */ 224 225 /* ADC */ /* XXX */ 226 227 /* SPI */ /* XXX */ 228 229 230 231 #endif /* _ARM_S3C2XX0_S3C24X0REG_H_ */ 232
Indexes created Wed Oct 01 19:09:53 GMT 2025