s3c2800.c revision 1.4
1 /* $NetBSD: s3c2800.c,v 1.4 2003/05/13 05:15:08 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 42 #include <machine/cpu.h> 43 #include <machine/bus.h> 44 45 #include <arm/cpufunc.h> 46 #include <arm/mainbus/mainbus.h> 47 #include <arm/s3c2xx0/s3c2800reg.h> 48 #include <arm/s3c2xx0/s3c2800var.h> 49 50 #include "locators.h" 51 #include "opt_cpuoptions.h" 52 53 /* prototypes */ 54 static int s3c2800_match(struct device *, struct cfdata *, void *); 55 static void s3c2800_attach(struct device *, struct device *, void *); 56 static int s3c2800_search(struct device *, struct cfdata *, void *); 57 58 /* attach structures */ 59 CFATTACH_DECL(ssio, sizeof(struct s3c2800_softc), s3c2800_match, s3c2800_attach, 60 NULL, NULL); 61 62 extern struct bus_space s3c2xx0_bs_tag; 63 64 struct s3c2xx0_softc *s3c2xx0_softc; 65 66 static int 67 s3c2800_print(void *aux, const char *name) 68 { 69 struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *) aux; 70 71 if (sa->sa_size) 72 aprint_normal(" addr 0x%lx", sa->sa_addr); 73 if (sa->sa_size > 1) 74 aprint_normal("-0x%lx", sa->sa_addr + sa->sa_size - 1); 75 if (sa->sa_intr != SSIOCF_INTR_DEFAULT) 76 aprint_normal(" intr %d", sa->sa_intr); 77 if (sa->sa_index != SSIOCF_INDEX_DEFAULT) 78 aprint_normal(" unit %d", sa->sa_index); 79 80 return (UNCONF); 81 } 82 83 int 84 s3c2800_match(struct device *parent, struct cfdata *match, void *aux) 85 { 86 return 1; 87 } 88 89 void 90 s3c2800_attach(struct device *parent, struct device *self, void *aux) 91 { 92 struct s3c2800_softc *sc = (struct s3c2800_softc *) self; 93 bus_space_tag_t iot; 94 const char *which_registers; /* for panic message */ 95 96 #define FAIL(which) do { \ 97 which_registers=(which); goto abort; }while(/*CONSTCOND*/0) 98 99 s3c2xx0_softc = &(sc->sc_sx); 100 sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag; 101 102 if (bus_space_map(iot, 103 S3C2800_INTCTL_BASE, S3C2800_INTCTL_SIZE, 104 BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh)) 105 FAIL("intc"); 106 /* tell register addresses to interrupt handler */ 107 s3c2800_intr_init(sc); 108 109 /* Map the GPIO registers */ 110 if (bus_space_map(iot, S3C2800_GPIO_BASE, S3C2800_GPIO_SIZE, 111 0, &sc->sc_sx.sc_gpio_ioh)) 112 FAIL("GPIO"); 113 114 #if 0 115 /* Map the DMA controller registers */ 116 if (bus_space_map(iot, S3C2800_DMAC_BASE, S3C2800_DMAC_SIZE, 117 0, &sc->sc_sx.sc_dmach)) 118 FAIL("DMAC"); 119 #endif 120 121 /* Memory controller */ 122 if (bus_space_map(iot, S3C2800_MEMCTL_BASE, 123 S3C2800_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh)) 124 FAIL("MEMC"); 125 /* Clock manager */ 126 if (bus_space_map(iot, S3C2800_CLKMAN_BASE, 127 S3C2800_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh)) 128 FAIL("CLK"); 129 130 #if 0 131 /* Real time clock */ 132 if (bus_space_map(iot, S3C2800_RTC_BASE, 133 S3C2800_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh)) 134 FAIL("RTC"); 135 #endif 136 137 if (bus_space_map(iot, S3C2800_TIMER0_BASE, 138 S3C2800_TIMER_SIZE, 0, &sc->sc_tmr0_ioh)) 139 FAIL("TIMER0"); 140 141 if (bus_space_map(iot, S3C2800_TIMER1_BASE, 142 S3C2800_TIMER_SIZE, 0, &sc->sc_tmr1_ioh)) 143 FAIL("TIMER1"); 144 145 /* calculate current clock frequency */ 146 s3c2800_clock_freq(sc); 147 printf("fclk %d MHz hclk %d MHz pclk %d MHz\n", 148 sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000, 149 sc->sc_sx.sc_pclk / 1000000); 150 151 printf("\n"); 152 153 /* 154 * Attach devices. 155 */ 156 config_search(s3c2800_search, self, NULL); 157 return; 158 159 abort: 160 panic("%s: unable to map %s registers", 161 self->dv_xname, which_registers); 162 163 #undef FAIL 164 } 165 166 int 167 s3c2800_search(struct device * parent, struct cfdata * cf, void *aux) 168 { 169 struct s3c2800_softc *sc = (struct s3c2800_softc *) parent; 170 struct s3c2xx0_attach_args aa; 171 172 aa.sa_sc = sc; 173 aa.sa_iot = sc->sc_sx.sc_iot; 174 aa.sa_addr = cf->cf_loc[SSIOCF_ADDR]; 175 aa.sa_size = cf->cf_loc[SSIOCF_SIZE]; 176 aa.sa_index = cf->cf_loc[SSIOCF_INDEX]; 177 aa.sa_intr = cf->cf_loc[SSIOCF_INTR]; 178 179 if (config_match(parent, cf, &aa)) 180 config_attach(parent, cf, &aa, s3c2800_print); 181 182 return 0; 183 } 184 185 /* 186 * Issue software reset command. 187 * called with MMU off. 188 */ 189 void 190 s3c2800_softreset(void) 191 { 192 *(volatile unsigned int *)(S3C2800_CLKMAN_BASE + CLKMAN_SWRCON) 193 = SWRCON_SWR; 194 } 195 196 /* 197 * fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register. 198 */ 199 void 200 s3c2800_clock_freq(struct s3c2800_softc *__sc) 201 { 202 int mdiv, pdiv, sdiv; 203 int pllcon, clkcon; 204 struct s3c2xx0_softc *sc = (struct s3c2xx0_softc *)__sc; 205 206 pllcon = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, 207 CLKMAN_PLLCON); 208 clkcon = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, 209 CLKMAN_CLKCON); 210 211 mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; 212 pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT; 213 sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT; 214 215 sc->sc_fclk = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / 216 ((pdiv + 2) * (1 << sdiv)); 217 sc->sc_hclk = sc->sc_fclk; 218 if (clkcon & CLKCON_HCLK) 219 sc->sc_hclk /= 2; 220 sc->sc_pclk = sc->sc_hclk; 221 if (clkcon & CLKCON_PCLK) 222 sc->sc_pclk /= 2; 223 } 224 225
Indexes created Mon Sep 29 21:09:56 GMT 2025