s3c2800_pci.c revision 1.15
1 /* $NetBSD: s3c2800_pci.c,v 1.15 2011/05/17 17:34:48 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * derived from evbarm/ifpga/ifpga_pci.c 35 */ 36 37 /* 38 * Copyright (c) 2001 ARM Ltd 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company may not be used to endorse or promote 50 * products derived from this software without specific prior written 51 * permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * Copyright (c) 1997,1998 Mark Brinicombe. 66 * Copyright (c) 1997,1998 Causality Limited 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by Mark Brinicombe 80 * for the NetBSD Project. 81 * 4. The name of the company nor the name of the author may be used to 82 * endorse or promote products derived from this software without specific 83 * prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 86 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 87 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 88 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 */ 97 98 /* 99 * PCI configuration support for Samsung s3c2800. 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.15 2011/05/17 17:34:48 dyoung Exp $"); 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/kernel.h> 108 #include <sys/device.h> 109 #include <sys/extent.h> 110 #include <sys/malloc.h> 111 112 #include <uvm/uvm_extern.h> 113 114 #include <machine/bus.h> 115 116 #include <arm/s3c2xx0/s3c2800reg.h> 117 #include <arm/s3c2xx0/s3c2800var.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pciconf.h> 121 122 #include "opt_pci.h" 123 #include "pci.h" 124 125 /* 126 * pci tag encoding. 127 * also useful for configuration type 0 address 128 */ 129 #define BUSNO_SHIFT 16 130 #define BUSNO_MASK (0xff<<BUSNO_SHIFT) 131 #define DEVNO_SHIFT 11 132 #define DEVNO_MASK (0x1f<<DEVNO_SHIFT) 133 #define tag_to_devno(tag) (((tag)&DEVNO_MASK)>>DEVNO_SHIFT) 134 #define FUNNO_SHIFT 8 135 #define FUNNO_MASK (0x07<<FUNNO_SHIFT) 136 137 #define BUS0_DEV_MIN 1 138 #define BUS0_DEV_MAX 21 139 140 void s3c2800_pci_attach_hook(struct device *, struct device *, 141 struct pcibus_attach_args *); 142 int s3c2800_pci_bus_maxdevs(void *, int); 143 pcitag_t s3c2800_pci_make_tag(void *, int, int, int); 144 void s3c2800_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 145 pcireg_t s3c2800_pci_conf_read(void *, pcitag_t, int); 146 void s3c2800_pci_conf_write(void *, pcitag_t, int, pcireg_t); 147 int s3c2800_pci_intr_map(const struct pci_attach_args *, 148 pci_intr_handle_t *); 149 const char *s3c2800_pci_intr_string(void *, pci_intr_handle_t); 150 const struct evcnt *s3c2800_pci_intr_evcnt(void *, pci_intr_handle_t); 151 void *s3c2800_pci_intr_establish(void *, pci_intr_handle_t, int, 152 int (*) (void *), void *); 153 void s3c2800_pci_intr_disestablish(void *, void *); 154 155 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 156 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 157 158 struct sspci_irq_handler { 159 int (*func) (void *); 160 void *arg; 161 int level; 162 SLIST_ENTRY(sspci_irq_handler) link; 163 }; 164 165 struct sspci_softc { 166 struct device sc_dev; 167 168 bus_space_tag_t sc_iot; 169 bus_space_handle_t sc_reg_ioh; 170 bus_space_handle_t sc_conf0_ioh; /* config type0 space */ 171 bus_space_handle_t sc_conf1_ioh; /* config type1 space */ 172 173 uint32_t sc_pciinten; /* copy of PCIINTEN register */ 174 175 /* list of interrupt handlers. SLIST is not good for removing 176 * element from it, but intr_disestablish is rarely called */ 177 SLIST_HEAD(, sspci_irq_handler) sc_irq_handlers; 178 179 void *sc_softinterrupt; 180 }; 181 182 static int sspci_match(struct device *, struct cfdata *, void *aux); 183 static void sspci_attach(struct device *, struct device *, void *); 184 185 static int sspci_bs_map(void *, bus_addr_t, bus_size_t, int, 186 bus_space_handle_t *); 187 static int sspci_init_controller(struct sspci_softc *); 188 static int sspci_intr(void *); 189 static void sspci_softintr(void *); 190 191 /* attach structures */ 192 CFATTACH_DECL(sspci, sizeof(struct sspci_softc), sspci_match, sspci_attach, 193 NULL, NULL); 194 195 196 struct arm32_pci_chipset sspci_chipset = { 197 NULL, /* conf_v */ 198 s3c2800_pci_attach_hook, 199 s3c2800_pci_bus_maxdevs, 200 s3c2800_pci_make_tag, 201 s3c2800_pci_decompose_tag, 202 s3c2800_pci_conf_read, 203 s3c2800_pci_conf_write, 204 NULL, /* intr_v */ 205 s3c2800_pci_intr_map, 206 s3c2800_pci_intr_string, 207 s3c2800_pci_intr_evcnt, 208 s3c2800_pci_intr_establish, 209 s3c2800_pci_intr_disestablish 210 }; 211 212 213 /* 214 * bus space tag for PCI IO/Memory access space. 215 * filled in by sspci_attach() 216 */ 217 struct bus_space sspci_io_tag, sspci_mem_tag; 218 219 static int 220 sspci_match(struct device *parent, struct cfdata *match, void *aux) 221 { 222 return 1; 223 } 224 225 static void 226 sspci_attach(struct device *parent, struct device *self, void *aux) 227 { 228 struct sspci_softc *sc = (struct sspci_softc *) self; 229 struct s3c2xx0_attach_args *aa = aux; 230 bus_space_tag_t iot; 231 bus_dma_tag_t pci_dma_tag; 232 const char *error_on; /* for panic message */ 233 #if defined(PCI_NETBSD_CONFIGURE) 234 struct extent *ioext, *memext; 235 struct pcibus_attach_args pci_pba; 236 #endif 237 238 #define FAIL(which) do { \ 239 error_on=(which); goto abort; }while(/*CONSTCOND*/0) 240 241 iot = sc->sc_iot = aa->sa_iot; 242 if (bus_space_map(iot, S3C2800_PCICTL_BASE, 243 S3C2800_PCICTL_SIZE, 0, &sc->sc_reg_ioh)) 244 FAIL("control regs"); 245 246 if (bus_space_map(iot, S3C2800_PCI_CONF0_BASE, 247 S3C2800_PCI_CONF0_SIZE, 0, &sc->sc_conf0_ioh)) 248 FAIL("config type 0 area"); 249 250 #if 0 251 if (bus_space_map(iot, S3C2800_PCI_CONF1_BASE, 252 S3C2800_PCI_CONF1_SIZE, 0, &sc->sc_conf1_ioh)) 253 FAIL("config type 1 area"); 254 #endif 255 printf("\n"); 256 257 SLIST_INIT(&sc->sc_irq_handlers); 258 if (!s3c2800_intr_establish(S3C2800_INT_PCI, IPL_AUDIO, IST_LEVEL, 259 sspci_intr, sc)) 260 FAIL("intr_establish"); 261 262 sc->sc_softinterrupt = softint_establish(SOFTINT_SERIAL, 263 sspci_softintr, sc); 264 if (sc->sc_softinterrupt == NULL) 265 FAIL("softint_establish"); 266 267 #if defined(PCI_NETBSD_CONFIGURE) 268 if (sspci_init_controller(sc)) { 269 printf("%s: failed to initialize controller\n", self->dv_xname); 270 return; 271 } 272 #endif 273 274 sc->sc_pciinten = 275 PCIINT_INA | PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 276 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD; 277 278 bus_space_write_4(iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 279 sc->sc_pciinten); 280 281 { 282 pcireg_t id_reg, class_reg; 283 char buf[1000]; 284 285 id_reg = bus_space_read_4(iot, sc->sc_reg_ioh, 286 PCI_ID_REG); 287 class_reg = bus_space_read_4(iot, 288 sc->sc_reg_ioh, PCI_CLASS_REG); 289 290 pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf)); 291 printf("%s: %s\n", self->dv_xname, buf); 292 } 293 294 #if defined(PCI_NETBSD_CONFIGURE) 295 ioext = extent_create("pciio", 0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100, 296 M_DEVBUF, NULL, 0, EX_NOWAIT); 297 298 memext = extent_create("pcimem", 0, S3C2800_PCI_MEMSPACE_SIZE, 299 M_DEVBUF, NULL, 0, EX_NOWAIT); 300 301 sspci_chipset.pc_conf_v = (void *) sc; 302 sspci_chipset.pc_intr_v = (void *) sc; 303 304 pci_configure_bus(&sspci_chipset, ioext, memext, NULL, 0, 305 arm_dcache_align); 306 307 extent_destroy(memext); 308 extent_destroy(ioext); 309 #endif /* PCI_NETBSD_CONFIGURE */ 310 311 /* initialize bus space tag */ 312 sspci_io_tag = *iot; 313 sspci_io_tag.bs_cookie = (void *) S3C2800_PCI_IOSPACE_BASE; 314 sspci_io_tag.bs_map = sspci_bs_map; 315 sspci_mem_tag = *iot; 316 sspci_mem_tag.bs_cookie = (void *) S3C2800_PCI_MEMSPACE_BASE; 317 sspci_mem_tag.bs_map = sspci_bs_map; 318 319 320 /* Platform provides PCI DMA tag */ 321 pci_dma_tag = s3c2800_pci_dma_init(); 322 323 pci_pba.pba_pc = &sspci_chipset; 324 pci_pba.pba_iot = &sspci_io_tag; 325 pci_pba.pba_memt = &sspci_mem_tag; 326 pci_pba.pba_dmat = pci_dma_tag; 327 pci_pba.pba_dmat64 = NULL; 328 pci_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 329 pci_pba.pba_bus = 0; 330 pci_pba.pba_bridgetag = NULL; 331 332 config_found_ia(self, "pcibus", &pci_pba, pcibusprint); 333 334 return; 335 336 #undef FAIL 337 abort: 338 panic("%s: map failed (%s)", 339 self->dv_xname, error_on); 340 } 341 342 343 static int 344 sspci_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 345 bus_space_handle_t * bshp) 346 { 347 bus_addr_t startpa, endpa; 348 vaddr_t va; 349 350 #ifdef PCI_DEBUG 351 printf("sspci_bs_map: t=%p, addr=%lx, size=%lx, flag=%d\n", 352 t, bpa, size, flag); 353 #endif 354 355 /* Round the allocation to page boundries */ 356 startpa = trunc_page(bpa); 357 endpa = round_page(bpa + size); 358 359 /* Get some VM. */ 360 va = uvm_km_alloc(kernel_map, endpa - startpa, 0, 361 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 362 if (va == 0) 363 return ENOMEM; 364 365 /* Store the bus space handle */ 366 *bshp = va + (bpa & PGOFSET); 367 368 /* Now map the pages */ 369 /* The cookie is the physical base address for PCI I/O or memory area */ 370 while (startpa < endpa) { 371 /* XXX pmap_kenter_pa maps pages cacheable -- not what we 372 * want. */ 373 pmap_enter(pmap_kernel(), va, (bus_addr_t) t + startpa, 374 VM_PROT_READ | VM_PROT_WRITE, 0); 375 va += PAGE_SIZE; 376 startpa += PAGE_SIZE; 377 } 378 pmap_update(pmap_kernel()); 379 380 return 0; 381 } 382 383 384 385 void 386 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int func, 387 int swiz, int *iline) 388 { 389 #ifdef PCI_DEBUG 390 printf("pci_conf_interrupt(pc(%lx), bus(%d), dev(%d), func(%d), swiz(%d), *iline(%p)\n", (unsigned long) pc, bus, dev, func, swiz, iline); 391 #endif 392 if (bus == 0) { 393 *iline = dev; 394 } else { 395 panic("pci_conf_interrupt: bus=%d: not yet implemented", bus); 396 } 397 } 398 399 void 400 s3c2800_pci_attach_hook(struct device * parent, struct device * self, 401 struct pcibus_attach_args * pba) 402 { 403 404 /* Nothing to do. */ 405 #ifdef PCI_DEBUG 406 printf("s3c2800_pci_attach_hook()\n"); 407 #endif 408 } 409 410 int 411 s3c2800_pci_bus_maxdevs(void *v, int busno) 412 { 413 414 #ifdef PCI_DEBUG 415 printf("s3c2800_pci_bus_maxdevs(v=%p, busno=%d)\n", v, busno); 416 #endif 417 return (32); 418 } 419 pcitag_t 420 s3c2800_pci_make_tag(void *v, int bus, int device, int function) 421 { 422 423 return ((bus << BUSNO_SHIFT) | (device << DEVNO_SHIFT) | 424 (function << FUNNO_SHIFT)); 425 } 426 427 void 428 s3c2800_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 429 { 430 if (bp != NULL) 431 *bp = (tag >> BUSNO_SHIFT) & 0xff; 432 if (dp != NULL) 433 *dp = (tag >> DEVNO_SHIFT) & 0x1f; 434 if (fp != NULL) 435 *fp = (tag >> FUNNO_SHIFT) & 0x7; 436 } 437 438 static vaddr_t 439 make_pci_conf_va(struct sspci_softc * sc, pcitag_t tag, int offset) 440 { 441 if ((tag & BUSNO_MASK) == 0) { 442 /* configuration type 0 */ 443 int devno = tag_to_devno(tag); 444 445 if (devno < BUS0_DEV_MIN || BUS0_DEV_MAX < devno) 446 return 0; 447 448 return (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 449 (tag & (DEVNO_MASK | FUNNO_MASK)) + offset; 450 } else { 451 /* XXX */ 452 return (vaddr_t) - 1; /* cause fault */ 453 } 454 } 455 456 457 pcireg_t 458 s3c2800_pci_conf_read(void *v, pcitag_t tag, int offset) 459 { 460 struct sspci_softc *sc = v; 461 vaddr_t va = make_pci_conf_va(sc, tag, offset); 462 int s; 463 pcireg_t rv; 464 465 #ifdef PCI_DEBUG 466 printf("s3c2800_pci_conf_read: base=%lx tag=%lx offset=%x\n", 467 sc->sc_conf0_ioh, tag, offset); 468 #endif 469 if (va == 0) 470 return -1; 471 472 PCI_CONF_LOCK(s); 473 474 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 475 #if PCI_DEBUG 476 printf("conf_read: %lx bad address\n", va); 477 #endif 478 rv = (pcireg_t) - 1; 479 } 480 PCI_CONF_UNLOCK(s); 481 482 return rv; 483 } 484 485 void 486 s3c2800_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 487 { 488 struct sspci_softc *sc = v; 489 vaddr_t va = make_pci_conf_va(sc, tag, offset); 490 u_int s; 491 492 #ifdef PCI_DEBUG 493 printf("s3c2800_pci_conf_write: tag=%lx offset=%x -> va=%lx\n", tag, offset, va); 494 #endif 495 496 PCI_CONF_LOCK(s); 497 498 *(pcireg_t *) va = val; 499 500 PCI_CONF_UNLOCK(s); 501 } 502 503 void * 504 s3c2800_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level, 505 int (*func) (void *), void *arg) 506 { 507 struct sspci_softc *sc = pcv; 508 struct sspci_irq_handler *handler; 509 int s; 510 511 #ifdef PCI_DEBUG 512 printf("s3c2800_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, " 513 "func=%p, arg=%p)\n", pcv, ih, level, func, arg); 514 #endif 515 516 handler = malloc(sizeof *handler, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 517 if (handler == NULL) 518 panic("sspci_intr_establish: can't malloc handler info"); 519 520 handler->func = func; 521 handler->arg = arg; 522 handler->level = level; 523 524 s = splhigh(); 525 SLIST_INSERT_HEAD(&sc->sc_irq_handlers, handler, link); 526 splx(s); 527 528 return (handler); 529 } 530 531 void 532 s3c2800_pci_intr_disestablish(void *pcv, void *cookie) 533 { 534 struct sspci_softc *sc = pcv; 535 struct sspci_irq_handler *ih = cookie; 536 int s; 537 538 #ifdef PCI_DEBUG 539 printf("s3c2800_pci_intr_disestablish(pcv=%p, cookie=%p)\n", 540 pcv, cookie); 541 #endif 542 543 s = splhigh(); 544 SLIST_REMOVE(&sc->sc_irq_handlers, ih, sspci_irq_handler, link); 545 splx(s); 546 } 547 548 int 549 s3c2800_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 550 { 551 #ifdef PCI_DEBUG 552 int pin = pa->pa_intrpin; 553 void *pcv = pa->pa_pc; 554 pcitag_t intrtag = pa->pa_intrtag; 555 int bus, device, function; 556 557 s3c2800_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 558 printf("s3c2800_pci_intr_map: pcv=%p, tag=%08lx pin=%d dev=%d\n", 559 pcv, intrtag, pin, device); 560 #endif 561 562 563 /* S3C2800 has only one interrupt line for PCI */ 564 *ihp = 0; 565 return 0; 566 } 567 568 const char * 569 s3c2800_pci_intr_string(void *pcv, pci_intr_handle_t ih) 570 { 571 /* We have only one interrupt source from PCI */ 572 return "pciint"; 573 } 574 575 const struct evcnt * 576 s3c2800_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih) 577 { 578 579 /* XXX for now, no evcnt parent reported */ 580 return NULL; 581 } 582 /* 583 * Initialize PCI controller 584 */ 585 int 586 sspci_init_controller(struct sspci_softc * sc) 587 { 588 bus_space_tag_t iot = sc->sc_iot; 589 bus_space_handle_t ioh = sc->sc_reg_ioh; 590 591 /* disable PCI command */ 592 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 593 0xffff0000); 594 595 /* latency=0x10, cacheline=8 */ 596 bus_space_write_4(iot, ioh, PCI_BHLC_REG, 597 PCI_BHLC_CODE(0, 0, 0, 0x10, 8)); 598 599 bus_space_write_4(iot, ioh, PCI_INTERRUPT_REG, 600 PCI_INTERRUPT_CODE(0, 0, 0, 0)); 601 602 603 604 #if 1 605 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 606 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 607 /* Cover all DBANKs with BAR0 */ 608 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xf8000000); 609 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, S3C2800_DBANK0_START); 610 #else 611 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 612 PCI_MAPREG_MEM_TYPE_32BIT | 0xf0000000); 613 bus_space_write_4(iot, ioh, PCI_MAPREG_START + 4, 614 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 615 616 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xffff0000); 617 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, 0xffff0000); 618 bus_space_write_4(iot, ioh, PCICTL_PCIBAM1, 0xf1000000); 619 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA1, S3C2800_DBANK0_START); 620 #endif 621 622 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 623 PCI_STATUS_PARITY_DETECT | 624 PCI_STATUS_SPECIAL_ERROR | 625 PCI_STATUS_MASTER_ABORT | 626 PCI_STATUS_MASTER_TARGET_ABORT | 627 PCI_STATUS_TARGET_TARGET_ABORT | 628 PCI_STATUS_DEVSEL_MEDIUM | 629 PCI_STATUS_PARITY_ERROR | 630 PCI_STATUS_BACKTOBACK_SUPPORT | 631 PCI_STATUS_CAPLIST_SUPPORT | 632 PCI_COMMAND_MASTER_ENABLE | 633 PCI_COMMAND_MEM_ENABLE | 634 PCI_COMMAND_IO_ENABLE); 635 636 bus_space_write_4(iot, ioh, PCICTL_PCICON, 637 PCICON_ARB | PCICON_HST); 638 639 bus_space_write_4(iot, ioh, PCICTL_PCISET, 0); 640 /* clear all interrupts */ 641 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, 0xffffffff); 642 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 0); 643 644 bus_space_write_4(iot, ioh, PCICTL_PCICON, 645 PCICON_RDY | PCICON_CFD | PCICON_ATS | 646 PCICON_ARB | PCICON_HST); 647 648 649 #ifdef PCI_DEBUG 650 { 651 pcireg_t reg; 652 int i; 653 654 for (i = 0; i <= 0x40; i += sizeof(pcireg_t)) { 655 reg = bus_space_read_4(iot, ioh, i); 656 printf("%03x: %08x\n", i, reg); 657 } 658 for (i = 0x100; i <= 0x154; i += sizeof(pcireg_t)) { 659 reg = bus_space_read_4(iot, ioh, i); 660 printf("%03x: %08x\n", i, reg); 661 } 662 } 663 #endif 664 return 0; 665 } 666 667 668 static const char *pci_abnormal_error_name[] = { 669 "PCI reset deasserted", 670 "PCI reset asserted", 671 "PCI master detected fatal error", 672 "PCI master detected parity error", 673 "PCI target detected parity error", 674 "PCI SERR# asserted", 675 }; 676 677 static int 678 sspci_intr(void *arg) 679 { 680 struct sspci_softc *sc = arg; 681 int s; 682 bus_space_tag_t iot = sc->sc_iot; 683 bus_space_handle_t ioh = sc->sc_reg_ioh; 684 uint32_t interrupts, errors; 685 686 interrupts = bus_space_read_4(iot, ioh, PCICTL_PCIINTST); 687 688 if (interrupts & PCIINT_INA) { 689 s = splhigh(); 690 softint_schedule(sc->sc_softinterrupt); 691 692 /* mask INTA itnerrupt until softinterrupt is handled */ 693 sc->sc_pciinten &= ~PCIINT_INA; 694 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 695 sc->sc_pciinten); 696 697 /* acknowledge INTA interrupt */ 698 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, PCIINT_INA); 699 700 splx(s); 701 702 interrupts &= ~PCIINT_INA; 703 704 } 705 errors = interrupts & (PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 706 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD); 707 if (errors) { 708 int i; 709 710 for (i = 0; errors; ++i) { 711 if ((errors & (1 << i)) == 0) 712 continue; 713 714 printf("%s: %s\n", sc->sc_dev.dv_xname, 715 pci_abnormal_error_name[i > 4 ? 5 : i]); 716 717 errors &= ~(1 << i); 718 } 719 /* acknowledge interrupts */ 720 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, interrupts); 721 } 722 return 0; 723 } 724 725 static void 726 sspci_softintr(void *arg) 727 { 728 struct sspci_softc *sc = arg; 729 struct sspci_irq_handler *ih; 730 int s; 731 732 733 SLIST_FOREACH(ih, &(sc->sc_irq_handlers), link) { 734 s = _splraise(ih->level); 735 ih->func(ih->arg); 736 splx(s); 737 } 738 739 /* unmask INTA interrupt */ 740 s = splhigh(); 741 sc->sc_pciinten |= PCIINT_INA; 742 bus_space_write_4(sc->sc_iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 743 sc->sc_pciinten); 744 splx(s); 745 } 746
Indexes created Wed Oct 01 13:09:50 GMT 2025