s3c2800_pci.c revision 1.21
1 /* $NetBSD: s3c2800_pci.c,v 1.21 2014/03/29 19:28:26 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * derived from evbarm/ifpga/ifpga_pci.c 35 */ 36 37 /* 38 * Copyright (c) 2001 ARM Ltd 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company may not be used to endorse or promote 50 * products derived from this software without specific prior written 51 * permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * Copyright (c) 1997,1998 Mark Brinicombe. 66 * Copyright (c) 1997,1998 Causality Limited 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by Mark Brinicombe 80 * for the NetBSD Project. 81 * 4. The name of the company nor the name of the author may be used to 82 * endorse or promote products derived from this software without specific 83 * prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 86 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 87 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 88 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 */ 97 98 /* 99 * PCI configuration support for Samsung s3c2800. 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.21 2014/03/29 19:28:26 christos Exp $"); 104 105 #include "opt_pci.h" 106 #include "pci.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/kernel.h> 111 #include <sys/device.h> 112 #include <sys/extent.h> 113 #include <sys/malloc.h> 114 115 #include <uvm/uvm_extern.h> 116 117 #include <sys/bus.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pciconf.h> 122 123 #include <arm/locore.h> 124 125 #include <arm/s3c2xx0/s3c2800reg.h> 126 #include <arm/s3c2xx0/s3c2800var.h> 127 128 /* 129 * pci tag encoding. 130 * also useful for configuration type 0 address 131 */ 132 #define BUSNO_SHIFT 16 133 #define BUSNO_MASK (0xff<<BUSNO_SHIFT) 134 #define DEVNO_SHIFT 11 135 #define DEVNO_MASK (0x1f<<DEVNO_SHIFT) 136 #define tag_to_devno(tag) (((tag)&DEVNO_MASK)>>DEVNO_SHIFT) 137 #define FUNNO_SHIFT 8 138 #define FUNNO_MASK (0x07<<FUNNO_SHIFT) 139 140 #define BUS0_DEV_MIN 1 141 #define BUS0_DEV_MAX 21 142 143 void s3c2800_pci_attach_hook(device_t, device_t, struct pcibus_attach_args *); 144 int s3c2800_pci_bus_maxdevs(void *, int); 145 pcitag_t s3c2800_pci_make_tag(void *, int, int, int); 146 void s3c2800_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 147 pcireg_t s3c2800_pci_conf_read(void *, pcitag_t, int); 148 void s3c2800_pci_conf_write(void *, pcitag_t, int, pcireg_t); 149 void s3c2800_pci_conf_interrupt(void *, int, int, int, int, int *); 150 int s3c2800_pci_intr_map(const struct pci_attach_args *, 151 pci_intr_handle_t *); 152 const char *s3c2800_pci_intr_string(void *, pci_intr_handle_t, char *, size_t); 153 const struct evcnt *s3c2800_pci_intr_evcnt(void *, pci_intr_handle_t); 154 void *s3c2800_pci_intr_establish(void *, pci_intr_handle_t, int, 155 int (*) (void *), void *); 156 void s3c2800_pci_intr_disestablish(void *, void *); 157 158 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 159 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 160 161 struct sspci_irq_handler { 162 int (*func) (void *); 163 void *arg; 164 int level; 165 SLIST_ENTRY(sspci_irq_handler) link; 166 }; 167 168 struct sspci_softc { 169 device_t sc_dev; 170 171 bus_space_tag_t sc_iot; 172 bus_space_handle_t sc_reg_ioh; 173 bus_space_handle_t sc_conf0_ioh; /* config type0 space */ 174 bus_space_handle_t sc_conf1_ioh; /* config type1 space */ 175 176 uint32_t sc_pciinten; /* copy of PCIINTEN register */ 177 178 /* list of interrupt handlers. SLIST is not good for removing 179 * element from it, but intr_disestablish is rarely called */ 180 SLIST_HEAD(, sspci_irq_handler) sc_irq_handlers; 181 182 void *sc_softinterrupt; 183 }; 184 185 static int sspci_match(device_t, cfdata_t, void *aux); 186 static void sspci_attach(device_t, device_t, void *); 187 188 static int sspci_bs_map(void *, bus_addr_t, bus_size_t, int, 189 bus_space_handle_t *); 190 static int sspci_init_controller(struct sspci_softc *); 191 static int sspci_intr(void *); 192 static void sspci_softintr(void *); 193 194 /* attach structures */ 195 CFATTACH_DECL_NEW(sspci, sizeof(struct sspci_softc), sspci_match, sspci_attach, 196 NULL, NULL); 197 198 199 struct arm32_pci_chipset sspci_chipset = { 200 NULL, /* conf_v */ 201 s3c2800_pci_attach_hook, 202 s3c2800_pci_bus_maxdevs, 203 s3c2800_pci_make_tag, 204 s3c2800_pci_decompose_tag, 205 s3c2800_pci_conf_read, 206 s3c2800_pci_conf_write, 207 NULL, /* intr_v */ 208 s3c2800_pci_intr_map, 209 s3c2800_pci_intr_string, 210 s3c2800_pci_intr_evcnt, 211 s3c2800_pci_intr_establish, 212 s3c2800_pci_intr_disestablish, 213 #ifdef __HAVE_PCI_CONF_HOOK 214 NULL, 215 #endif 216 s3c2800_pci_conf_interrupt, 217 }; 218 219 220 /* 221 * bus space tag for PCI IO/Memory access space. 222 * filled in by sspci_attach() 223 */ 224 struct bus_space sspci_io_tag, sspci_mem_tag; 225 226 static int 227 sspci_match(device_t parent, cfdata_t match, void *aux) 228 { 229 return 1; 230 } 231 232 static void 233 sspci_attach(device_t parent, device_t self, void *aux) 234 { 235 struct sspci_softc *sc = device_private(self); 236 struct s3c2xx0_attach_args *aa = aux; 237 bus_space_tag_t iot; 238 bus_dma_tag_t pci_dma_tag; 239 const char *error_on; /* for panic message */ 240 #if defined(PCI_NETBSD_CONFIGURE) 241 struct extent *ioext, *memext; 242 struct pcibus_attach_args pci_pba; 243 #endif 244 245 #define FAIL(which) do { \ 246 error_on=(which); goto abort; }while(/*CONSTCOND*/0) 247 248 sc->sc_dev = self; 249 iot = sc->sc_iot = aa->sa_iot; 250 if (bus_space_map(iot, S3C2800_PCICTL_BASE, 251 S3C2800_PCICTL_SIZE, 0, &sc->sc_reg_ioh)) 252 FAIL("control regs"); 253 254 if (bus_space_map(iot, S3C2800_PCI_CONF0_BASE, 255 S3C2800_PCI_CONF0_SIZE, 0, &sc->sc_conf0_ioh)) 256 FAIL("config type 0 area"); 257 258 #if 0 259 if (bus_space_map(iot, S3C2800_PCI_CONF1_BASE, 260 S3C2800_PCI_CONF1_SIZE, 0, &sc->sc_conf1_ioh)) 261 FAIL("config type 1 area"); 262 #endif 263 printf("\n"); 264 265 SLIST_INIT(&sc->sc_irq_handlers); 266 if (!s3c2800_intr_establish(S3C2800_INT_PCI, IPL_AUDIO, IST_LEVEL, 267 sspci_intr, sc)) 268 FAIL("intr_establish"); 269 270 sc->sc_softinterrupt = softint_establish(SOFTINT_SERIAL, 271 sspci_softintr, sc); 272 if (sc->sc_softinterrupt == NULL) 273 FAIL("softint_establish"); 274 275 #if defined(PCI_NETBSD_CONFIGURE) 276 if (sspci_init_controller(sc)) { 277 printf("%s: failed to initialize controller\n", device_xname(self)); 278 return; 279 } 280 #endif 281 282 sc->sc_pciinten = 283 PCIINT_INA | PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 284 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD; 285 286 bus_space_write_4(iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 287 sc->sc_pciinten); 288 289 { 290 pcireg_t id_reg, class_reg; 291 char buf[1000]; 292 293 id_reg = bus_space_read_4(iot, sc->sc_reg_ioh, 294 PCI_ID_REG); 295 class_reg = bus_space_read_4(iot, 296 sc->sc_reg_ioh, PCI_CLASS_REG); 297 298 pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf)); 299 printf("%s: %s\n", device_xname(self), buf); 300 } 301 302 #if defined(PCI_NETBSD_CONFIGURE) 303 ioext = extent_create("pciio", 0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100, 304 NULL, 0, EX_NOWAIT); 305 306 memext = extent_create("pcimem", 0, S3C2800_PCI_MEMSPACE_SIZE, 307 NULL, 0, EX_NOWAIT); 308 309 sspci_chipset.pc_conf_v = (void *) sc; 310 sspci_chipset.pc_intr_v = (void *) sc; 311 312 pci_configure_bus(&sspci_chipset, ioext, memext, NULL, 0, 313 arm_dcache_align); 314 315 extent_destroy(memext); 316 extent_destroy(ioext); 317 #endif /* PCI_NETBSD_CONFIGURE */ 318 319 /* initialize bus space tag */ 320 sspci_io_tag = *iot; 321 sspci_io_tag.bs_cookie = (void *) S3C2800_PCI_IOSPACE_BASE; 322 sspci_io_tag.bs_map = sspci_bs_map; 323 sspci_mem_tag = *iot; 324 sspci_mem_tag.bs_cookie = (void *) S3C2800_PCI_MEMSPACE_BASE; 325 sspci_mem_tag.bs_map = sspci_bs_map; 326 327 328 /* Platform provides PCI DMA tag */ 329 pci_dma_tag = s3c2800_pci_dma_init(); 330 331 pci_pba.pba_pc = &sspci_chipset; 332 pci_pba.pba_iot = &sspci_io_tag; 333 pci_pba.pba_memt = &sspci_mem_tag; 334 pci_pba.pba_dmat = pci_dma_tag; 335 pci_pba.pba_dmat64 = NULL; 336 pci_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 337 pci_pba.pba_bus = 0; 338 pci_pba.pba_bridgetag = NULL; 339 340 config_found_ia(self, "pcibus", &pci_pba, pcibusprint); 341 342 return; 343 344 #undef FAIL 345 abort: 346 panic("%s: map failed (%s)", 347 device_xname(self), error_on); 348 } 349 350 351 static int 352 sspci_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 353 bus_space_handle_t * bshp) 354 { 355 bus_addr_t startpa, endpa; 356 vaddr_t va; 357 358 #ifdef PCI_DEBUG 359 printf("sspci_bs_map: t=%p, addr=%lx, size=%lx, flag=%d\n", 360 t, bpa, size, flag); 361 #endif 362 363 /* Round the allocation to page boundries */ 364 startpa = trunc_page(bpa); 365 endpa = round_page(bpa + size); 366 367 /* Get some VM. */ 368 va = uvm_km_alloc(kernel_map, endpa - startpa, 0, 369 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 370 if (va == 0) 371 return ENOMEM; 372 373 /* Store the bus space handle */ 374 *bshp = va + (bpa & PGOFSET); 375 376 /* Now map the pages */ 377 /* The cookie is the physical base address for PCI I/O or memory area */ 378 while (startpa < endpa) { 379 /* XXX pmap_kenter_pa maps pages cacheable -- not what we 380 * want. */ 381 pmap_enter(pmap_kernel(), va, (bus_addr_t) t + startpa, 382 VM_PROT_READ | VM_PROT_WRITE, 0); 383 va += PAGE_SIZE; 384 startpa += PAGE_SIZE; 385 } 386 pmap_update(pmap_kernel()); 387 388 return 0; 389 } 390 391 392 393 void 394 s3c2800_pci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 395 { 396 #ifdef PCI_DEBUG 397 printf("pci_conf_interrupt(v(%p), bus(%d), dev(%d), ipin(%d), swiz(%d), *iline(%p)\n", v, bus, dev, ipin, swiz, iline); 398 #endif 399 if (bus == 0) { 400 *iline = dev; 401 } else { 402 panic("pci_conf_interrupt: bus=%d: not yet implemented", bus); 403 } 404 } 405 406 void 407 s3c2800_pci_attach_hook(device_t parent, device_t self, 408 struct pcibus_attach_args * pba) 409 { 410 411 /* Nothing to do. */ 412 #ifdef PCI_DEBUG 413 printf("s3c2800_pci_attach_hook()\n"); 414 #endif 415 } 416 417 int 418 s3c2800_pci_bus_maxdevs(void *v, int busno) 419 { 420 421 #ifdef PCI_DEBUG 422 printf("s3c2800_pci_bus_maxdevs(v=%p, busno=%d)\n", v, busno); 423 #endif 424 return (32); 425 } 426 pcitag_t 427 s3c2800_pci_make_tag(void *v, int bus, int device, int function) 428 { 429 430 return ((bus << BUSNO_SHIFT) | (device << DEVNO_SHIFT) | 431 (function << FUNNO_SHIFT)); 432 } 433 434 void 435 s3c2800_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 436 { 437 if (bp != NULL) 438 *bp = (tag >> BUSNO_SHIFT) & 0xff; 439 if (dp != NULL) 440 *dp = (tag >> DEVNO_SHIFT) & 0x1f; 441 if (fp != NULL) 442 *fp = (tag >> FUNNO_SHIFT) & 0x7; 443 } 444 445 static vaddr_t 446 make_pci_conf_va(struct sspci_softc * sc, pcitag_t tag, int offset) 447 { 448 if ((tag & BUSNO_MASK) == 0) { 449 /* configuration type 0 */ 450 int devno = tag_to_devno(tag); 451 452 if (devno < BUS0_DEV_MIN || BUS0_DEV_MAX < devno) 453 return 0; 454 455 return (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 456 (tag & (DEVNO_MASK | FUNNO_MASK)) + offset; 457 } else { 458 /* XXX */ 459 return (vaddr_t) - 1; /* cause fault */ 460 } 461 } 462 463 464 pcireg_t 465 s3c2800_pci_conf_read(void *v, pcitag_t tag, int offset) 466 { 467 struct sspci_softc *sc = v; 468 vaddr_t va = make_pci_conf_va(sc, tag, offset); 469 int s; 470 pcireg_t rv; 471 472 #ifdef PCI_DEBUG 473 printf("s3c2800_pci_conf_read: base=%lx tag=%lx offset=%x\n", 474 sc->sc_conf0_ioh, tag, offset); 475 #endif 476 if (va == 0) 477 return -1; 478 479 PCI_CONF_LOCK(s); 480 481 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 482 #if PCI_DEBUG 483 printf("conf_read: %lx bad address\n", va); 484 #endif 485 rv = (pcireg_t) - 1; 486 } 487 PCI_CONF_UNLOCK(s); 488 489 return rv; 490 } 491 492 void 493 s3c2800_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 494 { 495 struct sspci_softc *sc = v; 496 vaddr_t va = make_pci_conf_va(sc, tag, offset); 497 u_int s; 498 499 #ifdef PCI_DEBUG 500 printf("s3c2800_pci_conf_write: tag=%lx offset=%x -> va=%lx\n", tag, offset, va); 501 #endif 502 503 PCI_CONF_LOCK(s); 504 505 *(pcireg_t *) va = val; 506 507 PCI_CONF_UNLOCK(s); 508 } 509 510 void * 511 s3c2800_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level, 512 int (*func) (void *), void *arg) 513 { 514 struct sspci_softc *sc = pcv; 515 struct sspci_irq_handler *handler; 516 int s; 517 518 #ifdef PCI_DEBUG 519 printf("s3c2800_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, " 520 "func=%p, arg=%p)\n", pcv, ih, level, func, arg); 521 #endif 522 523 handler = malloc(sizeof *handler, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 524 if (handler == NULL) 525 panic("sspci_intr_establish: can't malloc handler info"); 526 527 handler->func = func; 528 handler->arg = arg; 529 handler->level = level; 530 531 s = splhigh(); 532 SLIST_INSERT_HEAD(&sc->sc_irq_handlers, handler, link); 533 splx(s); 534 535 return (handler); 536 } 537 538 void 539 s3c2800_pci_intr_disestablish(void *pcv, void *cookie) 540 { 541 struct sspci_softc *sc = pcv; 542 struct sspci_irq_handler *ih = cookie; 543 int s; 544 545 #ifdef PCI_DEBUG 546 printf("s3c2800_pci_intr_disestablish(pcv=%p, cookie=%p)\n", 547 pcv, cookie); 548 #endif 549 550 s = splhigh(); 551 SLIST_REMOVE(&sc->sc_irq_handlers, ih, sspci_irq_handler, link); 552 splx(s); 553 } 554 555 int 556 s3c2800_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 557 { 558 #ifdef PCI_DEBUG 559 int pin = pa->pa_intrpin; 560 void *pcv = pa->pa_pc; 561 pcitag_t intrtag = pa->pa_intrtag; 562 int bus, device, function; 563 564 s3c2800_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 565 printf("s3c2800_pci_intr_map: pcv=%p, tag=%08lx pin=%d dev=%d\n", 566 pcv, intrtag, pin, device); 567 #endif 568 569 570 /* S3C2800 has only one interrupt line for PCI */ 571 *ihp = 0; 572 return 0; 573 } 574 575 const char * 576 s3c2800_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len) 577 { 578 /* We have only one interrupt source from PCI */ 579 strlcpy(buf, "pciint", len); 580 return buf; 581 } 582 583 const struct evcnt * 584 s3c2800_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih) 585 { 586 587 /* XXX for now, no evcnt parent reported */ 588 return NULL; 589 } 590 /* 591 * Initialize PCI controller 592 */ 593 int 594 sspci_init_controller(struct sspci_softc * sc) 595 { 596 bus_space_tag_t iot = sc->sc_iot; 597 bus_space_handle_t ioh = sc->sc_reg_ioh; 598 599 /* disable PCI command */ 600 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 601 0xffff0000); 602 603 /* latency=0x10, cacheline=8 */ 604 bus_space_write_4(iot, ioh, PCI_BHLC_REG, 605 PCI_BHLC_CODE(0, 0, 0, 0x10, 8)); 606 607 bus_space_write_4(iot, ioh, PCI_INTERRUPT_REG, 608 PCI_INTERRUPT_CODE(0, 0, 0, 0)); 609 610 611 612 #if 1 613 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 614 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 615 /* Cover all DBANKs with BAR0 */ 616 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xf8000000); 617 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, S3C2800_DBANK0_START); 618 #else 619 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 620 PCI_MAPREG_MEM_TYPE_32BIT | 0xf0000000); 621 bus_space_write_4(iot, ioh, PCI_MAPREG_START + 4, 622 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 623 624 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xffff0000); 625 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, 0xffff0000); 626 bus_space_write_4(iot, ioh, PCICTL_PCIBAM1, 0xf1000000); 627 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA1, S3C2800_DBANK0_START); 628 #endif 629 630 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 631 PCI_STATUS_PARITY_DETECT | 632 PCI_STATUS_SPECIAL_ERROR | 633 PCI_STATUS_MASTER_ABORT | 634 PCI_STATUS_MASTER_TARGET_ABORT | 635 PCI_STATUS_TARGET_TARGET_ABORT | 636 PCI_STATUS_DEVSEL_MEDIUM | 637 PCI_STATUS_PARITY_ERROR | 638 PCI_STATUS_BACKTOBACK_SUPPORT | 639 PCI_STATUS_CAPLIST_SUPPORT | 640 PCI_COMMAND_MASTER_ENABLE | 641 PCI_COMMAND_MEM_ENABLE | 642 PCI_COMMAND_IO_ENABLE); 643 644 bus_space_write_4(iot, ioh, PCICTL_PCICON, 645 PCICON_ARB | PCICON_HST); 646 647 bus_space_write_4(iot, ioh, PCICTL_PCISET, 0); 648 /* clear all interrupts */ 649 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, 0xffffffff); 650 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 0); 651 652 bus_space_write_4(iot, ioh, PCICTL_PCICON, 653 PCICON_RDY | PCICON_CFD | PCICON_ATS | 654 PCICON_ARB | PCICON_HST); 655 656 657 #ifdef PCI_DEBUG 658 { 659 pcireg_t reg; 660 int i; 661 662 for (i = 0; i <= 0x40; i += sizeof(pcireg_t)) { 663 reg = bus_space_read_4(iot, ioh, i); 664 printf("%03x: %08x\n", i, reg); 665 } 666 for (i = 0x100; i <= 0x154; i += sizeof(pcireg_t)) { 667 reg = bus_space_read_4(iot, ioh, i); 668 printf("%03x: %08x\n", i, reg); 669 } 670 } 671 #endif 672 return 0; 673 } 674 675 676 static const char *pci_abnormal_error_name[] = { 677 "PCI reset deasserted", 678 "PCI reset asserted", 679 "PCI master detected fatal error", 680 "PCI master detected parity error", 681 "PCI target detected parity error", 682 "PCI SERR# asserted", 683 }; 684 685 static int 686 sspci_intr(void *arg) 687 { 688 struct sspci_softc *sc = arg; 689 int s; 690 bus_space_tag_t iot = sc->sc_iot; 691 bus_space_handle_t ioh = sc->sc_reg_ioh; 692 uint32_t interrupts, errors; 693 694 interrupts = bus_space_read_4(iot, ioh, PCICTL_PCIINTST); 695 696 if (interrupts & PCIINT_INA) { 697 s = splhigh(); 698 softint_schedule(sc->sc_softinterrupt); 699 700 /* mask INTA itnerrupt until softinterrupt is handled */ 701 sc->sc_pciinten &= ~PCIINT_INA; 702 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 703 sc->sc_pciinten); 704 705 /* acknowledge INTA interrupt */ 706 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, PCIINT_INA); 707 708 splx(s); 709 710 interrupts &= ~PCIINT_INA; 711 712 } 713 errors = interrupts & (PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 714 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD); 715 if (errors) { 716 int i; 717 718 for (i = 0; errors; ++i) { 719 if ((errors & (1 << i)) == 0) 720 continue; 721 722 printf("%s: %s\n", device_xname(sc->sc_dev), 723 pci_abnormal_error_name[i > 4 ? 5 : i]); 724 725 errors &= ~(1 << i); 726 } 727 /* acknowledge interrupts */ 728 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, interrupts); 729 } 730 return 0; 731 } 732 733 static void 734 sspci_softintr(void *arg) 735 { 736 struct sspci_softc *sc = arg; 737 struct sspci_irq_handler *ih; 738 int s; 739 740 741 SLIST_FOREACH(ih, &(sc->sc_irq_handlers), link) { 742 s = _splraise(ih->level); 743 ih->func(ih->arg); 744 splx(s); 745 } 746 747 /* unmask INTA interrupt */ 748 s = splhigh(); 749 sc->sc_pciinten |= PCIINT_INA; 750 bus_space_write_4(sc->sc_iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 751 sc->sc_pciinten); 752 splx(s); 753 } 754
Indexes created Wed Oct 01 07:09:59 GMT 2025