s3c2800_pci.c revision 1.27
1 /* $NetBSD: s3c2800_pci.c,v 1.27 2019/11/10 21:16:24 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * derived from evbarm/ifpga/ifpga_pci.c 35 */ 36 37 /* 38 * Copyright (c) 2001 ARM Ltd 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company may not be used to endorse or promote 50 * products derived from this software without specific prior written 51 * permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * Copyright (c) 1997,1998 Mark Brinicombe. 66 * Copyright (c) 1997,1998 Causality Limited 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by Mark Brinicombe 80 * for the NetBSD Project. 81 * 4. The name of the company nor the name of the author may be used to 82 * endorse or promote products derived from this software without specific 83 * prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 86 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 87 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 88 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 */ 97 98 /* 99 * PCI configuration support for Samsung s3c2800. 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.27 2019/11/10 21:16:24 chs Exp $"); 104 105 #include "opt_pci.h" 106 #include "pci.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/kernel.h> 111 #include <sys/device.h> 112 #include <sys/extent.h> 113 #include <sys/malloc.h> 114 115 #include <uvm/uvm_extern.h> 116 117 #include <sys/bus.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pciconf.h> 122 123 #include <arm/locore.h> 124 125 #include <arm/s3c2xx0/s3c2800reg.h> 126 #include <arm/s3c2xx0/s3c2800var.h> 127 128 /* 129 * pci tag encoding. 130 * also useful for configuration type 0 address 131 */ 132 #define BUSNO_SHIFT 16 133 #define BUSNO_MASK (0xff<<BUSNO_SHIFT) 134 #define DEVNO_SHIFT 11 135 #define DEVNO_MASK (0x1f<<DEVNO_SHIFT) 136 #define tag_to_devno(tag) (((tag)&DEVNO_MASK)>>DEVNO_SHIFT) 137 #define FUNNO_SHIFT 8 138 #define FUNNO_MASK (0x07<<FUNNO_SHIFT) 139 140 #define BUS0_DEV_MIN 1 141 #define BUS0_DEV_MAX 21 142 143 void s3c2800_pci_attach_hook(device_t, device_t, struct pcibus_attach_args *); 144 int s3c2800_pci_bus_maxdevs(void *, int); 145 pcitag_t s3c2800_pci_make_tag(void *, int, int, int); 146 void s3c2800_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 147 pcireg_t s3c2800_pci_conf_read(void *, pcitag_t, int); 148 void s3c2800_pci_conf_write(void *, pcitag_t, int, pcireg_t); 149 void s3c2800_pci_conf_interrupt(void *, int, int, int, int, int *); 150 int s3c2800_pci_intr_map(const struct pci_attach_args *, 151 pci_intr_handle_t *); 152 const char *s3c2800_pci_intr_string(void *, pci_intr_handle_t, char *, size_t); 153 const struct evcnt *s3c2800_pci_intr_evcnt(void *, pci_intr_handle_t); 154 void *s3c2800_pci_intr_establish(void *, pci_intr_handle_t, int, 155 int (*) (void *), void *, const char *); 156 void s3c2800_pci_intr_disestablish(void *, void *); 157 158 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 159 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 160 161 struct sspci_irq_handler { 162 int (*func) (void *); 163 void *arg; 164 int level; 165 SLIST_ENTRY(sspci_irq_handler) link; 166 }; 167 168 struct sspci_softc { 169 device_t sc_dev; 170 171 bus_space_tag_t sc_iot; 172 bus_space_handle_t sc_reg_ioh; 173 bus_space_handle_t sc_conf0_ioh; /* config type0 space */ 174 bus_space_handle_t sc_conf1_ioh; /* config type1 space */ 175 176 uint32_t sc_pciinten; /* copy of PCIINTEN register */ 177 178 /* list of interrupt handlers. SLIST is not good for removing 179 * element from it, but intr_disestablish is rarely called */ 180 SLIST_HEAD(, sspci_irq_handler) sc_irq_handlers; 181 182 void *sc_softinterrupt; 183 }; 184 185 static int sspci_match(device_t, cfdata_t, void *aux); 186 static void sspci_attach(device_t, device_t, void *); 187 188 static int sspci_bs_map(void *, bus_addr_t, bus_size_t, int, 189 bus_space_handle_t *); 190 static int sspci_init_controller(struct sspci_softc *); 191 static int sspci_intr(void *); 192 static void sspci_softintr(void *); 193 194 /* attach structures */ 195 CFATTACH_DECL_NEW(sspci, sizeof(struct sspci_softc), sspci_match, sspci_attach, 196 NULL, NULL); 197 198 199 struct arm32_pci_chipset sspci_chipset = { 200 .pc_attach_hook = s3c2800_pci_attach_hook, 201 .pc_bus_maxdevs = s3c2800_pci_bus_maxdevs, 202 .pc_make_tag = s3c2800_pci_make_tag, 203 .pc_decompose_tag = s3c2800_pci_decompose_tag, 204 .pc_conf_read = s3c2800_pci_conf_read, 205 .pc_conf_write = s3c2800_pci_conf_write, 206 .pc_intr_map = s3c2800_pci_intr_map, 207 .pc_intr_string = s3c2800_pci_intr_string, 208 .pc_intr_evcnt = s3c2800_pci_intr_evcnt, 209 .pc_intr_establish = s3c2800_pci_intr_establish, 210 .pc_intr_disestablish = s3c2800_pci_intr_disestablish, 211 .pc_conf_interrupt = s3c2800_pci_conf_interrupt, 212 }; 213 214 215 /* 216 * bus space tag for PCI IO/Memory access space. 217 * filled in by sspci_attach() 218 */ 219 struct bus_space sspci_io_tag, sspci_mem_tag; 220 221 static int 222 sspci_match(device_t parent, cfdata_t match, void *aux) 223 { 224 return 1; 225 } 226 227 static void 228 sspci_attach(device_t parent, device_t self, void *aux) 229 { 230 struct sspci_softc *sc = device_private(self); 231 struct s3c2xx0_attach_args *aa = aux; 232 bus_space_tag_t iot; 233 bus_dma_tag_t pci_dma_tag; 234 const char *error_on; /* for panic message */ 235 #if defined(PCI_NETBSD_CONFIGURE) 236 struct extent *ioext, *memext; 237 struct pcibus_attach_args pci_pba; 238 #endif 239 240 #define FAIL(which) do { \ 241 error_on=(which); goto abort; }while(/*CONSTCOND*/0) 242 243 sc->sc_dev = self; 244 iot = sc->sc_iot = aa->sa_iot; 245 if (bus_space_map(iot, S3C2800_PCICTL_BASE, 246 S3C2800_PCICTL_SIZE, 0, &sc->sc_reg_ioh)) 247 FAIL("control regs"); 248 249 if (bus_space_map(iot, S3C2800_PCI_CONF0_BASE, 250 S3C2800_PCI_CONF0_SIZE, 0, &sc->sc_conf0_ioh)) 251 FAIL("config type 0 area"); 252 253 #if 0 254 if (bus_space_map(iot, S3C2800_PCI_CONF1_BASE, 255 S3C2800_PCI_CONF1_SIZE, 0, &sc->sc_conf1_ioh)) 256 FAIL("config type 1 area"); 257 #endif 258 printf("\n"); 259 260 SLIST_INIT(&sc->sc_irq_handlers); 261 if (!s3c2800_intr_establish(S3C2800_INT_PCI, IPL_AUDIO, IST_LEVEL, 262 sspci_intr, sc)) 263 FAIL("intr_establish"); 264 265 sc->sc_softinterrupt = softint_establish(SOFTINT_SERIAL, 266 sspci_softintr, sc); 267 if (sc->sc_softinterrupt == NULL) 268 FAIL("softint_establish"); 269 270 #if defined(PCI_NETBSD_CONFIGURE) 271 if (sspci_init_controller(sc)) { 272 printf("%s: failed to initialize controller\n", device_xname(self)); 273 return; 274 } 275 #endif 276 277 sc->sc_pciinten = 278 PCIINT_INA | PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 279 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD; 280 281 bus_space_write_4(iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 282 sc->sc_pciinten); 283 284 { 285 pcireg_t id_reg, class_reg; 286 char buf[1000]; 287 288 id_reg = bus_space_read_4(iot, sc->sc_reg_ioh, 289 PCI_ID_REG); 290 class_reg = bus_space_read_4(iot, 291 sc->sc_reg_ioh, PCI_CLASS_REG); 292 293 pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf)); 294 printf("%s: %s\n", device_xname(self), buf); 295 } 296 297 #if defined(PCI_NETBSD_CONFIGURE) 298 ioext = extent_create("pciio", 0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100, 299 NULL, 0, EX_NOWAIT); 300 301 memext = extent_create("pcimem", 0, S3C2800_PCI_MEMSPACE_SIZE, 302 NULL, 0, EX_NOWAIT); 303 304 sspci_chipset.pc_conf_v = (void *) sc; 305 sspci_chipset.pc_intr_v = (void *) sc; 306 307 pci_configure_bus(&sspci_chipset, ioext, memext, NULL, 0, 308 arm_dcache_align); 309 310 extent_destroy(memext); 311 extent_destroy(ioext); 312 #endif /* PCI_NETBSD_CONFIGURE */ 313 314 /* initialize bus space tag */ 315 sspci_io_tag = *iot; 316 sspci_io_tag.bs_cookie = (void *) S3C2800_PCI_IOSPACE_BASE; 317 sspci_io_tag.bs_map = sspci_bs_map; 318 sspci_mem_tag = *iot; 319 sspci_mem_tag.bs_cookie = (void *) S3C2800_PCI_MEMSPACE_BASE; 320 sspci_mem_tag.bs_map = sspci_bs_map; 321 322 323 /* Platform provides PCI DMA tag */ 324 pci_dma_tag = s3c2800_pci_dma_init(); 325 326 pci_pba.pba_pc = &sspci_chipset; 327 pci_pba.pba_iot = &sspci_io_tag; 328 pci_pba.pba_memt = &sspci_mem_tag; 329 pci_pba.pba_dmat = pci_dma_tag; 330 pci_pba.pba_dmat64 = NULL; 331 pci_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 332 pci_pba.pba_bus = 0; 333 pci_pba.pba_bridgetag = NULL; 334 335 config_found_ia(self, "pcibus", &pci_pba, pcibusprint); 336 337 return; 338 339 #undef FAIL 340 abort: 341 panic("%s: map failed (%s)", 342 device_xname(self), error_on); 343 } 344 345 346 static int 347 sspci_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 348 bus_space_handle_t * bshp) 349 { 350 bus_addr_t startpa, endpa; 351 vaddr_t va; 352 353 #ifdef PCI_DEBUG 354 printf("sspci_bs_map: t=%p, addr=%lx, size=%lx, flag=%d\n", 355 t, bpa, size, flag); 356 #endif 357 358 /* Round the allocation to page boundries */ 359 startpa = trunc_page(bpa); 360 endpa = round_page(bpa + size); 361 362 /* Get some VM. */ 363 va = uvm_km_alloc(kernel_map, endpa - startpa, 0, 364 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 365 if (va == 0) 366 return ENOMEM; 367 368 /* Store the bus space handle */ 369 *bshp = va + (bpa & PGOFSET); 370 371 /* Now map the pages */ 372 /* The cookie is the physical base address for PCI I/O or memory area */ 373 while (startpa < endpa) { 374 /* XXX pmap_kenter_pa maps pages cacheable -- not what we 375 * want. */ 376 pmap_enter(pmap_kernel(), va, (bus_addr_t) t + startpa, 377 VM_PROT_READ | VM_PROT_WRITE, 0); 378 va += PAGE_SIZE; 379 startpa += PAGE_SIZE; 380 } 381 pmap_update(pmap_kernel()); 382 383 return 0; 384 } 385 386 387 388 void 389 s3c2800_pci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 390 { 391 #ifdef PCI_DEBUG 392 printf("pci_conf_interrupt(v(%p), bus(%d), dev(%d), ipin(%d), swiz(%d), *iline(%p)\n", v, bus, dev, ipin, swiz, iline); 393 #endif 394 if (bus == 0) { 395 *iline = dev; 396 } else { 397 panic("pci_conf_interrupt: bus=%d: not yet implemented", bus); 398 } 399 } 400 401 void 402 s3c2800_pci_attach_hook(device_t parent, device_t self, 403 struct pcibus_attach_args * pba) 404 { 405 406 /* Nothing to do. */ 407 #ifdef PCI_DEBUG 408 printf("s3c2800_pci_attach_hook()\n"); 409 #endif 410 } 411 412 int 413 s3c2800_pci_bus_maxdevs(void *v, int busno) 414 { 415 416 #ifdef PCI_DEBUG 417 printf("s3c2800_pci_bus_maxdevs(v=%p, busno=%d)\n", v, busno); 418 #endif 419 return (32); 420 } 421 pcitag_t 422 s3c2800_pci_make_tag(void *v, int bus, int device, int function) 423 { 424 425 return ((bus << BUSNO_SHIFT) | (device << DEVNO_SHIFT) | 426 (function << FUNNO_SHIFT)); 427 } 428 429 void 430 s3c2800_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 431 { 432 if (bp != NULL) 433 *bp = (tag >> BUSNO_SHIFT) & 0xff; 434 if (dp != NULL) 435 *dp = (tag >> DEVNO_SHIFT) & 0x1f; 436 if (fp != NULL) 437 *fp = (tag >> FUNNO_SHIFT) & 0x7; 438 } 439 440 static vaddr_t 441 make_pci_conf_va(struct sspci_softc * sc, pcitag_t tag, int offset) 442 { 443 444 if ((unsigned int)offset >= PCI_CONF_SIZE) 445 return (vaddr_t) -1; 446 447 if ((tag & BUSNO_MASK) == 0) { 448 /* configuration type 0 */ 449 int devno = tag_to_devno(tag); 450 451 if (devno < BUS0_DEV_MIN || BUS0_DEV_MAX < devno) 452 return 0; 453 454 return (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 455 (tag & (DEVNO_MASK | FUNNO_MASK)) + offset; 456 } else { 457 /* XXX */ 458 return (vaddr_t) - 1; /* cause fault */ 459 } 460 } 461 462 463 pcireg_t 464 s3c2800_pci_conf_read(void *v, pcitag_t tag, int offset) 465 { 466 struct sspci_softc *sc = v; 467 vaddr_t va = make_pci_conf_va(sc, tag, offset); 468 int s; 469 pcireg_t rv; 470 471 #ifdef PCI_DEBUG 472 printf("s3c2800_pci_conf_read: base=%lx tag=%lx offset=%x\n", 473 sc->sc_conf0_ioh, tag, offset); 474 #endif 475 if (va == 0) 476 return -1; 477 478 PCI_CONF_LOCK(s); 479 480 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 481 #if PCI_DEBUG 482 printf("conf_read: %lx bad address\n", va); 483 #endif 484 rv = (pcireg_t) - 1; 485 } 486 PCI_CONF_UNLOCK(s); 487 488 return rv; 489 } 490 491 void 492 s3c2800_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 493 { 494 struct sspci_softc *sc = v; 495 vaddr_t va = make_pci_conf_va(sc, tag, offset); 496 u_int s; 497 498 #ifdef PCI_DEBUG 499 printf("s3c2800_pci_conf_write: tag=%lx offset=%x -> va=%lx\n", tag, offset, va); 500 #endif 501 502 PCI_CONF_LOCK(s); 503 504 *(pcireg_t *) va = val; 505 506 PCI_CONF_UNLOCK(s); 507 } 508 509 void * 510 s3c2800_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level, 511 int (*func) (void *), void *arg, const char *xname) 512 { 513 struct sspci_softc *sc = pcv; 514 struct sspci_irq_handler *handler; 515 int s; 516 517 #ifdef PCI_DEBUG 518 printf("s3c2800_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, " 519 "func=%p, arg=%p, xname=%s)\n", pcv, ih, level, func, arg, xname); 520 #endif 521 522 handler = malloc(sizeof *handler, M_DEVBUF, M_WAITOK); 523 handler->func = func; 524 handler->arg = arg; 525 handler->level = level; 526 527 s = splhigh(); 528 SLIST_INSERT_HEAD(&sc->sc_irq_handlers, handler, link); 529 splx(s); 530 531 return (handler); 532 } 533 534 void 535 s3c2800_pci_intr_disestablish(void *pcv, void *cookie) 536 { 537 struct sspci_softc *sc = pcv; 538 struct sspci_irq_handler *ih = cookie; 539 int s; 540 541 #ifdef PCI_DEBUG 542 printf("s3c2800_pci_intr_disestablish(pcv=%p, cookie=%p)\n", 543 pcv, cookie); 544 #endif 545 546 s = splhigh(); 547 SLIST_REMOVE(&sc->sc_irq_handlers, ih, sspci_irq_handler, link); 548 splx(s); 549 } 550 551 int 552 s3c2800_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 553 { 554 #ifdef PCI_DEBUG 555 int pin = pa->pa_intrpin; 556 void *pcv = pa->pa_pc; 557 pcitag_t intrtag = pa->pa_intrtag; 558 int bus, device, function; 559 560 s3c2800_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 561 printf("s3c2800_pci_intr_map: pcv=%p, tag=%08lx pin=%d dev=%d\n", 562 pcv, intrtag, pin, device); 563 #endif 564 565 566 /* S3C2800 has only one interrupt line for PCI */ 567 *ihp = 0; 568 return 0; 569 } 570 571 const char * 572 s3c2800_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len) 573 { 574 /* We have only one interrupt source from PCI */ 575 strlcpy(buf, "pciint", len); 576 return buf; 577 } 578 579 const struct evcnt * 580 s3c2800_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih) 581 { 582 583 /* XXX for now, no evcnt parent reported */ 584 return NULL; 585 } 586 /* 587 * Initialize PCI controller 588 */ 589 int 590 sspci_init_controller(struct sspci_softc * sc) 591 { 592 bus_space_tag_t iot = sc->sc_iot; 593 bus_space_handle_t ioh = sc->sc_reg_ioh; 594 595 /* disable PCI command */ 596 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 597 0xffff0000); 598 599 /* latency=0x10, cacheline=8 */ 600 bus_space_write_4(iot, ioh, PCI_BHLC_REG, 601 PCI_BHLC_CODE(0, 0, 0, 0x10, 8)); 602 603 bus_space_write_4(iot, ioh, PCI_INTERRUPT_REG, 604 PCI_INTERRUPT_CODE(0, 0, 0, 0)); 605 606 607 608 #if 1 609 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 610 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 611 /* Cover all DBANKs with BAR0 */ 612 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xf8000000); 613 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, S3C2800_DBANK0_START); 614 #else 615 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 616 PCI_MAPREG_MEM_TYPE_32BIT | 0xf0000000); 617 bus_space_write_4(iot, ioh, PCI_MAPREG_START + 4, 618 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 619 620 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xffff0000); 621 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, 0xffff0000); 622 bus_space_write_4(iot, ioh, PCICTL_PCIBAM1, 0xf1000000); 623 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA1, S3C2800_DBANK0_START); 624 #endif 625 626 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 627 PCI_STATUS_PARITY_DETECT | 628 PCI_STATUS_SPECIAL_ERROR | 629 PCI_STATUS_MASTER_ABORT | 630 PCI_STATUS_MASTER_TARGET_ABORT | 631 PCI_STATUS_TARGET_TARGET_ABORT | 632 PCI_STATUS_DEVSEL_MEDIUM | 633 PCI_STATUS_PARITY_ERROR | 634 PCI_STATUS_BACKTOBACK_SUPPORT | 635 PCI_STATUS_CAPLIST_SUPPORT | 636 PCI_COMMAND_MASTER_ENABLE | 637 PCI_COMMAND_MEM_ENABLE | 638 PCI_COMMAND_IO_ENABLE); 639 640 bus_space_write_4(iot, ioh, PCICTL_PCICON, 641 PCICON_ARB | PCICON_HST); 642 643 bus_space_write_4(iot, ioh, PCICTL_PCISET, 0); 644 /* clear all interrupts */ 645 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, 0xffffffff); 646 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 0); 647 648 bus_space_write_4(iot, ioh, PCICTL_PCICON, 649 PCICON_RDY | PCICON_CFD | PCICON_ATS | 650 PCICON_ARB | PCICON_HST); 651 652 653 #ifdef PCI_DEBUG 654 { 655 pcireg_t reg; 656 int i; 657 658 for (i = 0; i <= 0x40; i += sizeof(pcireg_t)) { 659 reg = bus_space_read_4(iot, ioh, i); 660 printf("%03x: %08x\n", i, reg); 661 } 662 for (i = 0x100; i <= 0x154; i += sizeof(pcireg_t)) { 663 reg = bus_space_read_4(iot, ioh, i); 664 printf("%03x: %08x\n", i, reg); 665 } 666 } 667 #endif 668 return 0; 669 } 670 671 672 static const char *pci_abnormal_error_name[] = { 673 "PCI reset deasserted", 674 "PCI reset asserted", 675 "PCI master detected fatal error", 676 "PCI master detected parity error", 677 "PCI target detected parity error", 678 "PCI SERR# asserted", 679 }; 680 681 static int 682 sspci_intr(void *arg) 683 { 684 struct sspci_softc *sc = arg; 685 int s; 686 bus_space_tag_t iot = sc->sc_iot; 687 bus_space_handle_t ioh = sc->sc_reg_ioh; 688 uint32_t interrupts, errors; 689 690 interrupts = bus_space_read_4(iot, ioh, PCICTL_PCIINTST); 691 692 if (interrupts & PCIINT_INA) { 693 s = splhigh(); 694 softint_schedule(sc->sc_softinterrupt); 695 696 /* mask INTA itnerrupt until softinterrupt is handled */ 697 sc->sc_pciinten &= ~PCIINT_INA; 698 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 699 sc->sc_pciinten); 700 701 /* acknowledge INTA interrupt */ 702 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, PCIINT_INA); 703 704 splx(s); 705 706 interrupts &= ~PCIINT_INA; 707 708 } 709 errors = interrupts & (PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 710 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD); 711 if (errors) { 712 int i; 713 714 for (i = 0; errors; ++i) { 715 if ((errors & (1 << i)) == 0) 716 continue; 717 718 printf("%s: %s\n", device_xname(sc->sc_dev), 719 pci_abnormal_error_name[i > 4 ? 5 : i]); 720 721 errors &= ~(1 << i); 722 } 723 /* acknowledge interrupts */ 724 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, interrupts); 725 } 726 return 0; 727 } 728 729 static void 730 sspci_softintr(void *arg) 731 { 732 struct sspci_softc *sc = arg; 733 struct sspci_irq_handler *ih; 734 int s; 735 736 737 SLIST_FOREACH(ih, &(sc->sc_irq_handlers), link) { 738 s = _splraise(ih->level); 739 ih->func(ih->arg); 740 splx(s); 741 } 742 743 /* unmask INTA interrupt */ 744 s = splhigh(); 745 sc->sc_pciinten |= PCIINT_INA; 746 bus_space_write_4(sc->sc_iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 747 sc->sc_pciinten); 748 splx(s); 749 } 750
Indexes created Wed Oct 01 13:09:50 GMT 2025