s3c2800_pci.c revision 1.5
1 /* $NetBSD: s3c2800_pci.c,v 1.5 2003/06/15 23:08:57 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * derived from evbarm/ifpga/ifpga_pci.c 35 */ 36 37 /* 38 * Copyright (c) 2001 ARM Ltd 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company may not be used to endorse or promote 50 * products derived from this software without specific prior written 51 * permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * Copyright (c) 1997,1998 Mark Brinicombe. 66 * Copyright (c) 1997,1998 Causality Limited 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by Mark Brinicombe 80 * for the NetBSD Project. 81 * 4. The name of the company nor the name of the author may be used to 82 * endorse or promote products derived from this software without specific 83 * prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 86 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 87 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 88 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 */ 97 98 /* 99 * PCI configuration support for Samsung s3c2800. 100 */ 101 102 #include <sys/param.h> 103 #include <sys/systm.h> 104 #include <sys/kernel.h> 105 #include <sys/device.h> 106 #include <sys/extent.h> 107 #include <sys/malloc.h> 108 109 #include <uvm/uvm_extern.h> 110 111 #include <machine/bus.h> 112 113 #include <arm/s3c2xx0/s3c2800reg.h> 114 #include <arm/s3c2xx0/s3c2800var.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pciconf.h> 118 119 #include "opt_pci.h" 120 #include "pci.h" 121 122 /* 123 * pci tag encoding. 124 * also useful for configuration type 0 address 125 */ 126 #define BUSNO_SHIFT 16 127 #define BUSNO_MASK (0xff<<BUSNO_SHIFT) 128 #define DEVNO_SHIFT 11 129 #define DEVNO_MASK (0x1f<<DEVNO_SHIFT) 130 #define tag_to_devno(tag) (((tag)&DEVNO_MASK)>>DEVNO_SHIFT) 131 #define FUNNO_SHIFT 8 132 #define FUNNO_MASK (0x07<<FUNNO_SHIFT) 133 134 #define BUS0_DEV_MIN 1 135 #define BUS0_DEV_MAX 21 136 137 void s3c2800_pci_attach_hook(struct device *, struct device *, 138 struct pcibus_attach_args *); 139 int s3c2800_pci_bus_maxdevs(void *, int); 140 pcitag_t s3c2800_pci_make_tag(void *, int, int, int); 141 void s3c2800_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 142 pcireg_t s3c2800_pci_conf_read(void *, pcitag_t, int); 143 void s3c2800_pci_conf_write(void *, pcitag_t, int, pcireg_t); 144 int s3c2800_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 145 const char *s3c2800_pci_intr_string(void *, pci_intr_handle_t); 146 const struct evcnt *s3c2800_pci_intr_evcnt(void *, pci_intr_handle_t); 147 void * s3c2800_pci_intr_establish(void *, pci_intr_handle_t, int, 148 int (*) (void *), void *); 149 void s3c2800_pci_intr_disestablish(void *, void *); 150 151 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 152 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 153 154 struct sspci_irq_handler { 155 int (*func) (void *); 156 void *arg; 157 int level; 158 SLIST_ENTRY(sspci_irq_handler) link; 159 }; 160 161 struct sspci_softc { 162 struct device sc_dev; 163 164 bus_space_tag_t sc_iot; 165 bus_space_handle_t sc_reg_ioh; 166 bus_space_handle_t sc_conf0_ioh; /* config type0 space */ 167 bus_space_handle_t sc_conf1_ioh; /* config type1 space */ 168 169 uint32_t sc_pciinten; /* copy of PCIINTEN register */ 170 171 /* list of interrupt handlers. SLIST is not good for removing 172 * element from it, but intr_disestablish is rarely called */ 173 SLIST_HEAD(, sspci_irq_handler) sc_irq_handlers; 174 175 void *sc_softinterrupt; 176 }; 177 178 static int sspci_match(struct device *, struct cfdata *, void *aux); 179 static void sspci_attach(struct device *, struct device *, void *); 180 181 static int sspci_bs_map(void *, bus_addr_t, bus_size_t, int, 182 bus_space_handle_t *); 183 static int sspci_init_controller(struct sspci_softc *); 184 static int sspci_intr(void *); 185 static void sspci_softintr(void *); 186 187 /* attach structures */ 188 CFATTACH_DECL(sspci, sizeof(struct sspci_softc), sspci_match, sspci_attach, 189 NULL, NULL); 190 191 192 struct arm32_pci_chipset sspci_chipset = { 193 NULL, /* conf_v */ 194 s3c2800_pci_attach_hook, 195 s3c2800_pci_bus_maxdevs, 196 s3c2800_pci_make_tag, 197 s3c2800_pci_decompose_tag, 198 s3c2800_pci_conf_read, 199 s3c2800_pci_conf_write, 200 NULL, /* intr_v */ 201 s3c2800_pci_intr_map, 202 s3c2800_pci_intr_string, 203 s3c2800_pci_intr_evcnt, 204 s3c2800_pci_intr_establish, 205 s3c2800_pci_intr_disestablish 206 }; 207 208 209 /* 210 * bus space tag for PCI IO/Memory access space. 211 * filled in by sspci_attach() 212 */ 213 struct bus_space sspci_io_tag, sspci_mem_tag; 214 215 static int 216 sspci_match(struct device *parent, struct cfdata *match, void *aux) 217 { 218 return 1; 219 } 220 221 static int 222 sspci_print(void *aux, const char *pnp) 223 { 224 struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *) aux; 225 226 if (pnp) 227 aprint_normal("%s at %s", pci_pba->pba_busname, pnp); 228 if (strcmp(pci_pba->pba_busname, "pci") == 0) 229 aprint_normal(" bus %d", pci_pba->pba_bus); 230 231 return UNCONF; 232 } 233 234 static void 235 sspci_attach(struct device *parent, struct device *self, void *aux) 236 { 237 struct sspci_softc *sc = (struct sspci_softc *) self; 238 struct s3c2xx0_attach_args *aa = aux; 239 bus_space_tag_t iot; 240 bus_dma_tag_t pci_dma_tag; 241 const char *error_on; /* for panic message */ 242 #if defined(PCI_NETBSD_CONFIGURE) 243 struct extent *ioext, *memext; 244 struct pcibus_attach_args pci_pba; 245 #endif 246 247 #define FAIL(which) do { \ 248 error_on=(which); goto abort; }while(/*CONSTCOND*/0) 249 250 iot = sc->sc_iot = aa->sa_iot; 251 if (bus_space_map(iot, S3C2800_PCICTL_BASE, 252 S3C2800_PCICTL_SIZE, 0, &sc->sc_reg_ioh)) 253 FAIL("control regs"); 254 255 if (bus_space_map(iot, S3C2800_PCI_CONF0_BASE, 256 S3C2800_PCI_CONF0_SIZE, 0, &sc->sc_conf0_ioh)) 257 FAIL("config type 0 area"); 258 259 #if 0 260 if (bus_space_map(iot, S3C2800_PCI_CONF1_BASE, 261 S3C2800_PCI_CONF1_SIZE, 0, &sc->sc_conf1_ioh)) 262 FAIL("config type 1 area"); 263 #endif 264 printf("\n"); 265 266 SLIST_INIT(&sc->sc_irq_handlers); 267 if (!s3c2800_intr_establish(S3C2800_INT_PCI, IPL_AUDIO, IST_LEVEL, 268 sspci_intr, sc)) 269 FAIL("intr_establish"); 270 271 sc->sc_softinterrupt = softintr_establish(IPL_SOFT, 272 sspci_softintr, sc); 273 if (sc->sc_softinterrupt == NULL) 274 FAIL("softintr_establish"); 275 276 #if defined(PCI_NETBSD_CONFIGURE) 277 if (sspci_init_controller(sc)) { 278 printf("%s: failed to initialize controller\n", self->dv_xname); 279 return; 280 } 281 #endif 282 283 sc->sc_pciinten = 284 PCIINT_INA | PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 285 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD; 286 287 bus_space_write_4(iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 288 sc->sc_pciinten); 289 290 { 291 pcireg_t id_reg, class_reg; 292 char buf[1000]; 293 294 id_reg = bus_space_read_4(iot, sc->sc_reg_ioh, 295 PCI_ID_REG); 296 class_reg = bus_space_read_4(iot, 297 sc->sc_reg_ioh, PCI_CLASS_REG); 298 299 pci_devinfo(id_reg, class_reg, 1, buf); 300 printf("%s: %s\n", self->dv_xname, buf); 301 } 302 303 #if defined(PCI_NETBSD_CONFIGURE) 304 ioext = extent_create("pciio", 0, S3C2800_PCI_IOSPACE_SIZE, 305 M_DEVBUF, NULL, 0, EX_NOWAIT); 306 307 memext = extent_create("pcimem", 0, S3C2800_PCI_MEMSPACE_SIZE, 308 M_DEVBUF, NULL, 0, EX_NOWAIT); 309 310 sspci_chipset.pc_conf_v = (void *) sc; 311 sspci_chipset.pc_intr_v = (void *) sc; 312 313 pci_configure_bus(&sspci_chipset, ioext, memext, NULL, 0, 314 arm_dcache_align); 315 316 extent_destroy(memext); 317 extent_destroy(ioext); 318 319 printf("pci_configure_bus done\n"); 320 #endif /* PCI_NETBSD_CONFIGURE */ 321 322 /* initialize bus space tag */ 323 sspci_io_tag = *iot; 324 sspci_io_tag.bs_cookie = (void *) S3C2800_PCI_IOSPACE_BASE; 325 sspci_io_tag.bs_map = sspci_bs_map; 326 sspci_mem_tag = *iot; 327 sspci_mem_tag.bs_cookie = (void *) S3C2800_PCI_MEMSPACE_BASE; 328 sspci_mem_tag.bs_map = sspci_bs_map; 329 330 331 /* Platform provides PCI DMA tag */ 332 pci_dma_tag = s3c2800_pci_dma_init(); 333 334 pci_pba.pba_busname = "pci"; 335 pci_pba.pba_pc = &sspci_chipset; 336 pci_pba.pba_iot = &sspci_io_tag; 337 pci_pba.pba_memt = &sspci_mem_tag; 338 pci_pba.pba_dmat = pci_dma_tag; 339 pci_pba.pba_dmat64 = NULL; 340 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 341 pci_pba.pba_bus = 0; 342 pci_pba.pba_bridgetag = NULL; 343 344 config_found(self, &pci_pba, sspci_print); 345 346 return; 347 348 #undef FAIL 349 abort: 350 panic("%s: map failed (%s)", 351 self->dv_xname, error_on); 352 } 353 354 355 static int 356 sspci_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 357 bus_space_handle_t * bshp) 358 { 359 bus_addr_t startpa, endpa; 360 vaddr_t va; 361 362 #ifdef PCI_DEBUG 363 printf("sspci_bs_map: t=%p, addr=%lx, size=%lx, flag=%d\n", 364 t, bpa, size, flag); 365 #endif 366 367 /* Round the allocation to page boundries */ 368 startpa = trunc_page(bpa); 369 endpa = round_page(bpa + size); 370 371 /* Get some VM. */ 372 va = uvm_km_valloc(kernel_map, endpa - startpa); 373 if (va == 0) 374 return ENOMEM; 375 376 /* Store the bus space handle */ 377 *bshp = va + (bpa & PGOFSET); 378 379 /* Now map the pages */ 380 /* The cookie is the physical base address for PCI I/O or memory area */ 381 while (startpa < endpa) { 382 /* XXX pmap_kenter_pa maps pages cacheable -- not what we 383 * want. */ 384 pmap_enter(pmap_kernel(), va, (bus_addr_t) t + startpa, 385 VM_PROT_READ | VM_PROT_WRITE, 0); 386 va += PAGE_SIZE; 387 startpa += PAGE_SIZE; 388 } 389 pmap_update(pmap_kernel()); 390 391 return 0; 392 } 393 394 395 396 void 397 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int func, 398 int swiz, int *iline) 399 { 400 #ifdef PCI_DEBUG 401 printf("pci_conf_interrupt(pc(%lx), bus(%d), dev(%d), func(%d), swiz(%d), *iline(%p)\n", (unsigned long) pc, bus, dev, func, swiz, iline); 402 #endif 403 if (bus == 0) { 404 *iline = dev; 405 } else { 406 panic("pci_conf_interrupt: bus=%d: not yet implemented", bus); 407 } 408 } 409 410 void 411 s3c2800_pci_attach_hook(struct device * parent, struct device * self, 412 struct pcibus_attach_args * pba) 413 { 414 415 /* Nothing to do. */ 416 #ifdef PCI_DEBUG 417 printf("s3c2800_pci_attach_hook()\n"); 418 #endif 419 } 420 421 int 422 s3c2800_pci_bus_maxdevs(void *v, int busno) 423 { 424 425 #ifdef PCI_DEBUG 426 printf("s3c2800_pci_bus_maxdevs(v=%p, busno=%d)\n", v, busno); 427 #endif 428 return (32); 429 } 430 pcitag_t 431 s3c2800_pci_make_tag(void *v, int bus, int device, int function) 432 { 433 434 return ((bus << BUSNO_SHIFT) | (device << DEVNO_SHIFT) | 435 (function << FUNNO_SHIFT)); 436 } 437 438 void 439 s3c2800_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 440 { 441 if (bp != NULL) 442 *bp = (tag >> BUSNO_SHIFT) & 0xff; 443 if (dp != NULL) 444 *dp = (tag >> DEVNO_SHIFT) & 0x1f; 445 if (fp != NULL) 446 *fp = (tag >> FUNNO_SHIFT) & 0x7; 447 } 448 449 static vaddr_t 450 make_pci_conf_va(struct sspci_softc * sc, pcitag_t tag, int offset) 451 { 452 if ((tag & BUSNO_MASK) == 0) { 453 /* configuration type 0 */ 454 int devno = tag_to_devno(tag); 455 456 if (devno < BUS0_DEV_MIN || BUS0_DEV_MAX < devno) 457 return 0; 458 459 return (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 460 (tag & (DEVNO_MASK | FUNNO_MASK)) + offset; 461 } else { 462 /* XXX */ 463 return (vaddr_t) - 1; /* cause fault */ 464 } 465 } 466 467 468 pcireg_t 469 s3c2800_pci_conf_read(void *v, pcitag_t tag, int offset) 470 { 471 struct sspci_softc *sc = v; 472 vaddr_t va = make_pci_conf_va(sc, tag, offset); 473 int s; 474 pcireg_t rv; 475 476 #ifdef PCI_DEBUG 477 printf("s3c2800_pci_conf_read: base=%lx tag=%lx offset=%x\n", 478 sc->sc_conf0_ioh, tag, offset); 479 #endif 480 if (va == 0) 481 return -1; 482 483 PCI_CONF_LOCK(s); 484 485 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 486 #if PCI_DEBUG 487 printf("conf_read: %lx bad address\n", va); 488 #endif 489 rv = (pcireg_t) - 1; 490 } 491 PCI_CONF_UNLOCK(s); 492 493 return rv; 494 } 495 496 void 497 s3c2800_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 498 { 499 struct sspci_softc *sc = v; 500 vaddr_t va = make_pci_conf_va(sc, tag, offset); 501 u_int s; 502 503 #ifdef PCI_DEBUG 504 printf("s3c2800_pci_conf_write: tag=%lx offset=%x -> va=%lx\n", tag, offset, va); 505 #endif 506 507 PCI_CONF_LOCK(s); 508 509 *(pcireg_t *) va = val; 510 511 PCI_CONF_UNLOCK(s); 512 } 513 514 void * 515 s3c2800_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level, 516 int (*func) (void *), void *arg) 517 { 518 struct sspci_softc *sc = pcv; 519 struct sspci_irq_handler *handler; 520 int s; 521 522 #ifdef PCI_DEBUG 523 printf("s3c2800_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, " 524 "func=%p, arg=%p)\n", pcv, ih, level, func, arg); 525 #endif 526 527 handler = malloc(sizeof *handler, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 528 if (handler == NULL) 529 panic("sspci_intr_establish: can't malloc handler info"); 530 531 handler->func = func; 532 handler->arg = arg; 533 handler->level = level; 534 535 s = splhigh(); 536 SLIST_INSERT_HEAD(&sc->sc_irq_handlers, handler, link); 537 splx(s); 538 539 return (handler); 540 } 541 542 void 543 s3c2800_pci_intr_disestablish(void *pcv, void *cookie) 544 { 545 struct sspci_softc *sc = pcv; 546 struct sspci_irq_handler *ih = cookie; 547 int s; 548 549 #ifdef PCI_DEBUG 550 printf("s3c2800_pci_intr_disestablish(pcv=%p, cookie=%p)\n", 551 pcv, cookie); 552 #endif 553 554 s = splhigh(); 555 SLIST_REMOVE(&sc->sc_irq_handlers, ih, sspci_irq_handler, link); 556 splx(s); 557 } 558 559 int 560 s3c2800_pci_intr_map(struct pci_attach_args * pa, pci_intr_handle_t * ihp) 561 { 562 #ifdef PCI_DEBUG 563 int pin = pa->pa_intrpin; 564 void *pcv = pa->pa_pc; 565 pcitag_t intrtag = pa->pa_intrtag; 566 int bus, device, function; 567 568 s3c2800_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 569 printf("s3c2800_pci_intr_map: pcv=%p, tag=%08lx pin=%d dev=%d\n", 570 pcv, intrtag, pin, device); 571 #endif 572 573 574 /* S3C2800 has only one interrupt line for PCI */ 575 *ihp = 0; 576 return 0; 577 } 578 579 const char * 580 s3c2800_pci_intr_string(void *pcv, pci_intr_handle_t ih) 581 { 582 /* We have only one interrupt source from PCI */ 583 return "pciint"; 584 } 585 586 const struct evcnt * 587 s3c2800_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih) 588 { 589 590 /* XXX for now, no evcnt parent reported */ 591 return NULL; 592 } 593 /* 594 * Initialize PCI controller 595 */ 596 int 597 sspci_init_controller(struct sspci_softc * sc) 598 { 599 bus_space_tag_t iot = sc->sc_iot; 600 bus_space_handle_t ioh = sc->sc_reg_ioh; 601 602 /* disable PCI command */ 603 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 604 0xffff0000); 605 606 /* latency=0x10, cacheline=8 */ 607 bus_space_write_4(iot, ioh, PCI_BHLC_REG, 608 PCI_BHLC_CODE(0, 0, 0, 0x10, 8)); 609 610 bus_space_write_4(iot, ioh, PCI_INTERRUPT_REG, 611 PCI_INTERRUPT_CODE(0, 0, 0, 0)); 612 613 614 615 #if 1 616 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 617 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 618 /* Cover all DBANKs with BAR0 */ 619 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xf8000000); 620 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, S3C2800_DBANK0_START); 621 #else 622 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 623 PCI_MAPREG_MEM_TYPE_32BIT | 0xf0000000); 624 bus_space_write_4(iot, ioh, PCI_MAPREG_START + 4, 625 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 626 627 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xffff0000); 628 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, 0xffff0000); 629 bus_space_write_4(iot, ioh, PCICTL_PCIBAM1, 0xf1000000); 630 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA1, S3C2800_DBANK0_START); 631 #endif 632 633 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 634 PCI_STATUS_PARITY_DETECT | 635 PCI_STATUS_SPECIAL_ERROR | 636 PCI_STATUS_MASTER_ABORT | 637 PCI_STATUS_MASTER_TARGET_ABORT | 638 PCI_STATUS_TARGET_TARGET_ABORT | 639 PCI_STATUS_DEVSEL_MEDIUM | 640 PCI_STATUS_PARITY_ERROR | 641 PCI_STATUS_BACKTOBACK_SUPPORT | 642 PCI_STATUS_CAPLIST_SUPPORT | 643 PCI_COMMAND_MASTER_ENABLE | 644 PCI_COMMAND_MEM_ENABLE | 645 PCI_COMMAND_IO_ENABLE); 646 647 bus_space_write_4(iot, ioh, PCICTL_PCICON, 648 PCICON_ARB | PCICON_HST); 649 650 bus_space_write_4(iot, ioh, PCICTL_PCISET, 0); 651 /* clear all interrupts */ 652 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, 0xffffffff); 653 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 0); 654 655 bus_space_write_4(iot, ioh, PCICTL_PCICON, 656 PCICON_RDY | PCICON_CFD | PCICON_ATS | 657 PCICON_ARB | PCICON_HST); 658 659 660 #ifdef PCI_DEBUG 661 { 662 pcireg_t reg; 663 int i; 664 665 for (i = 0; i <= 0x40; i += sizeof(pcireg_t)) { 666 reg = bus_space_read_4(iot, ioh, i); 667 printf("%03x: %08x\n", i, reg); 668 } 669 for (i = 0x100; i <= 0x154; i += sizeof(pcireg_t)) { 670 reg = bus_space_read_4(iot, ioh, i); 671 printf("%03x: %08x\n", i, reg); 672 } 673 } 674 #endif 675 return 0; 676 } 677 678 679 static const char *pci_abnormal_error_name[] = { 680 "PCI reset deasserted", 681 "PCI reset asserted", 682 "PCI master detected fatal error", 683 "PCI master detected parity error", 684 "PCI target detected parity error", 685 "PCI SERR# asserted", 686 }; 687 688 static int 689 sspci_intr(void *arg) 690 { 691 struct sspci_softc *sc = arg; 692 int s; 693 bus_space_tag_t iot = sc->sc_iot; 694 bus_space_handle_t ioh = sc->sc_reg_ioh; 695 uint32_t interrupts, errors; 696 697 interrupts = bus_space_read_4(iot, ioh, PCICTL_PCIINTST); 698 699 if (interrupts & PCIINT_INA) { 700 s = splhigh(); 701 softintr_schedule(sc->sc_softinterrupt); 702 703 /* mask INTA itnerrupt until softinterrupt is handled */ 704 sc->sc_pciinten &= ~PCIINT_INA; 705 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 706 sc->sc_pciinten); 707 708 /* acknowledge INTA interrupt */ 709 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, PCIINT_INA); 710 711 splx(s); 712 713 interrupts &= ~PCIINT_INA; 714 715 } 716 errors = interrupts & (PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 717 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD); 718 if (errors) { 719 int i; 720 721 for (i = 0; errors; ++i) { 722 if ((errors & (1 << i)) == 0) 723 continue; 724 725 printf("%s: %s\n", sc->sc_dev.dv_xname, 726 pci_abnormal_error_name[i > 4 ? 5 : i]); 727 728 errors &= ~(1 << i); 729 } 730 /* acknowledge interrupts */ 731 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, interrupts); 732 } 733 return 0; 734 } 735 736 static void 737 sspci_softintr(void *arg) 738 { 739 struct sspci_softc *sc = arg; 740 struct sspci_irq_handler *ih; 741 int s; 742 743 744 SLIST_FOREACH(ih, &(sc->sc_irq_handlers), link) { 745 s = _splraise(ih->level); 746 ih->func(ih->arg); 747 splx(s); 748 } 749 750 /* unmask INTA interrupt */ 751 s = splhigh(); 752 sc->sc_pciinten |= PCIINT_INA; 753 bus_space_write_4(sc->sc_iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 754 sc->sc_pciinten); 755 splx(s); 756 } 757
Indexes created Wed Oct 01 07:09:59 GMT 2025