s3c2xx0_intr.c revision 1.3
1 /* $NetBSD: s3c2xx0_intr.c,v 1.3 2003/06/16 20:00:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * Common part of IRQ handlers for Samsung S3C2800/2400/2410 processors. 37 * derived from i80321_icu.c 38 */ 39 40 /* 41 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 42 * All rights reserved. 43 * 44 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed for the NetBSD Project by 57 * Wasabi Systems, Inc. 58 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 59 * or promote products derived from this software without specific prior 60 * written permission. 61 * 62 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 64 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 65 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 66 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 67 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 68 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 69 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 70 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 71 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 72 * POSSIBILITY OF SUCH DAMAGE. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/malloc.h> 78 #include <uvm/uvm_extern.h> 79 #include <machine/bus.h> 80 #include <machine/intr.h> 81 #include <arm/cpufunc.h> 82 83 #include <arm/s3c2xx0/s3c2xx0reg.h> 84 #include <arm/s3c2xx0/s3c2xx0var.h> 85 86 volatile uint32_t *s3c2xx0_intr_mask_reg; 87 88 static __inline void 89 __raise(int ipl) 90 { 91 if (current_spl_level < ipl) { 92 s3c2xx0_setipl(ipl); 93 } 94 } 95 /* 96 * modify interrupt mask table for SPL levels 97 */ 98 void 99 s3c2xx0_update_intr_masks(int irqno, int level) 100 { 101 int mask = 1 << irqno; 102 int i; 103 104 105 s3c2xx0_ilevel[irqno] = level; 106 107 for (i = 0; i < level; ++i) 108 s3c2xx0_imask[i] |= mask; /* Enable interrupt at lower 109 * level */ 110 for (; i < NIPL - 1; ++i) 111 s3c2xx0_imask[i] &= ~mask; /* Disable itnerrupt at upper 112 * level */ 113 114 /* 115 * Enforce a heirarchy that gives "slow" device (or devices with 116 * limited input buffer space/"real-time" requirements) a better 117 * chance at not dropping data. 118 */ 119 s3c2xx0_imask[IPL_BIO] &= s3c2xx0_imask[IPL_SOFTNET]; 120 s3c2xx0_imask[IPL_NET] &= s3c2xx0_imask[IPL_BIO]; 121 s3c2xx0_imask[IPL_SOFTSERIAL] &= s3c2xx0_imask[IPL_NET]; 122 s3c2xx0_imask[IPL_TTY] &= s3c2xx0_imask[IPL_SOFTSERIAL]; 123 124 /* 125 * splvm() blocks all interrupts that use the kernel memory 126 * allocation facilities. 127 */ 128 s3c2xx0_imask[IPL_VM] &= s3c2xx0_imask[IPL_TTY]; 129 130 /* 131 * Audio devices are not allowed to perform memory allocation 132 * in their interrupt routines, and they have fairly "real-time" 133 * requirements, so give them a high interrupt priority. 134 */ 135 s3c2xx0_imask[IPL_AUDIO] &= s3c2xx0_imask[IPL_VM]; 136 137 /* 138 * splclock() must block anything that uses the scheduler. 139 */ 140 s3c2xx0_imask[IPL_CLOCK] &= s3c2xx0_imask[IPL_AUDIO]; 141 142 /* 143 * splhigh() must block "everything". 144 */ 145 s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_STATCLOCK]; 146 147 /* 148 * XXX We need serial drivers to run at the absolute highest priority 149 * in order to avoid overruns, so serial > high. 150 */ 151 s3c2xx0_imask[IPL_SERIAL] &= s3c2xx0_imask[IPL_HIGH]; 152 153 } 154 155 156 static void 157 init_interrupt_masks(void) 158 { 159 int i; 160 s3c2xx0_imask[IPL_NONE] = 0xffffffff; 161 162 for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i) 163 s3c2xx0_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL); 164 for (; i < NIPL; ++i) 165 s3c2xx0_imask[i] = 0; 166 167 /* 168 * Initialize the soft interrupt masks to block themselves. 169 */ 170 s3c2xx0_imask[IPL_SOFT] = ~SI_TO_IRQBIT(SI_SOFT); 171 s3c2xx0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK); 172 s3c2xx0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET); 173 174 /* 175 * splsoftclock() is the only interface that users of the 176 * generic software interrupt facility have to block their 177 * soft intrs, so splsoftclock() must also block IPL_SOFT. 178 */ 179 s3c2xx0_imask[IPL_SOFTCLOCK] &= s3c2xx0_imask[IPL_SOFT]; 180 181 /* 182 * splsoftnet() must also block splsoftclock(), since we don't 183 * want timer-driven network events to occur while we're 184 * processing incoming packets. 185 */ 186 s3c2xx0_imask[IPL_SOFTNET] &= s3c2xx0_imask[IPL_SOFTCLOCK]; 187 188 } 189 190 191 /* 192 * Disable/enable interrupts. 193 * This is for S3C2XX0's intergrated UART, which can't disable tx/rx 194 * interrupts without disabling tx/rx by means of UART regsiters. 195 */ 196 void 197 s3c2xx0_mask_interrupts(int mask) 198 { 199 int save = disable_interrupts(I32_bit); 200 int i; 201 202 for (i = 0; i < NIPL - 1; ++i) 203 s3c2xx0_imask[i] &= ~mask; 204 205 intr_mask = s3c2xx0_imask[current_spl_level]; 206 *s3c2xx0_intr_mask_reg = intr_mask; 207 208 restore_interrupts(save); 209 } 210 211 void 212 s3c2xx0_unmask_interrupts(int mask) 213 { 214 int save = disable_interrupts(I32_bit); 215 int i; 216 217 for (i = 0; i < ICU_LEN; ++i) { 218 if ((mask & (1 << i)) == 0) 219 continue; 220 s3c2xx0_update_intr_masks(i, s3c2xx0_ilevel[i]); 221 } 222 223 intr_mask = s3c2xx0_imask[current_spl_level]; 224 *s3c2xx0_intr_mask_reg = intr_mask; 225 226 restore_interrupts(save); 227 } 228 229 void 230 s3c2xx0_do_pending(void) 231 { 232 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 233 int oldirqstate, spl_save; 234 235 if (__cpu_simple_lock_try(&processing) == 0) 236 return; 237 238 spl_save = current_spl_level; 239 240 oldirqstate = disable_interrupts(I32_bit); 241 242 #define DO_SOFTINT(si,ipl) \ 243 if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \ 244 softint_pending &= ~SI_TO_IRQBIT(si); \ 245 __raise(ipl); \ 246 restore_interrupts(oldirqstate); \ 247 softintr_dispatch(si); \ 248 oldirqstate = disable_interrupts(I32_bit); \ 249 s3c2xx0_setipl(spl_save); \ 250 } 251 252 do { 253 DO_SOFTINT(SI_SOFTSERIAL, IPL_SOFTSERIAL); 254 DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET); 255 DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK); 256 DO_SOFTINT(SI_SOFT, IPL_SOFT); 257 } while (softint_pending & intr_mask); 258 259 __cpu_simple_unlock(&processing); 260 261 restore_interrupts(oldirqstate); 262 } 263 264 265 static int 266 stray_interrupt(void *cookie) 267 { 268 int save; 269 int irqno = (int) cookie; 270 printf("stray interrupt %d\n", irqno); 271 272 save = disable_interrupts(I32_bit); 273 *s3c2xx0_intr_mask_reg &= ~(1U << irqno); 274 restore_interrupts(save); 275 276 return 0; 277 } 278 /* 279 * Initialize interrupt dispatcher. 280 */ 281 void 282 s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch * dispatch_table, int icu_len) 283 { 284 int i; 285 286 for (i = 0; i < icu_len; ++i) { 287 dispatch_table[i].func = stray_interrupt; 288 dispatch_table[i].cookie = (void *) (i); 289 dispatch_table[i].level = IPL_BIO; 290 } 291 292 init_interrupt_masks(); 293 294 _splraise(IPL_SERIAL); 295 enable_interrupts(I32_bit); 296 } 297 #undef splx 298 void 299 splx(int ipl) 300 { 301 s3c2xx0_splx(ipl); 302 } 303 #undef _splraise 304 int 305 _splraise(int ipl) 306 { 307 return s3c2xx0_splraise(ipl); 308 } 309 #undef _spllower 310 int 311 _spllower(int ipl) 312 { 313 return s3c2xx0_spllower(ipl); 314 } 315 #undef _setsoftintr 316 void 317 _setsoftintr(int si) 318 { 319 return s3c2xx0_setsoftintr(si); 320 } 321
Indexes created Tue Sep 30 11:09:46 GMT 2025