s3c2xx0_intr.c revision 1.4
1 /* $NetBSD: s3c2xx0_intr.c,v 1.4 2003/07/15 00:24:49 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * Common part of IRQ handlers for Samsung S3C2800/2400/2410 processors. 37 * derived from i80321_icu.c 38 */ 39 40 /* 41 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 42 * All rights reserved. 43 * 44 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed for the NetBSD Project by 57 * Wasabi Systems, Inc. 58 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 59 * or promote products derived from this software without specific prior 60 * written permission. 61 * 62 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 64 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 65 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 66 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 67 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 68 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 69 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 70 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 71 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 72 * POSSIBILITY OF SUCH DAMAGE. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: s3c2xx0_intr.c,v 1.4 2003/07/15 00:24:49 lukem Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/malloc.h> 81 #include <uvm/uvm_extern.h> 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 #include <arm/cpufunc.h> 85 86 #include <arm/s3c2xx0/s3c2xx0reg.h> 87 #include <arm/s3c2xx0/s3c2xx0var.h> 88 89 volatile uint32_t *s3c2xx0_intr_mask_reg; 90 91 static __inline void 92 __raise(int ipl) 93 { 94 if (current_spl_level < ipl) { 95 s3c2xx0_setipl(ipl); 96 } 97 } 98 /* 99 * modify interrupt mask table for SPL levels 100 */ 101 void 102 s3c2xx0_update_intr_masks(int irqno, int level) 103 { 104 int mask = 1 << irqno; 105 int i; 106 107 108 s3c2xx0_ilevel[irqno] = level; 109 110 for (i = 0; i < level; ++i) 111 s3c2xx0_imask[i] |= mask; /* Enable interrupt at lower 112 * level */ 113 for (; i < NIPL - 1; ++i) 114 s3c2xx0_imask[i] &= ~mask; /* Disable itnerrupt at upper 115 * level */ 116 117 /* 118 * Enforce a heirarchy that gives "slow" device (or devices with 119 * limited input buffer space/"real-time" requirements) a better 120 * chance at not dropping data. 121 */ 122 s3c2xx0_imask[IPL_BIO] &= s3c2xx0_imask[IPL_SOFTNET]; 123 s3c2xx0_imask[IPL_NET] &= s3c2xx0_imask[IPL_BIO]; 124 s3c2xx0_imask[IPL_SOFTSERIAL] &= s3c2xx0_imask[IPL_NET]; 125 s3c2xx0_imask[IPL_TTY] &= s3c2xx0_imask[IPL_SOFTSERIAL]; 126 127 /* 128 * splvm() blocks all interrupts that use the kernel memory 129 * allocation facilities. 130 */ 131 s3c2xx0_imask[IPL_VM] &= s3c2xx0_imask[IPL_TTY]; 132 133 /* 134 * Audio devices are not allowed to perform memory allocation 135 * in their interrupt routines, and they have fairly "real-time" 136 * requirements, so give them a high interrupt priority. 137 */ 138 s3c2xx0_imask[IPL_AUDIO] &= s3c2xx0_imask[IPL_VM]; 139 140 /* 141 * splclock() must block anything that uses the scheduler. 142 */ 143 s3c2xx0_imask[IPL_CLOCK] &= s3c2xx0_imask[IPL_AUDIO]; 144 145 /* 146 * splhigh() must block "everything". 147 */ 148 s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_STATCLOCK]; 149 150 /* 151 * XXX We need serial drivers to run at the absolute highest priority 152 * in order to avoid overruns, so serial > high. 153 */ 154 s3c2xx0_imask[IPL_SERIAL] &= s3c2xx0_imask[IPL_HIGH]; 155 156 } 157 158 159 static void 160 init_interrupt_masks(void) 161 { 162 int i; 163 s3c2xx0_imask[IPL_NONE] = 0xffffffff; 164 165 for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i) 166 s3c2xx0_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL); 167 for (; i < NIPL; ++i) 168 s3c2xx0_imask[i] = 0; 169 170 /* 171 * Initialize the soft interrupt masks to block themselves. 172 */ 173 s3c2xx0_imask[IPL_SOFT] = ~SI_TO_IRQBIT(SI_SOFT); 174 s3c2xx0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK); 175 s3c2xx0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET); 176 177 /* 178 * splsoftclock() is the only interface that users of the 179 * generic software interrupt facility have to block their 180 * soft intrs, so splsoftclock() must also block IPL_SOFT. 181 */ 182 s3c2xx0_imask[IPL_SOFTCLOCK] &= s3c2xx0_imask[IPL_SOFT]; 183 184 /* 185 * splsoftnet() must also block splsoftclock(), since we don't 186 * want timer-driven network events to occur while we're 187 * processing incoming packets. 188 */ 189 s3c2xx0_imask[IPL_SOFTNET] &= s3c2xx0_imask[IPL_SOFTCLOCK]; 190 191 } 192 193 194 /* 195 * Disable/enable interrupts. 196 * This is for S3C2XX0's intergrated UART, which can't disable tx/rx 197 * interrupts without disabling tx/rx by means of UART regsiters. 198 */ 199 void 200 s3c2xx0_mask_interrupts(int mask) 201 { 202 int save = disable_interrupts(I32_bit); 203 int i; 204 205 for (i = 0; i < NIPL - 1; ++i) 206 s3c2xx0_imask[i] &= ~mask; 207 208 intr_mask = s3c2xx0_imask[current_spl_level]; 209 *s3c2xx0_intr_mask_reg = intr_mask; 210 211 restore_interrupts(save); 212 } 213 214 void 215 s3c2xx0_unmask_interrupts(int mask) 216 { 217 int save = disable_interrupts(I32_bit); 218 int i; 219 220 for (i = 0; i < ICU_LEN; ++i) { 221 if ((mask & (1 << i)) == 0) 222 continue; 223 s3c2xx0_update_intr_masks(i, s3c2xx0_ilevel[i]); 224 } 225 226 intr_mask = s3c2xx0_imask[current_spl_level]; 227 *s3c2xx0_intr_mask_reg = intr_mask; 228 229 restore_interrupts(save); 230 } 231 232 void 233 s3c2xx0_do_pending(void) 234 { 235 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 236 int oldirqstate, spl_save; 237 238 if (__cpu_simple_lock_try(&processing) == 0) 239 return; 240 241 spl_save = current_spl_level; 242 243 oldirqstate = disable_interrupts(I32_bit); 244 245 #define DO_SOFTINT(si,ipl) \ 246 if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \ 247 softint_pending &= ~SI_TO_IRQBIT(si); \ 248 __raise(ipl); \ 249 restore_interrupts(oldirqstate); \ 250 softintr_dispatch(si); \ 251 oldirqstate = disable_interrupts(I32_bit); \ 252 s3c2xx0_setipl(spl_save); \ 253 } 254 255 do { 256 DO_SOFTINT(SI_SOFTSERIAL, IPL_SOFTSERIAL); 257 DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET); 258 DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK); 259 DO_SOFTINT(SI_SOFT, IPL_SOFT); 260 } while (softint_pending & intr_mask); 261 262 __cpu_simple_unlock(&processing); 263 264 restore_interrupts(oldirqstate); 265 } 266 267 268 static int 269 stray_interrupt(void *cookie) 270 { 271 int save; 272 int irqno = (int) cookie; 273 printf("stray interrupt %d\n", irqno); 274 275 save = disable_interrupts(I32_bit); 276 *s3c2xx0_intr_mask_reg &= ~(1U << irqno); 277 restore_interrupts(save); 278 279 return 0; 280 } 281 /* 282 * Initialize interrupt dispatcher. 283 */ 284 void 285 s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch * dispatch_table, int icu_len) 286 { 287 int i; 288 289 for (i = 0; i < icu_len; ++i) { 290 dispatch_table[i].func = stray_interrupt; 291 dispatch_table[i].cookie = (void *) (i); 292 dispatch_table[i].level = IPL_BIO; 293 } 294 295 init_interrupt_masks(); 296 297 _splraise(IPL_SERIAL); 298 enable_interrupts(I32_bit); 299 } 300 #undef splx 301 void 302 splx(int ipl) 303 { 304 s3c2xx0_splx(ipl); 305 } 306 #undef _splraise 307 int 308 _splraise(int ipl) 309 { 310 return s3c2xx0_splraise(ipl); 311 } 312 #undef _spllower 313 int 314 _spllower(int ipl) 315 { 316 return s3c2xx0_spllower(ipl); 317 } 318 #undef _setsoftintr 319 void 320 _setsoftintr(int si) 321 { 322 return s3c2xx0_setsoftintr(si); 323 } 324
Indexes created Tue Sep 30 11:09:46 GMT 2025