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s3c2xx0_intr.h revision 1.12
      1  1.12   matt /*	$NetBSD: s3c2xx0_intr.h,v 1.12 2008/04/27 18:58:45 matt Exp $ */
      2   1.1    bsh 
      3   1.1    bsh /*
      4   1.3    bsh  * Copyright (c) 2002, 2003 Fujitsu Component Limited
      5   1.3    bsh  * Copyright (c) 2002, 2003 Genetec Corporation
      6   1.1    bsh  * All rights reserved.
      7   1.1    bsh  *
      8   1.1    bsh  * Redistribution and use in source and binary forms, with or without
      9   1.1    bsh  * modification, are permitted provided that the following conditions
     10   1.1    bsh  * are met:
     11   1.1    bsh  * 1. Redistributions of source code must retain the above copyright
     12   1.1    bsh  *    notice, this list of conditions and the following disclaimer.
     13   1.1    bsh  * 2. Redistributions in binary form must reproduce the above copyright
     14   1.1    bsh  *    notice, this list of conditions and the following disclaimer in the
     15   1.1    bsh  *    documentation and/or other materials provided with the distribution.
     16   1.1    bsh  * 3. Neither the name of The Fujitsu Component Limited nor the name of
     17   1.1    bsh  *    Genetec corporation may not be used to endorse or promote products
     18   1.1    bsh  *    derived from this software without specific prior written permission.
     19   1.1    bsh  *
     20   1.1    bsh  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
     21   1.1    bsh  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     22   1.1    bsh  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     23   1.1    bsh  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     24   1.1    bsh  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
     25   1.1    bsh  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26   1.1    bsh  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     27   1.1    bsh  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     28   1.1    bsh  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     29   1.1    bsh  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     30   1.1    bsh  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     31   1.1    bsh  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32   1.1    bsh  * SUCH DAMAGE.
     33   1.1    bsh  */
     34   1.1    bsh 
     35   1.1    bsh /* Derived from i80321_intr.h */
     36   1.1    bsh 
     37   1.1    bsh /*
     38   1.1    bsh  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
     39   1.1    bsh  * All rights reserved.
     40   1.1    bsh  *
     41   1.1    bsh  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
     42   1.1    bsh  *
     43   1.1    bsh  * Redistribution and use in source and binary forms, with or without
     44   1.1    bsh  * modification, are permitted provided that the following conditions
     45   1.1    bsh  * are met:
     46   1.1    bsh  * 1. Redistributions of source code must retain the above copyright
     47   1.1    bsh  *    notice, this list of conditions and the following disclaimer.
     48   1.1    bsh  * 2. Redistributions in binary form must reproduce the above copyright
     49   1.1    bsh  *    notice, this list of conditions and the following disclaimer in the
     50   1.1    bsh  *    documentation and/or other materials provided with the distribution.
     51   1.1    bsh  * 3. All advertising materials mentioning features or use of this software
     52   1.1    bsh  *    must display the following acknowledgement:
     53   1.1    bsh  *	This product includes software developed for the NetBSD Project by
     54   1.1    bsh  *	Wasabi Systems, Inc.
     55   1.1    bsh  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     56   1.1    bsh  *    or promote products derived from this software without specific prior
     57   1.1    bsh  *    written permission.
     58   1.1    bsh  *
     59   1.1    bsh  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     60   1.1    bsh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     61   1.1    bsh  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     62   1.1    bsh  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     63   1.1    bsh  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     64   1.1    bsh  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     65   1.1    bsh  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     66   1.1    bsh  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     67   1.1    bsh  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     68   1.1    bsh  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     69   1.1    bsh  * POSSIBILITY OF SUCH DAMAGE.
     70   1.1    bsh  */
     71   1.1    bsh 
     72   1.1    bsh #ifndef _S3C2XX0_INTR_H_
     73   1.1    bsh #define _S3C2XX0_INTR_H_
     74   1.1    bsh 
     75   1.1    bsh #include <arm/cpu.h>
     76   1.1    bsh #include <arm/armreg.h>
     77   1.1    bsh #include <arm/cpufunc.h>
     78   1.1    bsh #include <machine/atomic.h>
     79   1.1    bsh #include <machine/intr.h>
     80   1.1    bsh 
     81   1.1    bsh #include <arm/s3c2xx0/s3c2xx0reg.h>
     82   1.1    bsh 
     83   1.1    bsh typedef int (* s3c2xx0_irq_handler_t)(void *);
     84   1.1    bsh 
     85   1.1    bsh extern volatile uint32_t *s3c2xx0_intr_mask_reg;
     86   1.1    bsh 
     87  1.10  perry extern volatile int intr_mask;
     88  1.10  perry extern volatile int global_intr_mask;
     89  1.11   matt #ifdef __HAVE_FAST_SOFTINTS
     90  1.10  perry extern volatile int softint_pending;
     91  1.11   matt #endif
     92   1.1    bsh extern int s3c2xx0_imask[];
     93   1.1    bsh extern int s3c2xx0_ilevel[];
     94   1.1    bsh 
     95   1.1    bsh void s3c2xx0_update_intr_masks( int, int );
     96   1.3    bsh 
     97  1.10  perry static inline void
     98   1.3    bsh s3c2xx0_mask_interrupts(int mask)
     99   1.3    bsh {
    100   1.3    bsh 	int save = disable_interrupts(I32_bit);
    101   1.4    bsh 	global_intr_mask &= ~mask;
    102   1.4    bsh 	s3c2xx0_update_hw_mask();
    103   1.3    bsh 	restore_interrupts(save);
    104   1.3    bsh }
    105   1.3    bsh 
    106  1.10  perry static inline void
    107   1.3    bsh s3c2xx0_unmask_interrupts(int mask)
    108   1.3    bsh {
    109   1.3    bsh 	int save = disable_interrupts(I32_bit);
    110   1.4    bsh 	global_intr_mask |= mask;
    111   1.4    bsh 	s3c2xx0_update_hw_mask();
    112   1.3    bsh 	restore_interrupts(save);
    113   1.3    bsh }
    114   1.1    bsh 
    115  1.10  perry static inline void
    116   1.1    bsh s3c2xx0_setipl(int new)
    117   1.1    bsh {
    118  1.12   matt 	set_curcpl(new);
    119  1.12   matt 	intr_mask = s3c2xx0_imask[curcpl()];
    120   1.4    bsh 	s3c2xx0_update_hw_mask();
    121  1.11   matt #ifdef __HAVE_FAST_SOFTINTS
    122   1.4    bsh 	update_softintr_mask();
    123  1.11   matt #endif
    124   1.1    bsh }
    125   1.1    bsh 
    126   1.1    bsh 
    127  1.10  perry static inline void
    128   1.1    bsh s3c2xx0_splx(int new)
    129   1.1    bsh {
    130   1.1    bsh 	int psw;
    131   1.1    bsh 
    132   1.1    bsh 	psw = disable_interrupts(I32_bit);
    133   1.1    bsh 	s3c2xx0_setipl(new);
    134   1.1    bsh 	restore_interrupts(psw);
    135   1.1    bsh 
    136  1.11   matt #ifdef __HAVE_FAST_SOFTINTS
    137  1.12   matt 	cpu_dosoftints();
    138  1.11   matt #endif
    139   1.1    bsh }
    140   1.1    bsh 
    141   1.1    bsh 
    142  1.10  perry static inline int
    143   1.1    bsh s3c2xx0_splraise(int ipl)
    144   1.1    bsh {
    145   1.1    bsh 	int	old, psw;
    146   1.1    bsh 
    147  1.12   matt 	old = curcpl();
    148  1.12   matt 	if( ipl > old ){
    149   1.1    bsh 		psw = disable_interrupts(I32_bit);
    150   1.1    bsh 		s3c2xx0_setipl(ipl);
    151   1.1    bsh 		restore_interrupts(psw);
    152   1.1    bsh 	}
    153   1.1    bsh 
    154   1.1    bsh 	return (old);
    155   1.1    bsh }
    156   1.1    bsh 
    157  1.10  perry static inline int
    158   1.1    bsh s3c2xx0_spllower(int ipl)
    159   1.1    bsh {
    160  1.12   matt 	int old = curcpl();
    161   1.1    bsh 	int psw = disable_interrupts(I32_bit);
    162   1.1    bsh 	s3c2xx0_splx(ipl);
    163   1.1    bsh 	restore_interrupts(psw);
    164   1.1    bsh 	return(old);
    165   1.1    bsh }
    166   1.1    bsh 
    167   1.1    bsh int	_splraise(int);
    168   1.1    bsh int	_spllower(int);
    169   1.1    bsh void	splx(int);
    170   1.1    bsh 
    171   1.1    bsh #if !defined(EVBARM_SPL_NOINLINE)
    172   1.1    bsh 
    173   1.7    bsh #define	splx(new)		s3c2xx0_splx(new)
    174   1.1    bsh #define	_spllower(ipl)		s3c2xx0_spllower(ipl)
    175   1.1    bsh #define	_splraise(ipl)		s3c2xx0_splraise(ipl)
    176   1.1    bsh 
    177   1.1    bsh #endif	/* !EVBARM_SPL_NOINTR */
    178   1.1    bsh 
    179   1.1    bsh 
    180   1.1    bsh /*
    181   1.1    bsh  * interrupt dispatch table.
    182   1.1    bsh  */
    183   1.1    bsh #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
    184   1.1    bsh struct intrhand {
    185   1.1    bsh 	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
    186   1.1    bsh 	s3c2xx0_irq_handler_t ih_func;	/* handler */
    187   1.1    bsh 	void *ih_arg;			/* arg for handler */
    188   1.1    bsh };
    189   1.1    bsh #endif
    190   1.1    bsh 
    191   1.1    bsh struct s3c2xx0_intr_dispatch {
    192   1.1    bsh #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
    193   1.1    bsh 	TAILQ_HEAD(,intrhand) list;
    194   1.1    bsh #else
    195   1.1    bsh 	s3c2xx0_irq_handler_t func;
    196   1.1    bsh #endif
    197   1.1    bsh 	void *cookie;		/* NULL for stackframe */
    198   1.1    bsh 	int level;
    199   1.1    bsh 	/* struct evbnt ev; */
    200   1.1    bsh };
    201   1.1    bsh 
    202   1.1    bsh /* used by s3c2{80,40,41}0 interrupt handler */
    203   1.1    bsh void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int );
    204   1.6    bsh 
    205   1.6    bsh /* initialize some variable so that splfoo() doesn't touch ileegal
    206   1.6    bsh    address during bootstrap */
    207   1.6    bsh void s3c2xx0_intr_bootstrap(vaddr_t);
    208   1.1    bsh 
    209   1.5   matt #endif /* _S3C2XX0_INTR_H_ */
    210