s3c2xx0_intr.h revision 1.10.52.1
1 /* $NetBSD: s3c2xx0_intr.h,v 1.10.52.1 2007/11/09 05:37:42 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* Derived from i80321_intr.h */ 36 37 /* 38 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 #ifndef _S3C2XX0_INTR_H_ 73 #define _S3C2XX0_INTR_H_ 74 75 #include <arm/cpu.h> 76 #include <arm/armreg.h> 77 #include <arm/cpufunc.h> 78 #include <machine/atomic.h> 79 #include <machine/intr.h> 80 #include <arm/softintr.h> 81 82 #include <arm/s3c2xx0/s3c2xx0reg.h> 83 84 typedef int (* s3c2xx0_irq_handler_t)(void *); 85 86 extern volatile uint32_t *s3c2xx0_intr_mask_reg; 87 88 extern volatile int intr_mask; 89 extern volatile int global_intr_mask; 90 extern volatile int softint_pending; 91 extern int s3c2xx0_imask[]; 92 extern int s3c2xx0_ilevel[]; 93 94 void s3c2xx0_do_pending(int); 95 void s3c2xx0_update_intr_masks( int, int ); 96 97 static inline void 98 s3c2xx0_mask_interrupts(int mask) 99 { 100 int save = disable_interrupts(I32_bit); 101 global_intr_mask &= ~mask; 102 s3c2xx0_update_hw_mask(); 103 restore_interrupts(save); 104 } 105 106 static inline void 107 s3c2xx0_unmask_interrupts(int mask) 108 { 109 int save = disable_interrupts(I32_bit); 110 global_intr_mask |= mask; 111 s3c2xx0_update_hw_mask(); 112 restore_interrupts(save); 113 } 114 115 static inline void 116 s3c2xx0_setipl(int new) 117 { 118 set_curcpl(new); 119 intr_mask = s3c2xx0_imask[curcpl()]; 120 s3c2xx0_update_hw_mask(); 121 update_softintr_mask(); 122 } 123 124 125 static inline void 126 s3c2xx0_splx(int new) 127 { 128 int psw; 129 130 psw = disable_interrupts(I32_bit); 131 s3c2xx0_setipl(new); 132 restore_interrupts(psw); 133 134 /* If there are software interrupts to process, do it. */ 135 if (get_pending_softint()) 136 s3c2xx0_do_pending(0); 137 } 138 139 140 static inline int 141 s3c2xx0_splraise(int ipl) 142 { 143 int old, psw; 144 145 old = curcpl(); 146 if( ipl > old ){ 147 psw = disable_interrupts(I32_bit); 148 s3c2xx0_setipl(ipl); 149 restore_interrupts(psw); 150 } 151 152 return (old); 153 } 154 155 static inline int 156 s3c2xx0_spllower(int ipl) 157 { 158 int old = curcpl(); 159 int psw = disable_interrupts(I32_bit); 160 s3c2xx0_splx(ipl); 161 restore_interrupts(psw); 162 return(old); 163 } 164 165 static inline void 166 s3c2xx0_setsoftintr(int si) 167 { 168 169 atomic_set_bit( (u_int *)__UNVOLATILE(&softint_pending), 170 SI_TO_IRQBIT(si) ); 171 172 /* Process unmasked pending soft interrupts. */ 173 if (get_pending_softint()) 174 s3c2xx0_do_pending(0); 175 176 } 177 178 179 int _splraise(int); 180 int _spllower(int); 181 void splx(int); 182 void _setsoftintr(int); 183 184 #if !defined(EVBARM_SPL_NOINLINE) 185 186 #define splx(new) s3c2xx0_splx(new) 187 #define _spllower(ipl) s3c2xx0_spllower(ipl) 188 #define _splraise(ipl) s3c2xx0_splraise(ipl) 189 #define _setsoftintr(si) s3c2xx0_setsoftintr(si) 190 191 #endif /* !EVBARM_SPL_NOINTR */ 192 193 194 /* 195 * interrupt dispatch table. 196 */ 197 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 198 struct intrhand { 199 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 200 s3c2xx0_irq_handler_t ih_func; /* handler */ 201 void *ih_arg; /* arg for handler */ 202 }; 203 #endif 204 205 struct s3c2xx0_intr_dispatch { 206 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 207 TAILQ_HEAD(,intrhand) list; 208 #else 209 s3c2xx0_irq_handler_t func; 210 #endif 211 void *cookie; /* NULL for stackframe */ 212 int level; 213 /* struct evbnt ev; */ 214 }; 215 216 /* used by s3c2{80,40,41}0 interrupt handler */ 217 void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int ); 218 219 /* initialize some variable so that splfoo() doesn't touch ileegal 220 address during bootstrap */ 221 void s3c2xx0_intr_bootstrap(vaddr_t); 222 223 #endif /* _S3C2XX0_INTR_H_ */ 224
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