s3c2xx0_intr.h revision 1.11
1 /* $NetBSD: s3c2xx0_intr.h,v 1.11 2008/01/06 01:37:56 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* Derived from i80321_intr.h */ 36 37 /* 38 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 #ifndef _S3C2XX0_INTR_H_ 73 #define _S3C2XX0_INTR_H_ 74 75 #include <arm/cpu.h> 76 #include <arm/armreg.h> 77 #include <arm/cpufunc.h> 78 #include <machine/atomic.h> 79 #include <machine/intr.h> 80 81 #include <arm/s3c2xx0/s3c2xx0reg.h> 82 83 typedef int (* s3c2xx0_irq_handler_t)(void *); 84 85 extern volatile uint32_t *s3c2xx0_intr_mask_reg; 86 87 extern volatile int current_spl_level; 88 extern volatile int intr_mask; 89 extern volatile int global_intr_mask; 90 #ifdef __HAVE_FAST_SOFTINTS 91 extern volatile int softint_pending; 92 #endif 93 extern int s3c2xx0_imask[]; 94 extern int s3c2xx0_ilevel[]; 95 96 #ifdef __HAVE_FAST_SOFTINTS 97 void s3c2xx0_do_pending(int); 98 #endif 99 void s3c2xx0_update_intr_masks( int, int ); 100 101 static inline void 102 s3c2xx0_mask_interrupts(int mask) 103 { 104 int save = disable_interrupts(I32_bit); 105 global_intr_mask &= ~mask; 106 s3c2xx0_update_hw_mask(); 107 restore_interrupts(save); 108 } 109 110 static inline void 111 s3c2xx0_unmask_interrupts(int mask) 112 { 113 int save = disable_interrupts(I32_bit); 114 global_intr_mask |= mask; 115 s3c2xx0_update_hw_mask(); 116 restore_interrupts(save); 117 } 118 119 static inline void 120 s3c2xx0_setipl(int new) 121 { 122 current_spl_level = new; 123 intr_mask = s3c2xx0_imask[current_spl_level]; 124 s3c2xx0_update_hw_mask(); 125 #ifdef __HAVE_FAST_SOFTINTS 126 update_softintr_mask(); 127 #endif 128 } 129 130 131 static inline void 132 s3c2xx0_splx(int new) 133 { 134 int psw; 135 136 psw = disable_interrupts(I32_bit); 137 s3c2xx0_setipl(new); 138 restore_interrupts(psw); 139 140 #ifdef __HAVE_FAST_SOFTINTS 141 /* If there are software interrupts to process, do it. */ 142 if (get_pending_softint()) 143 s3c2xx0_do_pending(0); 144 #endif 145 } 146 147 148 static inline int 149 s3c2xx0_splraise(int ipl) 150 { 151 int old, psw; 152 153 old = current_spl_level; 154 if( ipl > current_spl_level ){ 155 psw = disable_interrupts(I32_bit); 156 s3c2xx0_setipl(ipl); 157 restore_interrupts(psw); 158 } 159 160 return (old); 161 } 162 163 static inline int 164 s3c2xx0_spllower(int ipl) 165 { 166 int old = current_spl_level; 167 int psw = disable_interrupts(I32_bit); 168 s3c2xx0_splx(ipl); 169 restore_interrupts(psw); 170 return(old); 171 } 172 173 #ifdef __HAVE_FAST_SOFTINTS 174 static inline void 175 s3c2xx0_setsoftintr(int si) 176 { 177 178 atomic_set_bit( (u_int *)__UNVOLATILE(&softint_pending), 179 SI_TO_IRQBIT(si) ); 180 181 /* Process unmasked pending soft interrupts. */ 182 if (get_pending_softint()) 183 s3c2xx0_do_pending(0); 184 } 185 #endif 186 187 188 int _splraise(int); 189 int _spllower(int); 190 void splx(int); 191 #ifdef __HAVE_FAST_SOFTINTS 192 void _setsoftintr(int); 193 #endif 194 195 #if !defined(EVBARM_SPL_NOINLINE) 196 197 #define splx(new) s3c2xx0_splx(new) 198 #define _spllower(ipl) s3c2xx0_spllower(ipl) 199 #define _splraise(ipl) s3c2xx0_splraise(ipl) 200 #if 0 201 #define _setsoftintr(si) s3c2xx0_setsoftintr(si) 202 #endif 203 204 #endif /* !EVBARM_SPL_NOINTR */ 205 206 207 /* 208 * interrupt dispatch table. 209 */ 210 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 211 struct intrhand { 212 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 213 s3c2xx0_irq_handler_t ih_func; /* handler */ 214 void *ih_arg; /* arg for handler */ 215 }; 216 #endif 217 218 struct s3c2xx0_intr_dispatch { 219 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 220 TAILQ_HEAD(,intrhand) list; 221 #else 222 s3c2xx0_irq_handler_t func; 223 #endif 224 void *cookie; /* NULL for stackframe */ 225 int level; 226 /* struct evbnt ev; */ 227 }; 228 229 /* used by s3c2{80,40,41}0 interrupt handler */ 230 void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int ); 231 232 /* initialize some variable so that splfoo() doesn't touch ileegal 233 address during bootstrap */ 234 void s3c2xx0_intr_bootstrap(vaddr_t); 235 236 #endif /* _S3C2XX0_INTR_H_ */ 237
Indexes created Thu Oct 02 01:09:59 GMT 2025