s3c2xx0_intr.h revision 1.12 1 /* $NetBSD: s3c2xx0_intr.h,v 1.12 2008/04/27 18:58:45 matt Exp $ */
2
3 /*
4 * Copyright (c) 2002, 2003 Fujitsu Component Limited
5 * Copyright (c) 2002, 2003 Genetec Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 * Genetec corporation may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35 /* Derived from i80321_intr.h */
36
37 /*
38 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
39 * All rights reserved.
40 *
41 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. All advertising materials mentioning features or use of this software
52 * must display the following acknowledgement:
53 * This product includes software developed for the NetBSD Project by
54 * Wasabi Systems, Inc.
55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
56 * or promote products derived from this software without specific prior
57 * written permission.
58 *
59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
69 * POSSIBILITY OF SUCH DAMAGE.
70 */
71
72 #ifndef _S3C2XX0_INTR_H_
73 #define _S3C2XX0_INTR_H_
74
75 #include <arm/cpu.h>
76 #include <arm/armreg.h>
77 #include <arm/cpufunc.h>
78 #include <machine/atomic.h>
79 #include <machine/intr.h>
80
81 #include <arm/s3c2xx0/s3c2xx0reg.h>
82
83 typedef int (* s3c2xx0_irq_handler_t)(void *);
84
85 extern volatile uint32_t *s3c2xx0_intr_mask_reg;
86
87 extern volatile int intr_mask;
88 extern volatile int global_intr_mask;
89 #ifdef __HAVE_FAST_SOFTINTS
90 extern volatile int softint_pending;
91 #endif
92 extern int s3c2xx0_imask[];
93 extern int s3c2xx0_ilevel[];
94
95 void s3c2xx0_update_intr_masks( int, int );
96
97 static inline void
98 s3c2xx0_mask_interrupts(int mask)
99 {
100 int save = disable_interrupts(I32_bit);
101 global_intr_mask &= ~mask;
102 s3c2xx0_update_hw_mask();
103 restore_interrupts(save);
104 }
105
106 static inline void
107 s3c2xx0_unmask_interrupts(int mask)
108 {
109 int save = disable_interrupts(I32_bit);
110 global_intr_mask |= mask;
111 s3c2xx0_update_hw_mask();
112 restore_interrupts(save);
113 }
114
115 static inline void
116 s3c2xx0_setipl(int new)
117 {
118 set_curcpl(new);
119 intr_mask = s3c2xx0_imask[curcpl()];
120 s3c2xx0_update_hw_mask();
121 #ifdef __HAVE_FAST_SOFTINTS
122 update_softintr_mask();
123 #endif
124 }
125
126
127 static inline void
128 s3c2xx0_splx(int new)
129 {
130 int psw;
131
132 psw = disable_interrupts(I32_bit);
133 s3c2xx0_setipl(new);
134 restore_interrupts(psw);
135
136 #ifdef __HAVE_FAST_SOFTINTS
137 cpu_dosoftints();
138 #endif
139 }
140
141
142 static inline int
143 s3c2xx0_splraise(int ipl)
144 {
145 int old, psw;
146
147 old = curcpl();
148 if( ipl > old ){
149 psw = disable_interrupts(I32_bit);
150 s3c2xx0_setipl(ipl);
151 restore_interrupts(psw);
152 }
153
154 return (old);
155 }
156
157 static inline int
158 s3c2xx0_spllower(int ipl)
159 {
160 int old = curcpl();
161 int psw = disable_interrupts(I32_bit);
162 s3c2xx0_splx(ipl);
163 restore_interrupts(psw);
164 return(old);
165 }
166
167 int _splraise(int);
168 int _spllower(int);
169 void splx(int);
170
171 #if !defined(EVBARM_SPL_NOINLINE)
172
173 #define splx(new) s3c2xx0_splx(new)
174 #define _spllower(ipl) s3c2xx0_spllower(ipl)
175 #define _splraise(ipl) s3c2xx0_splraise(ipl)
176
177 #endif /* !EVBARM_SPL_NOINTR */
178
179
180 /*
181 * interrupt dispatch table.
182 */
183 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
184 struct intrhand {
185 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
186 s3c2xx0_irq_handler_t ih_func; /* handler */
187 void *ih_arg; /* arg for handler */
188 };
189 #endif
190
191 struct s3c2xx0_intr_dispatch {
192 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
193 TAILQ_HEAD(,intrhand) list;
194 #else
195 s3c2xx0_irq_handler_t func;
196 #endif
197 void *cookie; /* NULL for stackframe */
198 int level;
199 /* struct evbnt ev; */
200 };
201
202 /* used by s3c2{80,40,41}0 interrupt handler */
203 void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int );
204
205 /* initialize some variable so that splfoo() doesn't touch ileegal
206 address during bootstrap */
207 void s3c2xx0_intr_bootstrap(vaddr_t);
208
209 #endif /* _S3C2XX0_INTR_H_ */
210