s3c2xx0_intr.h revision 1.2
1 /* $NetBSD: s3c2xx0_intr.h,v 1.2 2003/01/02 23:37:59 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* Derived from i80321_intr.h */ 36 37 /* 38 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 #ifndef _S3C2XX0_INTR_H_ 73 #define _S3C2XX0_INTR_H_ 74 75 #include <arm/cpu.h> 76 #include <arm/armreg.h> 77 #include <arm/cpufunc.h> 78 #include <machine/atomic.h> 79 #include <machine/intr.h> 80 #include <arm/softintr.h> 81 82 #include <arm/s3c2xx0/s3c2xx0reg.h> 83 84 typedef int (* s3c2xx0_irq_handler_t)(void *); 85 86 extern volatile uint32_t *s3c2xx0_intr_mask_reg; 87 88 extern __volatile int current_spl_level; 89 extern __volatile int intr_mask; 90 extern __volatile int softint_pending; 91 extern int s3c2xx0_imask[]; 92 extern int s3c2xx0_ilevel[]; 93 94 void s3c2xx0_do_pending(void); 95 void s3c2xx0_update_intr_masks( int, int ); 96 void s3c2xx0_mask_interrupts(int); 97 void s3c2xx0_unmask_interrupts(int); 98 99 static __inline void 100 s3c2xx0_setipl(int new) 101 { 102 current_spl_level = new; 103 intr_mask = s3c2xx0_imask[current_spl_level]; 104 *s3c2xx0_intr_mask_reg = intr_mask; 105 } 106 107 108 static __inline void 109 s3c2xx0_splx(int new) 110 { 111 int psw; 112 113 psw = disable_interrupts(I32_bit); 114 s3c2xx0_setipl(new); 115 restore_interrupts(psw); 116 117 /* If there are software interrupts to process, do it. */ 118 if (softint_pending & intr_mask) 119 s3c2xx0_do_pending(); 120 } 121 122 123 static __inline int 124 s3c2xx0_splraise(int ipl) 125 { 126 int old, psw; 127 128 old = current_spl_level; 129 if( ipl > current_spl_level ){ 130 psw = disable_interrupts(I32_bit); 131 s3c2xx0_setipl(ipl); 132 restore_interrupts(psw); 133 } 134 135 return (old); 136 } 137 138 static __inline int 139 s3c2xx0_spllower(int ipl) 140 { 141 int old = current_spl_level; 142 int psw = disable_interrupts(I32_bit); 143 s3c2xx0_splx(ipl); 144 restore_interrupts(psw); 145 return(old); 146 } 147 148 static __inline void 149 s3c2xx0_setsoftintr(int si) 150 { 151 atomic_set_bit( (u_int *)&softint_pending, SI_TO_IRQBIT(si) ); 152 153 /* Process unmasked pending soft interrupts. */ 154 if ( softint_pending & intr_mask ) 155 s3c2xx0_do_pending(); 156 } 157 158 159 int _splraise(int); 160 int _spllower(int); 161 void splx(int); 162 void _setsoftintr(int); 163 164 #if !defined(EVBARM_SPL_NOINLINE) 165 166 #define splx(new) s3c2xx0_splx(new) 167 #define _spllower(ipl) s3c2xx0_spllower(ipl) 168 #define _splraise(ipl) s3c2xx0_splraise(ipl) 169 #define _setsoftintr(si) s3c2xx0_setsoftintr(si) 170 171 #endif /* !EVBARM_SPL_NOINTR */ 172 173 174 /* 175 * interrupt dispatch table. 176 */ 177 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 178 struct intrhand { 179 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 180 s3c2xx0_irq_handler_t ih_func; /* handler */ 181 void *ih_arg; /* arg for handler */ 182 }; 183 #endif 184 185 struct s3c2xx0_intr_dispatch { 186 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 187 TAILQ_HEAD(,intrhand) list; 188 #else 189 s3c2xx0_irq_handler_t func; 190 #endif 191 void *cookie; /* NULL for stackframe */ 192 int level; 193 /* struct evbnt ev; */ 194 }; 195 196 /* used by s3c2{80,40,41}0 interrupt handler */ 197 void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int ); 198 199 #endif _S3C2XX0_INTR_H_ 200 201
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