sscom_var.h revision 1.10
1 /* $NetBSD: sscom_var.h,v 1.10 2012/01/30 03:28:33 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* derived from sys/dev/ic/comvar.h */ 35 36 /* 37 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #ifndef _ARM_S3C2XX0_SSCOM_VAR_H 67 #define _ARM_S3C2XX0_SSCOM_VAR_H 68 69 #include "opt_multiprocessor.h" 70 #include "opt_lockdebug.h" 71 #include "opt_sscom.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/device.h> 76 #include <sys/termios.h> 77 #include <sys/callout.h> 78 #include <sys/bus.h> 79 80 #ifdef SSCOM_S3C2410 81 #include <arm/s3c2xx0/s3c2410reg.h> 82 #include <arm/s3c2xx0/s3c2410var.h> 83 #elif defined(SSCOM_S3C2440) 84 #include <arm/s3c2xx0/s3c2440reg.h> 85 #include <arm/s3c2xx0/s3c2440var.h> 86 #endif 87 88 /* Hardware flag masks */ 89 #define SSCOM_HW_FLOW 0x02 90 #define SSCOM_HW_DEV_OK 0x04 91 #define SSCOM_HW_CONSOLE 0x08 92 #define SSCOM_HW_KGDB 0x10 93 #define SSCOM_HW_TXINT 0x20 94 #define SSCOM_HW_RXINT 0x40 95 96 /* Buffer size for character buffer */ 97 #define SSCOM_RING_SIZE 2048 98 99 struct sscom_softc { 100 device_t sc_dev; 101 void *sc_si; 102 struct tty *sc_tty; 103 104 struct callout sc_diag_callout; 105 106 int sc_unit; /* UART0/UART1 */ 107 int sc_frequency; 108 109 bus_space_tag_t sc_iot; 110 bus_space_handle_t sc_ioh; 111 112 u_int sc_overflows, 113 sc_floods, 114 sc_errors; 115 116 int sc_hwflags, 117 sc_swflags; 118 119 u_int sc_r_hiwat, 120 sc_r_lowat; 121 u_char *volatile sc_rbget, 122 *volatile sc_rbput; 123 volatile u_int sc_rbavail; 124 u_char *sc_rbuf, 125 *sc_ebuf; 126 127 u_char *sc_tba; 128 u_int sc_tbc, 129 sc_heldtbc; 130 131 volatile u_char sc_rx_flags, 132 #define RX_TTY_BLOCKED 0x01 133 #define RX_TTY_OVERFLOWED 0x02 134 #define RX_IBUF_BLOCKED 0x04 135 #define RX_IBUF_OVERFLOWED 0x08 136 #define RX_ANY_BLOCK 0x0f 137 sc_tx_busy, 138 sc_tx_done, 139 sc_tx_stopped, 140 sc_st_check, 141 sc_rx_ready; 142 143 /* data to stored in UART registers. 144 actual write to UART register is pended while sc_tx_busy */ 145 uint16_t sc_ucon; /* control register */ 146 uint16_t sc_ubrdiv; /* baudrate register */ 147 uint8_t sc_heldchange; /* register changes are pended */ 148 uint8_t sc_ulcon; /* line control */ 149 uint8_t sc_umcon; /* modem control */ 150 #define UMCON_HW_MASK (UMCON_RTS) 151 #define UMCON_DTR (1<<4) /* provided by other means such as GPIO */ 152 uint8_t sc_msts; /* modem status */ 153 #define MSTS_CTS UMSTAT_CTS /* bit0 */ 154 #define MSTS_DCD (1<<1) 155 #define MSTS_DSR (1<<2) 156 157 uint8_t sc_msr_dcd; /* DCD or 0 */ 158 uint8_t sc_mcr_dtr; /* DTR or 0 or DTR|RTS*/ 159 uint8_t sc_mcr_rts; /* RTS or DTR in sc_umcon */ 160 uint8_t sc_msr_cts; /* CTS or DCD in sc_msts */ 161 162 uint8_t sc_msr_mask; /* sc_msr_cts|sc_msr_dcd */ 163 uint8_t sc_mcr_active; 164 uint8_t sc_msr_delta; 165 166 uint8_t sc_rx_irqno, sc_tx_irqno; 167 168 #if 0 169 /* PPS signal on DCD, with or without inkernel clock disciplining */ 170 u_char sc_ppsmask; /* pps signal mask */ 171 u_char sc_ppsassert; /* pps leading edge */ 172 u_char sc_ppsclear; /* pps trailing edge */ 173 pps_info_t ppsinfo; 174 pps_params_t ppsparam; 175 #endif 176 177 #if NRND > 0 && defined(RND_COM) 178 krndsource_t rnd_source; 179 #endif 180 #if (defined(MULTIPROCESSOR) || defined(LOCKDEBUG)) && defined(SSCOM_MPLOCK) 181 struct simplelock sc_lock; 182 #endif 183 184 /* 185 * S3C2XX0's UART doesn't have modem control/status pins. 186 * On platforms with S3C2XX0, those pins are simply unavailable 187 * or provided by other means such as GPIO. Platform specific attach routine 188 * have to provide functions to read/write modem control/status pins. 189 */ 190 int (* read_modem_status)( struct sscom_softc * ); 191 void (* set_modem_control)( struct sscom_softc * ); 192 }; 193 194 /* UART register address, etc. */ 195 struct sscom_uart_info { 196 int unit; 197 char tx_int, rx_int, err_int; 198 bus_addr_t iobase; 199 }; 200 201 #define sscom_rxrdy(iot,ioh) \ 202 (bus_space_read_1((iot), (ioh), SSCOM_UTRSTAT) & UTRSTAT_RXREADY) 203 #define sscom_getc(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_URXH) 204 #define sscom_geterr(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_UERSTAT) 205 206 /* 207 * we need to tweak interrupt controller to mask/unmask rxint and/or txint. 208 */ 209 #ifdef SSCOM_S3C2410 210 /* RXINTn, TXINTn and ERRn interrupts are cascaded to UARTn irq. */ 211 212 #define _sscom_intbit(irqno) (1<<((irqno)-S3C2410_SUBIRQ_MIN)) 213 214 #define sscom_unmask_rxint(sc) \ 215 s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno)) 216 #define sscom_mask_rxint(sc) \ 217 s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno)) 218 #define sscom_unmask_txint(sc) \ 219 s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno)) 220 #define sscom_mask_txint(sc) \ 221 s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno)) 222 #define sscom_unmask_txrxint(sc) \ 223 s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \ 224 _sscom_intbit((sc)->sc_rx_irqno)) 225 #define sscom_mask_txrxint(sc) \ 226 s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \ 227 _sscom_intbit((sc)->sc_rx_irqno)) 228 229 #elif defined(SSCOM_S3C2440) 230 /* RXINTn, TXINTn and ERRn interrupts are cascaded to UARTn irq. */ 231 232 #define _sscom_intbit(irqno) (1<<((irqno)-S3C2440_SUBIRQ_MIN)) 233 234 #define sscom_unmask_rxint(sc) \ 235 s3c2440_unmask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno)) 236 #define sscom_mask_rxint(sc) \ 237 s3c2440_mask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno)) 238 #define sscom_unmask_txint(sc) \ 239 s3c2440_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno)) 240 #define sscom_mask_txint(sc) \ 241 s3c2440_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno)) 242 #define sscom_unmask_txrxint(sc) \ 243 s3c2440_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \ 244 _sscom_intbit((sc)->sc_rx_irqno)) 245 #define sscom_mask_txrxint(sc) \ 246 s3c2440_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \ 247 _sscom_intbit((sc)->sc_rx_irqno)) 248 #else 249 250 /* for S3C2800 and S3C2400 */ 251 #define sscom_unmask_rxint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_rx_irqno) 252 #define sscom_mask_rxint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_rx_irqno) 253 #define sscom_unmask_txint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_tx_irqno) 254 #define sscom_mask_txint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_tx_irqno) 255 #define sscom_unmask_txrxint(sc) \ 256 s3c2xx0_unmask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno)) 257 #define sscom_mask_txrxint(sc) \ 258 s3c2xx0_mask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno)) 259 260 #endif /* SSCOM_S3C2410 */ 261 262 #define sscom_enable_rxint(sc) \ 263 (sscom_unmask_rxint(sc), ((sc)->sc_hwflags |= SSCOM_HW_RXINT)) 264 #define sscom_disable_rxint(sc) \ 265 (sscom_mask_rxint(sc), ((sc)->sc_hwflags &= ~SSCOM_HW_RXINT)) 266 #define sscom_enable_txint(sc) \ 267 (sscom_unmask_txint(sc), ((sc)->sc_hwflags |= SSCOM_HW_TXINT)) 268 #define sscom_disable_txint(sc) \ 269 (sscom_mask_txint(sc),((sc)->sc_hwflags &= ~SSCOM_HW_TXINT)) 270 #define sscom_enable_txrxint(sc) \ 271 (sscom_unmask_txrxint(sc),((sc)->sc_hwflags |= (SSCOM_HW_TXINT|SSCOM_HW_RXINT))) 272 #define sscom_disable_txrxint(sc) \ 273 (sscom_mask_txrxint(sc),((sc)->sc_hwflags &= ~(SSCOM_HW_TXINT|SSCOM_HW_RXINT))) 274 275 276 int sscomspeed(long, long); 277 void sscom_attach_subr(struct sscom_softc *); 278 279 int sscom_detach(struct device *, int); 280 int sscom_activate(struct device *, enum devact); 281 void sscom_shutdown(struct sscom_softc *); 282 void sscomdiag (void *); 283 void sscomstart(struct tty *); 284 int sscomparam(struct tty *, struct termios *); 285 int sscomread(dev_t, struct uio *, int); 286 void sscom_config(struct sscom_softc *); 287 288 int sscomtxintr(void *); 289 int sscomrxintr(void *); 290 291 int sscom_cnattach(bus_space_tag_t, const struct sscom_uart_info *, 292 int, int, tcflag_t); 293 void sscom_cndetach(void); 294 int sscom_is_console(bus_space_tag_t, int, bus_space_handle_t *); 295 296 #ifdef KGDB 297 int sscom_kgdb_attach(bus_space_tag_t, const struct sscom_uart_info *, 298 int, int, tcflag_t); 299 #endif 300 301 #endif /* _ARM_S3C2XX0_SSCOM_VAR_H */ 302
Indexes created Tue Sep 30 17:09:57 GMT 2025