sscom_var.h revision 1.11.6.3
1 /* $NetBSD: sscom_var.h,v 1.11.6.3 2017/12/03 11:35:55 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* derived from sys/dev/ic/comvar.h */ 35 36 /* 37 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #ifndef _ARM_S3C2XX0_SSCOM_VAR_H 67 #define _ARM_S3C2XX0_SSCOM_VAR_H 68 69 #include "opt_multiprocessor.h" 70 #include "opt_lockdebug.h" 71 #include "opt_sscom.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/device.h> 76 #include <sys/termios.h> 77 #include <sys/callout.h> 78 #include <sys/bus.h> 79 #ifdef RND_COM 80 #include <sys/rndsource.h> 81 #endif 82 83 #ifdef SSCOM_S3C2410 84 #include <arm/s3c2xx0/s3c2410reg.h> 85 #include <arm/s3c2xx0/s3c2410var.h> 86 #elif defined(SSCOM_S3C2440) 87 #include <arm/s3c2xx0/s3c2440reg.h> 88 #include <arm/s3c2xx0/s3c2440var.h> 89 #endif 90 91 /* Hardware flag masks */ 92 #define SSCOM_HW_FLOW 0x02 93 #define SSCOM_HW_DEV_OK 0x04 94 #define SSCOM_HW_CONSOLE 0x08 95 #define SSCOM_HW_KGDB 0x10 96 #define SSCOM_HW_TXINT 0x20 97 #define SSCOM_HW_RXINT 0x40 98 99 /* Buffer size for character buffer */ 100 #define SSCOM_RING_SIZE 2048 101 102 struct sscom_softc { 103 device_t sc_dev; 104 void *sc_si; 105 struct tty *sc_tty; 106 107 struct callout sc_diag_callout; 108 109 int sc_unit; /* UART0/UART1 */ 110 int sc_frequency; 111 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_ioh; 114 115 u_int sc_overflows, 116 sc_floods, 117 sc_errors; 118 119 int sc_hwflags, 120 sc_swflags; 121 122 u_int sc_r_hiwat, 123 sc_r_lowat; 124 u_char *volatile sc_rbget, 125 *volatile sc_rbput; 126 volatile u_int sc_rbavail; 127 u_char *sc_rbuf, 128 *sc_ebuf; 129 130 u_char *sc_tba; 131 u_int sc_tbc, 132 sc_heldtbc; 133 134 volatile u_char sc_rx_flags, 135 #define RX_TTY_BLOCKED 0x01 136 #define RX_TTY_OVERFLOWED 0x02 137 #define RX_IBUF_BLOCKED 0x04 138 #define RX_IBUF_OVERFLOWED 0x08 139 #define RX_ANY_BLOCK 0x0f 140 sc_tx_busy, 141 sc_tx_done, 142 sc_tx_stopped, 143 sc_st_check, 144 sc_rx_ready; 145 146 /* data to stored in UART registers. 147 actual write to UART register is pended while sc_tx_busy */ 148 uint16_t sc_ucon; /* control register */ 149 uint16_t sc_ubrdiv; /* baudrate register */ 150 uint8_t sc_heldchange; /* register changes are pended */ 151 uint8_t sc_ulcon; /* line control */ 152 uint8_t sc_umcon; /* modem control */ 153 #define UMCON_HW_MASK (UMCON_RTS) 154 #define UMCON_DTR (1<<4) /* provided by other means such as GPIO */ 155 uint8_t sc_msts; /* modem status */ 156 #define MSTS_CTS UMSTAT_CTS /* bit0 */ 157 #define MSTS_DCD (1<<1) 158 #define MSTS_DSR (1<<2) 159 160 uint8_t sc_msr_dcd; /* DCD or 0 */ 161 uint8_t sc_mcr_dtr; /* DTR or 0 or DTR|RTS*/ 162 uint8_t sc_mcr_rts; /* RTS or DTR in sc_umcon */ 163 uint8_t sc_msr_cts; /* CTS or DCD in sc_msts */ 164 165 uint8_t sc_msr_mask; /* sc_msr_cts|sc_msr_dcd */ 166 uint8_t sc_mcr_active; 167 uint8_t sc_msr_delta; 168 169 uint8_t sc_rx_irqno, sc_tx_irqno; 170 171 #if 0 172 /* PPS signal on DCD, with or without inkernel clock disciplining */ 173 u_char sc_ppsmask; /* pps signal mask */ 174 u_char sc_ppsassert; /* pps leading edge */ 175 u_char sc_ppsclear; /* pps trailing edge */ 176 pps_info_t ppsinfo; 177 pps_params_t ppsparam; 178 #endif 179 180 #ifdef RND_COM 181 krndsource_t sc_rnd_source; 182 #endif 183 #if (defined(MULTIPROCESSOR) || defined(LOCKDEBUG)) && defined(SSCOM_MPLOCK) 184 kmutex_t sc_lock; 185 #endif 186 187 /* 188 * S3C2XX0's UART doesn't have modem control/status pins. 189 * On platforms with S3C2XX0, those pins are simply unavailable 190 * or provided by other means such as GPIO. Platform specific attach routine 191 * have to provide functions to read/write modem control/status pins. 192 */ 193 int (*sc_read_modem_status)( struct sscom_softc * ); 194 void (*sc_set_modem_control)( struct sscom_softc * ); 195 void (*sc_change_txrx_interrupts)(struct sscom_softc *, bool, u_int); 196 }; 197 198 /* UART register address, etc. */ 199 struct sscom_uart_info { 200 int unit; 201 char tx_int, rx_int, err_int; 202 bus_addr_t iobase; 203 }; 204 205 #define sscom_rxrdy(iot,ioh) \ 206 (bus_space_read_1((iot), (ioh), SSCOM_UTRSTAT) & UTRSTAT_RXREADY) 207 #define sscom_getc(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_URXH) 208 #define sscom_geterr(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_UERSTAT) 209 210 #define sscom_mask_rxint(sc) \ 211 (*(sc)->sc_change_txrx_interrupts)((sc), false, SSCOM_HW_RXINT) 212 #define sscom_unmask_rxint(sc) \ 213 (*(sc)->sc_change_txrx_interrupts)((sc), true, SSCOM_HW_RXINT) 214 #define sscom_mask_txint(sc) \ 215 (*(sc)->sc_change_txrx_interrupts)((sc), false, SSCOM_HW_TXINT) 216 #define sscom_unmask_txint(sc) \ 217 (*(sc)->sc_change_txrx_interrupts)((sc), true, SSCOM_HW_TXINT) 218 #define sscom_mask_txrxint(sc) \ 219 (*(sc)->sc_change_txrx_interrupts)((sc), false, \ 220 SSCOM_HW_RXINT | SSCOM_HW_TXINT) 221 #define sscom_unmask_txrxint(sc) \ 222 (*(sc)->sc_change_txrx_interrupts)((sc), true, \ 223 SSCOM_HW_RXINT | SSCOM_HW_TXINT) 224 225 #define sscom_enable_rxint(sc) \ 226 (sscom_unmask_rxint(sc), ((sc)->sc_hwflags |= SSCOM_HW_RXINT)) 227 #define sscom_disable_rxint(sc) \ 228 (sscom_mask_rxint(sc), ((sc)->sc_hwflags &= ~SSCOM_HW_RXINT)) 229 #define sscom_enable_txint(sc) \ 230 (sscom_unmask_txint(sc), ((sc)->sc_hwflags |= SSCOM_HW_TXINT)) 231 #define sscom_disable_txint(sc) \ 232 (sscom_mask_txint(sc),((sc)->sc_hwflags &= ~SSCOM_HW_TXINT)) 233 #define sscom_enable_txrxint(sc) \ 234 (sscom_unmask_txrxint(sc),((sc)->sc_hwflags |= (SSCOM_HW_TXINT|SSCOM_HW_RXINT))) 235 #define sscom_disable_txrxint(sc) \ 236 (sscom_mask_txrxint(sc),((sc)->sc_hwflags &= ~(SSCOM_HW_TXINT|SSCOM_HW_RXINT))) 237 238 239 int sscomspeed(long, long); 240 void sscom_attach_subr(struct sscom_softc *); 241 242 int sscom_detach(device_t, int); 243 int sscom_activate(device_t, enum devact); 244 void sscom_shutdown(struct sscom_softc *); 245 void sscomdiag(void *); 246 void sscomstart(struct tty *); 247 int sscomparam(struct tty *, struct termios *); 248 int sscomread(dev_t, struct uio *, int); 249 void sscom_config(struct sscom_softc *); 250 251 int sscomtxintr(void *); 252 int sscomrxintr(void *); 253 254 int sscom_cnattach(bus_space_tag_t, const struct sscom_uart_info *, 255 int, int, tcflag_t); 256 void sscom_cndetach(void); 257 int sscom_is_console(bus_space_tag_t, int, bus_space_handle_t *); 258 259 #ifdef KGDB 260 int sscom_kgdb_attach(bus_space_tag_t, const struct sscom_uart_info *, 261 int, int, tcflag_t); 262 #endif 263 264 #endif /* _ARM_S3C2XX0_SSCOM_VAR_H */ 265
Indexes created Wed Oct 22 00:09:40 GMT 2025