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      1  1.4  martin /*	$NetBSD: sa1111_reg.h,v 1.4 2008/04/28 20:23:14 martin Exp $	*/
      2  1.1     rjs 
      3  1.1     rjs /*-
      4  1.1     rjs  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5  1.1     rjs  * All rights reserved.
      6  1.1     rjs  *
      7  1.1     rjs  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1     rjs  * by IWAMOTO Toshihiro.
      9  1.1     rjs  *
     10  1.1     rjs  * Redistribution and use in source and binary forms, with or without
     11  1.1     rjs  * modification, are permitted provided that the following conditions
     12  1.1     rjs  * are met:
     13  1.1     rjs  * 1. Redistributions of source code must retain the above copyright
     14  1.1     rjs  *    notice, this list of conditions and the following disclaimer.
     15  1.1     rjs  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1     rjs  *    notice, this list of conditions and the following disclaimer in the
     17  1.1     rjs  *    documentation and/or other materials provided with the distribution.
     18  1.1     rjs  *
     19  1.1     rjs  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  1.1     rjs  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  1.1     rjs  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  1.1     rjs  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  1.1     rjs  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  1.1     rjs  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  1.1     rjs  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  1.1     rjs  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  1.1     rjs  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  1.1     rjs  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  1.1     rjs  * POSSIBILITY OF SUCH DAMAGE.
     30  1.1     rjs  */
     31  1.1     rjs 
     32  1.3     bsh #ifndef _ARM_SA11X0_SA1111_REG_H
     33  1.3     bsh #define _ARM_SA11X0_SA1111_REG_H
     34  1.3     bsh 
     35  1.3     bsh 
     36  1.1     rjs /* Interrupt Controller */
     37  1.1     rjs 
     38  1.1     rjs /* number of interrupt bits */
     39  1.1     rjs #define SACCIC_LEN	55
     40  1.1     rjs 
     41  1.1     rjs /* System Bus Interface */
     42  1.2     rjs #define SACCSBI_SKCR		0x0000
     43  1.3     bsh #define  SKCR_PLLBYPASS  	(1<<0)
     44  1.3     bsh #define  SKCR_RCLKEN    	(1<<1)
     45  1.3     bsh #define  SKCR_SLEEP     	(1<<2)
     46  1.3     bsh #define  SKCR_DOZE		(1<<3)
     47  1.3     bsh #define  SKCR_VCOOFF		(1<<4)
     48  1.3     bsh #define  SKCR_RDYEN		(1<<7)
     49  1.3     bsh #define  SKCR_SELAC		(1<<8)	/* AC Link or I2S */
     50  1.3     bsh #define  SKCR_NOEEN		(1<<12)	/* Enable nOE */
     51  1.2     rjs #define SACCSBI_SMCR		0x0004
     52  1.1     rjs #define SACCSBI_SKID		0x0008
     53  1.1     rjs 
     54  1.2     rjs /* System Controller */
     55  1.2     rjs #define SACCSC_SKPCR		0x0200
     56  1.2     rjs 
     57  1.2     rjs /* USB Host Controller */
     58  1.2     rjs #define SACCUSB_REVISION	0x0400
     59  1.2     rjs #define SACCUSB_CONTROL		0x0404
     60  1.2     rjs #define SACCUSB_STATUS		0x0408
     61  1.2     rjs #define SACCUSB_RESET		0x051C
     62  1.2     rjs 
     63  1.1     rjs /* Interrupt Controller */
     64  1.1     rjs #define SACCIC_INTTEST0		0x1600
     65  1.1     rjs #define SACCIC_INTTEST1		0x1604
     66  1.1     rjs #define SACCIC_INTEN0		0x1608
     67  1.1     rjs #define SACCIC_INTEN1		0x160C
     68  1.1     rjs #define SACCIC_INTPOL0		0x1610
     69  1.1     rjs #define SACCIC_INTPOL1		0x1614
     70  1.1     rjs #define SACCIC_INTTSTSEL	0x1618
     71  1.1     rjs #define SACCIC_INTSTATCLR0	0x161C
     72  1.1     rjs #define SACCIC_INTSTATCLR1	0x1620
     73  1.1     rjs #define SACCIC_INTSET0		0x1624
     74  1.1     rjs #define SACCIC_INTSET1		0x1628
     75  1.1     rjs #define SACCIC_WAKE_EN0		0x162C
     76  1.1     rjs #define SACCIC_WAKE_EN1		0x1630
     77  1.1     rjs #define SACCIC_WAKE_POL0	0x1634
     78  1.1     rjs #define SACCIC_WAKE_POL1	0x1638
     79  1.1     rjs 
     80  1.1     rjs /* GPIO registers */
     81  1.1     rjs #define SACCGPIOA_DDR		0x1000		/* data direction */
     82  1.1     rjs #define SACCGPIOA_DVR		0x1004		/* data value */
     83  1.1     rjs #define SACCGPIOA_SDR		0x1008		/* sleep direction */
     84  1.1     rjs #define SACCGPIOA_SSR		0x100C		/* sleep state */
     85  1.1     rjs #define SACCGPIOB_DDR		0x1010
     86  1.1     rjs #define SACCGPIOB_DVR		0x1014
     87  1.1     rjs #define SACCGPIOB_SDR		0x1018
     88  1.1     rjs #define SACCGPIOB_SSR		0x101C
     89  1.1     rjs #define SACCGPIOC_DDR		0x1020
     90  1.1     rjs #define SACCGPIOC_DVR		0x1024
     91  1.1     rjs #define SACCGPIOC_SDR		0x1028
     92  1.1     rjs #define SACCGPIOC_SSR		0x102C
     93  1.2     rjs 
     94  1.3     bsh #define SACC_KBD0		0x0a00
     95  1.3     bsh #define SACC_KBD1		0x0c00
     96  1.3     bsh 
     97  1.3     bsh #define SACCKBD_CR		0x00
     98  1.3     bsh #define  KBDCR_FKC		(1<<0) /* Force MSCLK/TPCLK low */
     99  1.3     bsh #define  KBDCR_FKD		(1<<1) /* Force MSDATA/TPDATA low */
    100  1.3     bsh #define  KBDCR_ENA		(1<<3) /* Enable */
    101  1.3     bsh #define SACCKBD_STAT		0x04
    102  1.3     bsh #define  KBDSTAT_KBC		(1<<0) /* KBCLK pin value */
    103  1.3     bsh #define  KBDSTAT_KBD		(1<<1) /* KBDATA pin value */
    104  1.3     bsh #define  KBDSTAT_RXP		(1<<2) /* Parity */
    105  1.3     bsh #define  KBDSTAT_ENA		(1<<3) /* Enable */
    106  1.3     bsh #define  KBDSTAT_RXB		(1<<4) /* Rx busy */
    107  1.3     bsh #define  KBDSTAT_RXF		(1<<5) /* Rx full */
    108  1.3     bsh #define  KBDSTAT_TXB		(1<<6) /* Tx busy */
    109  1.3     bsh #define  KBDSTAT_TXE		(1<<7) /* Tx empty */
    110  1.3     bsh #define  KBDSTAT_STP		(1<<8) /* Stop bit error */
    111  1.3     bsh #define SACCKBD_DATA		0x08
    112  1.3     bsh #define SACCKBD_CLKDIV		0x0c
    113  1.3     bsh #define  KBDCLKDIV_DIV8		0
    114  1.3     bsh #define  KBDCLKDIV_DIV4		1
    115  1.3     bsh #define  KBDCLKDIV_DIV2		2
    116  1.3     bsh #define SACCKBD_CLKPRECNT	0x10
    117  1.3     bsh #define SACCKBD_KBDITR		0x14 /* Interrupt test */
    118  1.3     bsh 
    119  1.3     bsh #define SACCKBD_SIZE  		0x18
    120  1.3     bsh 
    121  1.3     bsh #endif /* _ARM_SA11X0_SA1111_REG_H */
    122