sa1111_reg.h revision 1.3 1 /* $NetBSD: sa1111_reg.h,v 1.3 2002/12/18 04:09:31 bsh Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by IWAMOTO Toshihiro.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef _ARM_SA11X0_SA1111_REG_H
40 #define _ARM_SA11X0_SA1111_REG_H
41
42
43 /* Interrupt Controller */
44
45 /* number of interrupt bits */
46 #define SACCIC_LEN 55
47
48 /* System Bus Interface */
49 #define SACCSBI_SKCR 0x0000
50 #define SKCR_PLLBYPASS (1<<0)
51 #define SKCR_RCLKEN (1<<1)
52 #define SKCR_SLEEP (1<<2)
53 #define SKCR_DOZE (1<<3)
54 #define SKCR_VCOOFF (1<<4)
55 #define SKCR_RDYEN (1<<7)
56 #define SKCR_SELAC (1<<8) /* AC Link or I2S */
57 #define SKCR_NOEEN (1<<12) /* Enable nOE */
58 #define SACCSBI_SMCR 0x0004
59 #define SACCSBI_SKID 0x0008
60
61 /* System Controller */
62 #define SACCSC_SKPCR 0x0200
63
64 /* USB Host Controller */
65 #define SACCUSB_REVISION 0x0400
66 #define SACCUSB_CONTROL 0x0404
67 #define SACCUSB_STATUS 0x0408
68 #define SACCUSB_RESET 0x051C
69
70 /* Interrupt Controller */
71 #define SACCIC_INTTEST0 0x1600
72 #define SACCIC_INTTEST1 0x1604
73 #define SACCIC_INTEN0 0x1608
74 #define SACCIC_INTEN1 0x160C
75 #define SACCIC_INTPOL0 0x1610
76 #define SACCIC_INTPOL1 0x1614
77 #define SACCIC_INTTSTSEL 0x1618
78 #define SACCIC_INTSTATCLR0 0x161C
79 #define SACCIC_INTSTATCLR1 0x1620
80 #define SACCIC_INTSET0 0x1624
81 #define SACCIC_INTSET1 0x1628
82 #define SACCIC_WAKE_EN0 0x162C
83 #define SACCIC_WAKE_EN1 0x1630
84 #define SACCIC_WAKE_POL0 0x1634
85 #define SACCIC_WAKE_POL1 0x1638
86
87 /* GPIO registers */
88 #define SACCGPIOA_DDR 0x1000 /* data direction */
89 #define SACCGPIOA_DVR 0x1004 /* data value */
90 #define SACCGPIOA_SDR 0x1008 /* sleep direction */
91 #define SACCGPIOA_SSR 0x100C /* sleep state */
92 #define SACCGPIOB_DDR 0x1010
93 #define SACCGPIOB_DVR 0x1014
94 #define SACCGPIOB_SDR 0x1018
95 #define SACCGPIOB_SSR 0x101C
96 #define SACCGPIOC_DDR 0x1020
97 #define SACCGPIOC_DVR 0x1024
98 #define SACCGPIOC_SDR 0x1028
99 #define SACCGPIOC_SSR 0x102C
100
101 #define SACC_KBD0 0x0a00
102 #define SACC_KBD1 0x0c00
103
104 #define SACCKBD_CR 0x00
105 #define KBDCR_FKC (1<<0) /* Force MSCLK/TPCLK low */
106 #define KBDCR_FKD (1<<1) /* Force MSDATA/TPDATA low */
107 #define KBDCR_ENA (1<<3) /* Enable */
108 #define SACCKBD_STAT 0x04
109 #define KBDSTAT_KBC (1<<0) /* KBCLK pin value */
110 #define KBDSTAT_KBD (1<<1) /* KBDATA pin value */
111 #define KBDSTAT_RXP (1<<2) /* Parity */
112 #define KBDSTAT_ENA (1<<3) /* Enable */
113 #define KBDSTAT_RXB (1<<4) /* Rx busy */
114 #define KBDSTAT_RXF (1<<5) /* Rx full */
115 #define KBDSTAT_TXB (1<<6) /* Tx busy */
116 #define KBDSTAT_TXE (1<<7) /* Tx empty */
117 #define KBDSTAT_STP (1<<8) /* Stop bit error */
118 #define SACCKBD_DATA 0x08
119 #define SACCKBD_CLKDIV 0x0c
120 #define KBDCLKDIV_DIV8 0
121 #define KBDCLKDIV_DIV4 1
122 #define KBDCLKDIV_DIV2 2
123 #define SACCKBD_CLKPRECNT 0x10
124 #define SACCKBD_KBDITR 0x14 /* Interrupt test */
125
126 #define SACCKBD_SIZE 0x18
127
128 #endif /* _ARM_SA11X0_SA1111_REG_H */
129