sa11x0_dmacreg.h revision 1.1.64.1
1 /* $NetBSD: sa11x0_dmacreg.h,v 1.1.64.1 2006/05/24 15:47:52 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by IWAMOTO Toshihiro. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* SA11[01]0 integrated DMA controller */ 39 40 #define SADMAC_NPORTS 40 41 42 #define SADMAC_DAR0 0x00 /* DMA device address register */ 43 #define SADMAC_DCR0_SET 0x04 /* DMA control/status (set) */ 44 #define SADMAC_DCR0_CLR 0x08 /* DMA control/status (clear) */ 45 #define SADMAC_DCR0 0x0C /* DMA control/status (read only) */ 46 #define SADMAC_DBSA0 0x10 /* DMA Buffer A start address */ 47 #define SADMAC_DBTA0 0x14 /* DMA Buffer A transfer count */ 48 #define SADMAC_DBSB0 0x18 /* DMA Buffer B start address */ 49 #define SADMAC_DBTB0 0x1C /* DMA Buffer B transfer count */ 50 51 #define SADMAC_DAR1 0x20 52 #define SADMAC_DCR1_SET 0x24 53 #define SADMAC_DCR1_CLR 0x28 54 #define SADMAC_DCR1 0x2C 55 #define SADMAC_DBSA1 0x30 56 #define SADMAC_DBTA1 0x34 57 #define SADMAC_DBSB1 0x38 58 #define SADMAC_DBTB1 0x3C 59 60 #define SADMAC_DAR2 0x40 61 #define SADMAC_DCR2_SET 0x44 62 #define SADMAC_DCR2_CLR 0x48 63 #define SADMAC_DCR2 0x4C 64 #define SADMAC_DBSA2 0x50 65 #define SADMAC_DBTA2 0x54 66 #define SADMAC_DBSB2 0x58 67 #define SADMAC_DBTB2 0x5C 68 69 #define SADMAC_DAR3 0x60 70 #define SADMAC_DCR3_SET 0x64 71 #define SADMAC_DCR3_CLR 0x68 72 #define SADMAC_DCR3 0x6C 73 #define SADMAC_DBSA3 0x70 74 #define SADMAC_DBTA3 0x74 75 #define SADMAC_DBSB3 0x78 76 #define SADMAC_DBTB3 0x7C 77 78 #define SADMAC_DAR4 0x80 79 #define SADMAC_DCR4_SET 0x84 80 #define SADMAC_DCR4_CLR 0x88 81 #define SADMAC_DCR4 0x8C 82 #define SADMAC_DBSA4 0x90 83 #define SADMAC_DBTA4 0x94 84 #define SADMAC_DBSB4 0x98 85 #define SADMAC_DBTB4 0x9C 86 87 #define SADMAC_DAR5 0xA0 88 #define SADMAC_DCR5_SET 0xA4 89 #define SADMAC_DCR5_CLR 0xA8 90 #define SADMAC_DCR5 0xAC 91 #define SADMAC_DBSA5 0xB0 92 #define SADMAC_DBTA5 0xB4 93 #define SADMAC_DBSB5 0xB8 94 #define SADMAC_DBTB5 0xBC 95
Indexes created Sat Oct 25 01:09:55 GMT 2025