1 1.4 rjs /* $NetBSD: sa11x0_gpioreg.h,v 1.4 2009/05/29 14:06:53 rjs Exp $ */ 2 1.1 rjs 3 1.1 rjs /*- 4 1.1 rjs * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. 5 1.1 rjs * 6 1.1 rjs * This code is derived from software contributed to The NetBSD Foundation 7 1.1 rjs * by Ichiro FUKUHARA (ichiro (at) ichiro.org). 8 1.1 rjs * 9 1.1 rjs * Redistribution and use in source and binary forms, with or without 10 1.1 rjs * modification, are permitted provided that the following conditions 11 1.1 rjs * are met: 12 1.1 rjs * 1. Redistributions of source code must retain the above copyright 13 1.1 rjs * notice, this list of conditions and the following disclaimer. 14 1.1 rjs * 2. Redistributions in binary form must reproduce the above copyright 15 1.1 rjs * notice, this list of conditions and the following disclaimer in the 16 1.1 rjs * documentation and/or other materials provided with the distribution. 17 1.1 rjs * 18 1.1 rjs * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.1 rjs * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.1 rjs * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.1 rjs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.1 rjs * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.1 rjs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.1 rjs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.1 rjs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.1 rjs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.1 rjs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.1 rjs * POSSIBILITY OF SUCH DAMAGE. 29 1.1 rjs */ 30 1.1 rjs 31 1.1 rjs /* 32 1.1 rjs * SA-11x0 GPIO Register 33 1.1 rjs */ 34 1.1 rjs 35 1.1 rjs #define SAGPIO_NPORTS 8 36 1.1 rjs 37 1.1 rjs /* GPIO pin-level register */ 38 1.1 rjs #define SAGPIO_PLR 0x00 39 1.1 rjs 40 1.1 rjs /* GPIO pin direction register */ 41 1.1 rjs #define SAGPIO_PDR 0x04 42 1.1 rjs 43 1.1 rjs /* GPIO pin output set register */ 44 1.1 rjs #define SAGPIO_PSR 0x08 45 1.1 rjs 46 1.1 rjs /* GPIO pin output clear register */ 47 1.1 rjs #define SAGPIO_PCR 0x0C 48 1.1 rjs 49 1.1 rjs /* GPIO rising-edge detect register */ 50 1.1 rjs #define SAGPIO_RER 0x10 51 1.1 rjs 52 1.1 rjs /* GPIO falling-edge detect register */ 53 1.1 rjs #define SAGPIO_FER 0x14 54 1.1 rjs 55 1.1 rjs /* GPIO edge-detect status register */ 56 1.1 rjs #define SAGPIO_EDR 0x18 57 1.1 rjs 58 1.1 rjs /* GPIO alternate function register */ 59 1.1 rjs #define SAGPIO_AFR 0x1C 60 1.1 rjs 61 1.1 rjs /* XXX */ 62 1.1 rjs #define GPIO(x) (0x00000001 << (x)) 63 1.1 rjs 64 1.1 rjs /* 65 1.2 rjs * SA-11x0 GPIOs parameter 66 1.1 rjs */ 67 1.1 rjs /* 68 1.2 rjs port name desc 69 1.2 rjs 0 Reserved 70 1.2 rjs 1 Reserved 71 1.2 rjs 2...9 LDD{8..15} LCD DATA(8-15) 72 1.2 rjs 10 SSP_TXD SSP transmit 73 1.2 rjs 11 SSP_RXD SSP receive 74 1.2 rjs 12 SSP_SCLK SSP serial clock 75 1.2 rjs 13 SSP_SFRM SSP frameclock 76 1.2 rjs 14 UART_TXD UART transmit 77 1.2 rjs 15 UART_RXD UART receive 78 1.2 rjs 16 GPCLK_OUT General-purpose clock out 79 1.2 rjs 17 Reserved 80 1.2 rjs 18 UART_SCLK Sample clock input 81 1.2 rjs 19 SSP_CLK Sample clock input 82 1.2 rjs 20 UART_SCLK3 Sample clock input 83 1.2 rjs 21 MCP_CLK MCP dock in 84 1.2 rjs 22 TREQA Either TIC request A 85 1.2 rjs 23 TREQB Either TIC request B 86 1.2 rjs 24 Reserved 87 1.2 rjs 25 RTC Real Time Clock 88 1.2 rjs 26 RCLK_OUT internal clock /2 89 1.2 rjs 27 32KHZ_OUT Raw 32.768kHz osc output 90 1.1 rjs */ 91 1.4 rjs 92 1.4 rjs #define GPIO_ALT_SSP_TXD (1 << 10) 93 1.4 rjs #define GPIO_ALT_SSP_RXD (1 << 11) 94 1.4 rjs #define GPIO_ALT_SSP_SCLK (1 << 12) 95 1.4 rjs #define GPIO_ALT_SSP_SFRM (1 << 13) 96 1.4 rjs #define GPIO_ALT_SSP_CLK (1 << 19) 97 1.4 rjs 98
Indexes created Tue Oct 14 01:09:49 GMT 2025