sa11x0_irqhandler.c revision 1.14 1 1.14 matt /* $NetBSD: sa11x0_irqhandler.c,v 1.14 2008/04/27 18:58:45 matt Exp $ */
2 1.1 rjs
3 1.1 rjs /*-
4 1.1 rjs * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
5 1.1 rjs * All rights reserved.
6 1.1 rjs *
7 1.1 rjs * This code is derived from software contributed to the NetBSD Foundation
8 1.1 rjs * by IWAMOTO Toshihiro.
9 1.1 rjs *
10 1.1 rjs * This code is derived from software contributed to The NetBSD Foundation
11 1.1 rjs * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
12 1.1 rjs * Simulation Facility, NASA Ames Research Center.
13 1.1 rjs *
14 1.1 rjs * Redistribution and use in source and binary forms, with or without
15 1.1 rjs * modification, are permitted provided that the following conditions
16 1.1 rjs * are met:
17 1.1 rjs * 1. Redistributions of source code must retain the above copyright
18 1.1 rjs * notice, this list of conditions and the following disclaimer.
19 1.1 rjs * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 rjs * notice, this list of conditions and the following disclaimer in the
21 1.1 rjs * documentation and/or other materials provided with the distribution.
22 1.1 rjs * 3. All advertising materials mentioning features or use of this software
23 1.1 rjs * must display the following acknowledgement:
24 1.1 rjs * This product includes software developed by the NetBSD
25 1.1 rjs * Foundation, Inc. and its contributors.
26 1.1 rjs * 4. Neither the name of The NetBSD Foundation nor the names of its
27 1.1 rjs * contributors may be used to endorse or promote products derived
28 1.1 rjs * from this software without specific prior written permission.
29 1.1 rjs *
30 1.1 rjs * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
31 1.1 rjs * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 1.1 rjs * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 1.1 rjs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
34 1.1 rjs * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 1.1 rjs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 1.1 rjs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 1.1 rjs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 1.1 rjs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 1.1 rjs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 1.1 rjs * POSSIBILITY OF SUCH DAMAGE.
41 1.1 rjs */
42 1.1 rjs
43 1.1 rjs /*-
44 1.1 rjs * Copyright (c) 1991 The Regents of the University of California.
45 1.1 rjs * All rights reserved.
46 1.1 rjs *
47 1.1 rjs * This code is derived from software contributed to Berkeley by
48 1.1 rjs * William Jolitz.
49 1.1 rjs *
50 1.1 rjs * Redistribution and use in source and binary forms, with or without
51 1.1 rjs * modification, are permitted provided that the following conditions
52 1.1 rjs * are met:
53 1.1 rjs * 1. Redistributions of source code must retain the above copyright
54 1.1 rjs * notice, this list of conditions and the following disclaimer.
55 1.1 rjs * 2. Redistributions in binary form must reproduce the above copyright
56 1.1 rjs * notice, this list of conditions and the following disclaimer in the
57 1.1 rjs * documentation and/or other materials provided with the distribution.
58 1.5 agc * 3. Neither the name of the University nor the names of its contributors
59 1.1 rjs * may be used to endorse or promote products derived from this software
60 1.1 rjs * without specific prior written permission.
61 1.1 rjs *
62 1.1 rjs * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
63 1.1 rjs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64 1.1 rjs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
65 1.1 rjs * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
66 1.1 rjs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67 1.1 rjs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
68 1.1 rjs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
69 1.1 rjs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
70 1.1 rjs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
71 1.1 rjs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 1.1 rjs * SUCH DAMAGE.
73 1.1 rjs *
74 1.1 rjs * @(#)isa.c 7.2 (Berkeley) 5/13/91
75 1.1 rjs */
76 1.1 rjs
77 1.4 lukem
78 1.4 lukem #include <sys/cdefs.h>
79 1.14 matt __KERNEL_RCSID(0, "$NetBSD: sa11x0_irqhandler.c,v 1.14 2008/04/27 18:58:45 matt Exp $");
80 1.1 rjs
81 1.1 rjs #include "opt_irqstats.h"
82 1.1 rjs
83 1.1 rjs #include <sys/param.h>
84 1.1 rjs #include <sys/kernel.h>
85 1.1 rjs #include <sys/systm.h>
86 1.1 rjs #include <sys/syslog.h>
87 1.1 rjs #include <sys/malloc.h>
88 1.1 rjs #include <uvm/uvm_extern.h>
89 1.1 rjs
90 1.1 rjs #include <arm/sa11x0/sa11x0_reg.h>
91 1.1 rjs #include <arm/sa11x0/sa11x0_var.h>
92 1.1 rjs
93 1.1 rjs #include <machine/intr.h>
94 1.1 rjs #include <machine/cpu.h>
95 1.1 rjs
96 1.1 rjs irqhandler_t *irqhandlers[NIRQS];
97 1.1 rjs
98 1.1 rjs u_int actual_mask;
99 1.14 matt u_int irqmasks[NIPL];
100 1.1 rjs
101 1.3 chs extern void set_spl_masks(void);
102 1.1 rjs static int fakeintr(void *);
103 1.8 peter #ifdef INTR_DEBUG
104 1.3 chs static int dumpirqhandlers(void);
105 1.1 rjs #endif
106 1.3 chs void intr_calculatemasks(void);
107 1.3 chs
108 1.3 chs const struct evcnt *sa11x0_intr_evcnt(sa11x0_chipset_tag_t, int);
109 1.3 chs void stray_irqhandler(void *);
110 1.3 chs
111 1.14 matt #if IPL_NONE > IPL_HIGH
112 1.14 matt #error IPL_NONE must be less than IPL_HIGH
113 1.14 matt #endif
114 1.1 rjs /*
115 1.1 rjs * Recalculate the interrupt masks from scratch.
116 1.1 rjs * We could code special registry and deregistry versions of this function that
117 1.1 rjs * would be faster, but the code would be nastier, and we don't expect this to
118 1.1 rjs * happen very much anyway.
119 1.1 rjs */
120 1.1 rjs void
121 1.3 chs intr_calculatemasks(void)
122 1.1 rjs {
123 1.14 matt int irq, ipl;
124 1.1 rjs struct irqhandler *q;
125 1.1 rjs int intrlevel[ICU_LEN];
126 1.1 rjs
127 1.1 rjs /* First, figure out which levels each IRQ uses. */
128 1.1 rjs for (irq = 0; irq < ICU_LEN; irq++) {
129 1.14 matt int ipls = 0;
130 1.1 rjs for (q = irqhandlers[irq]; q; q = q->ih_next)
131 1.14 matt ipls |= 1 << q->ih_level;
132 1.14 matt intrlevel[irq] = ipls;
133 1.1 rjs }
134 1.1 rjs
135 1.1 rjs /* Then figure out which IRQs use each level. */
136 1.14 matt for (ipl = 0; ipl < NIPL; ipl++) {
137 1.1 rjs int irqs = 0;
138 1.1 rjs for (irq = 0; irq < ICU_LEN; irq++)
139 1.14 matt if (intrlevel[irq] & (1 << ipl))
140 1.1 rjs irqs |= 1 << irq;
141 1.14 matt irqmasks[ipl] = irqs;
142 1.1 rjs }
143 1.1 rjs
144 1.1 rjs /*
145 1.1 rjs * Enforce a hierarchy that gives slow devices a better chance at not
146 1.1 rjs * dropping data.
147 1.1 rjs */
148 1.14 matt for (ipl = IPL_NONE; ipl < NIPL - 1; ipl++)
149 1.14 matt irqmasks[ipl + 1] |= irqmasks[ipl];
150 1.1 rjs }
151 1.1 rjs
152 1.1 rjs
153 1.1 rjs const struct evcnt *
154 1.1 rjs sa11x0_intr_evcnt(sa11x0_chipset_tag_t ic, int irq)
155 1.1 rjs {
156 1.1 rjs
157 1.1 rjs /* XXX for now, no evcnt parent reported */
158 1.1 rjs return NULL;
159 1.1 rjs }
160 1.1 rjs
161 1.1 rjs void *
162 1.1 rjs sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
163 1.7 peter int (*ih_fun)(void *), void *ih_arg)
164 1.1 rjs {
165 1.1 rjs int saved_cpsr;
166 1.1 rjs struct irqhandler **p, *q, *ih;
167 1.1 rjs static struct irqhandler fakehand = {fakeintr};
168 1.1 rjs
169 1.1 rjs /* no point in sleeping unless someone can free memory. */
170 1.1 rjs ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
171 1.1 rjs if (ih == NULL)
172 1.1 rjs panic("sa11x0_intr_establish: can't malloc handler info");
173 1.1 rjs
174 1.1 rjs if (irq < 0 || irq >= ICU_LEN || type == IST_NONE)
175 1.1 rjs panic("intr_establish: bogus irq or type");
176 1.1 rjs
177 1.1 rjs /* All interrupts are level intrs. */
178 1.1 rjs
179 1.1 rjs /*
180 1.1 rjs * Figure out where to put the handler.
181 1.1 rjs * This is O(N^2), but we want to preserve the order, and N is
182 1.1 rjs * generally small.
183 1.1 rjs */
184 1.1 rjs for (p = &irqhandlers[irq]; (q = *p) != NULL; p = &q->ih_next)
185 1.10 peter continue;
186 1.1 rjs
187 1.1 rjs /*
188 1.1 rjs * Actually install a fake handler momentarily, since we might be doing
189 1.1 rjs * this with interrupts enabled and don't want the real routine called
190 1.1 rjs * until masking is set up.
191 1.1 rjs */
192 1.1 rjs fakehand.ih_level = level;
193 1.1 rjs *p = &fakehand;
194 1.1 rjs
195 1.1 rjs intr_calculatemasks();
196 1.1 rjs
197 1.1 rjs /*
198 1.1 rjs * Poke the real handler in now.
199 1.1 rjs */
200 1.1 rjs ih->ih_func = ih_fun;
201 1.1 rjs ih->ih_arg = ih_arg;
202 1.1 rjs #ifdef hpcarm
203 1.1 rjs ih->ih_count = 0;
204 1.1 rjs #else
205 1.1 rjs ih->ih_num = 0;
206 1.1 rjs #endif
207 1.1 rjs ih->ih_next = NULL;
208 1.1 rjs ih->ih_level = level;
209 1.1 rjs #ifdef hpcarm
210 1.1 rjs ih->ih_irq = irq;
211 1.1 rjs #endif
212 1.1 rjs ih->ih_name = NULL; /* XXX */
213 1.1 rjs *p = ih;
214 1.1 rjs
215 1.1 rjs saved_cpsr = SetCPSR(I32_bit, I32_bit);
216 1.1 rjs set_spl_masks();
217 1.1 rjs
218 1.1 rjs irq_setmasks();
219 1.1 rjs
220 1.1 rjs SetCPSR(I32_bit, saved_cpsr & I32_bit);
221 1.8 peter #ifdef INTR_DEBUG
222 1.1 rjs dumpirqhandlers();
223 1.1 rjs #endif
224 1.10 peter return ih;
225 1.1 rjs }
226 1.1 rjs
227 1.1 rjs #ifdef hpcarm
228 1.1 rjs /*
229 1.1 rjs * Deregister an interrupt handler.
230 1.1 rjs */
231 1.1 rjs void
232 1.1 rjs sa11x0_intr_disestablish(sa11x0_chipset_tag_t ic, void *arg)
233 1.1 rjs {
234 1.1 rjs struct irqhandler *ih = arg;
235 1.1 rjs int irq = ih->ih_irq;
236 1.1 rjs int saved_cpsr;
237 1.1 rjs struct irqhandler **p, *q;
238 1.1 rjs
239 1.1 rjs #if DIAGNOSTIC
240 1.1 rjs if (irq < 0 || irq >= ICU_LEN)
241 1.1 rjs panic("intr_disestablish: bogus irq");
242 1.1 rjs #endif
243 1.1 rjs
244 1.1 rjs /*
245 1.1 rjs * Remove the handler from the chain.
246 1.1 rjs * This is O(n^2), too.
247 1.1 rjs */
248 1.1 rjs for (p = &irqhandlers[irq]; (q = *p) != NULL && q != ih;
249 1.1 rjs p = &q->ih_next)
250 1.10 peter continue;
251 1.1 rjs if (q)
252 1.1 rjs *p = q->ih_next;
253 1.1 rjs else
254 1.1 rjs panic("intr_disestablish: handler not registered");
255 1.1 rjs free(ih, M_DEVBUF);
256 1.1 rjs
257 1.1 rjs intr_calculatemasks();
258 1.1 rjs saved_cpsr = SetCPSR(I32_bit, I32_bit);
259 1.1 rjs set_spl_masks();
260 1.1 rjs
261 1.1 rjs irq_setmasks();
262 1.1 rjs SetCPSR(I32_bit, saved_cpsr & I32_bit);
263 1.1 rjs
264 1.1 rjs }
265 1.1 rjs #endif
266 1.1 rjs
267 1.1 rjs void
268 1.1 rjs stray_irqhandler(void *p)
269 1.1 rjs {
270 1.1 rjs
271 1.1 rjs printf("stray interrupt\n");
272 1.1 rjs }
273 1.1 rjs
274 1.1 rjs int
275 1.1 rjs fakeintr(void *p)
276 1.1 rjs {
277 1.1 rjs
278 1.1 rjs return 0;
279 1.1 rjs }
280 1.1 rjs
281 1.8 peter #ifdef INTR_DEBUG
282 1.1 rjs int
283 1.7 peter dumpirqhandlers(void)
284 1.1 rjs {
285 1.1 rjs int irq;
286 1.1 rjs struct irqhandler *p;
287 1.1 rjs
288 1.1 rjs for (irq = 0; irq < ICU_LEN; irq++) {
289 1.1 rjs printf("irq %d:", irq);
290 1.1 rjs p = irqhandlers[irq];
291 1.1 rjs for (; p; p = p->ih_next)
292 1.1 rjs printf("ih_func: 0x%lx, ", (unsigned long)p->ih_func);
293 1.1 rjs printf("\n");
294 1.1 rjs }
295 1.1 rjs return 0;
296 1.1 rjs }
297 1.1 rjs #endif
298