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sa11x0_irqhandler.c revision 1.1
      1 /*	$NetBSD: sa11x0_irqhandler.c,v 1.1 2001/07/08 23:37:53 rjs Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to the NetBSD Foundation
      8  * by IWAMOTO Toshihiro.
      9  *
     10  * This code is derived from software contributed to The NetBSD Foundation
     11  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
     12  * Simulation Facility, NASA Ames Research Center.
     13  *
     14  * Redistribution and use in source and binary forms, with or without
     15  * modification, are permitted provided that the following conditions
     16  * are met:
     17  * 1. Redistributions of source code must retain the above copyright
     18  *    notice, this list of conditions and the following disclaimer.
     19  * 2. Redistributions in binary form must reproduce the above copyright
     20  *    notice, this list of conditions and the following disclaimer in the
     21  *    documentation and/or other materials provided with the distribution.
     22  * 3. All advertising materials mentioning features or use of this software
     23  *    must display the following acknowledgement:
     24  *	This product includes software developed by the NetBSD
     25  *	Foundation, Inc. and its contributors.
     26  * 4. Neither the name of The NetBSD Foundation nor the names of its
     27  *    contributors may be used to endorse or promote products derived
     28  *    from this software without specific prior written permission.
     29  *
     30  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     31  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     32  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     33  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     34  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     35  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     36  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     37  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     38  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     39  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     40  * POSSIBILITY OF SUCH DAMAGE.
     41  */
     42 
     43 /*-
     44  * Copyright (c) 1991 The Regents of the University of California.
     45  * All rights reserved.
     46  *
     47  * This code is derived from software contributed to Berkeley by
     48  * William Jolitz.
     49  *
     50  * Redistribution and use in source and binary forms, with or without
     51  * modification, are permitted provided that the following conditions
     52  * are met:
     53  * 1. Redistributions of source code must retain the above copyright
     54  *    notice, this list of conditions and the following disclaimer.
     55  * 2. Redistributions in binary form must reproduce the above copyright
     56  *    notice, this list of conditions and the following disclaimer in the
     57  *    documentation and/or other materials provided with the distribution.
     58  * 3. All advertising materials mentioning features or use of this software
     59  *    must display the following acknowledgement:
     60  *	This product includes software developed by the University of
     61  *	California, Berkeley and its contributors.
     62  * 4. Neither the name of the University nor the names of its contributors
     63  *    may be used to endorse or promote products derived from this software
     64  *    without specific prior written permission.
     65  *
     66  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     67  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     68  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     69  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     70  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     71  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     72  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     73  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     74  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     75  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     76  * SUCH DAMAGE.
     77  *
     78  *	@(#)isa.c	7.2 (Berkeley) 5/13/91
     79  */
     80 
     81 
     82 #include "opt_cputypes.h"
     83 #include "opt_irqstats.h"
     84 
     85 #include <sys/param.h>
     86 #include <sys/kernel.h>
     87 #include <sys/systm.h>
     88 #include <sys/syslog.h>
     89 #include <sys/malloc.h>
     90 #include <uvm/uvm_extern.h>
     91 
     92 #include <arm/sa11x0/sa11x0_reg.h>
     93 #include <arm/sa11x0/sa11x0_var.h>
     94 
     95 #include <machine/intr.h>
     96 #include <machine/cpu.h>
     97 
     98 irqhandler_t *irqhandlers[NIRQS];
     99 
    100 int current_intr_depth;
    101 u_int actual_mask;
    102 #ifdef hpcarm
    103 #define IPL_LEVELS (NIPL+1)
    104 u_int imask[NIPL];
    105 #else
    106 u_int spl_mask;
    107 u_int irqmasks[IPL_LEVELS];
    108 #endif
    109 u_int irqblock[NIRQS];
    110 
    111 
    112 extern void set_spl_masks();
    113 static int fakeintr(void *);
    114 #ifdef DEBUG
    115 static int dumpirqhandlers();
    116 #endif
    117 /*
    118  * Recalculate the interrupt masks from scratch.
    119  * We could code special registry and deregistry versions of this function that
    120  * would be faster, but the code would be nastier, and we don't expect this to
    121  * happen very much anyway.
    122  */
    123 void
    124 intr_calculatemasks()
    125 {
    126 	int irq, level;
    127 	struct irqhandler *q;
    128 	int intrlevel[ICU_LEN];
    129 
    130 	/* First, figure out which levels each IRQ uses. */
    131 	for (irq = 0; irq < ICU_LEN; irq++) {
    132 		int levels = 0;
    133 		for (q = irqhandlers[irq]; q; q = q->ih_next)
    134 			levels |= 1 << q->ih_level;
    135 		intrlevel[irq] = levels;
    136 	}
    137 
    138 	/* Then figure out which IRQs use each level. */
    139 #ifdef hpcarm
    140 	for (level = 0; level < NIPL; level++) {
    141 #else
    142 	for (level = 0; level <= IPL_LEVELS; level++) {
    143 #endif
    144 		int irqs = 0;
    145 		for (irq = 0; irq < ICU_LEN; irq++)
    146 			if (intrlevel[irq] & (1 << level))
    147 				irqs |= 1 << irq;
    148 #ifdef hpcarm
    149 		imask[level] = irqs;
    150 #else
    151 		irqmasks[level] = irqs;
    152 #endif
    153 	}
    154 
    155 	/*
    156 	 * Enforce a hierarchy that gives slow devices a better chance at not
    157 	 * dropping data.
    158 	 */
    159 #ifdef hpcarm
    160 	for (level = NIPL - 1; level > 0; level--)
    161 		imask[level - 1] |= imask[level];
    162 #else
    163 	for (level = IPL_LEVELS; level > 0; level--)
    164 		irqmasks[level - 1] |= irqmasks[level];
    165 #endif
    166 	/*
    167 	 * Calculate irqblock[], which emulates hardware interrupt levels.
    168 	 */
    169 	for (irq = 0; irq < ICU_LEN; irq++) {
    170 		int irqs = 1 << irq;
    171 		for (q = irqhandlers[irq]; q; q = q->ih_next)
    172 #ifdef hpcarm
    173 			irqs |= ~imask[q->ih_level];
    174 #else
    175 			irqs |= ~irqmasks[q->ih_level];
    176 #endif
    177 		irqblock[irq] = irqs;
    178 	}
    179 }
    180 
    181 
    182 const struct evcnt *
    183 sa11x0_intr_evcnt(sa11x0_chipset_tag_t ic, int irq)
    184 {
    185 
    186 	/* XXX for now, no evcnt parent reported */
    187 	return NULL;
    188 }
    189 
    190 void *
    191 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
    192 		      int (*ih_fun)(void *), void *ih_arg)
    193 {
    194 	int saved_cpsr;
    195 	struct irqhandler **p, *q, *ih;
    196 	static struct irqhandler fakehand = {fakeintr};
    197 
    198 	/* no point in sleeping unless someone can free memory. */
    199 	ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
    200 	if (ih == NULL)
    201 		panic("sa11x0_intr_establish: can't malloc handler info");
    202 
    203 	if (irq < 0 || irq >= ICU_LEN || type == IST_NONE)
    204 		panic("intr_establish: bogus irq or type");
    205 
    206 	/* All interrupts are level intrs. */
    207 
    208 	/*
    209 	 * Figure out where to put the handler.
    210 	 * This is O(N^2), but we want to preserve the order, and N is
    211 	 * generally small.
    212 	 */
    213 	for (p = &irqhandlers[irq]; (q = *p) != NULL; p = &q->ih_next)
    214 		;
    215 
    216 	/*
    217 	 * Actually install a fake handler momentarily, since we might be doing
    218 	 * this with interrupts enabled and don't want the real routine called
    219 	 * until masking is set up.
    220 	 */
    221 	fakehand.ih_level = level;
    222 	*p = &fakehand;
    223 
    224 	intr_calculatemasks();
    225 
    226 	/*
    227 	 * Poke the real handler in now.
    228 	 */
    229 	ih->ih_func = ih_fun;
    230 	ih->ih_arg = ih_arg;
    231 #ifdef hpcarm
    232 	ih->ih_count = 0;
    233 #else
    234 	ih->ih_num = 0;
    235 #endif
    236 	ih->ih_next = NULL;
    237 	ih->ih_level = level;
    238 #ifdef hpcarm
    239 	ih->ih_irq = irq;
    240 #endif
    241 	ih->ih_name = NULL; /* XXX */
    242 	*p = ih;
    243 
    244 	saved_cpsr = SetCPSR(I32_bit, I32_bit);
    245 	set_spl_masks();
    246 
    247 	irq_setmasks();
    248 
    249 	SetCPSR(I32_bit, saved_cpsr & I32_bit);
    250 #ifdef DEBUG
    251 	dumpirqhandlers();
    252 #endif
    253 	return (ih);
    254 }
    255 
    256 #ifdef hpcarm
    257 /*
    258  * Deregister an interrupt handler.
    259  */
    260 void
    261 sa11x0_intr_disestablish(sa11x0_chipset_tag_t ic, void *arg)
    262 {
    263 	struct irqhandler *ih = arg;
    264 	int irq = ih->ih_irq;
    265 	int saved_cpsr;
    266 	struct irqhandler **p, *q;
    267 
    268 #if DIAGNOSTIC
    269 	if (irq < 0 || irq >= ICU_LEN)
    270 		panic("intr_disestablish: bogus irq");
    271 #endif
    272 
    273 	/*
    274 	 * Remove the handler from the chain.
    275 	 * This is O(n^2), too.
    276 	 */
    277 	for (p = &irqhandlers[irq]; (q = *p) != NULL && q != ih;
    278 	     p = &q->ih_next)
    279 		;
    280 	if (q)
    281 		*p = q->ih_next;
    282 	else
    283 		panic("intr_disestablish: handler not registered");
    284 	free(ih, M_DEVBUF);
    285 
    286 	intr_calculatemasks();
    287 	saved_cpsr = SetCPSR(I32_bit, I32_bit);
    288 	set_spl_masks();
    289 
    290 	irq_setmasks();
    291 	SetCPSR(I32_bit, saved_cpsr & I32_bit);
    292 
    293 }
    294 #endif
    295 
    296 void
    297 stray_irqhandler(void *p)
    298 {
    299 
    300 	printf("stray interrupt\n");
    301 }
    302 
    303 int
    304 fakeintr(void *p)
    305 {
    306 
    307 	return 0;
    308 }
    309 
    310 #ifdef DEBUG
    311 int
    312 dumpirqhandlers()
    313 {
    314 	int irq;
    315 	struct irqhandler *p;
    316 
    317 	for (irq = 0; irq < ICU_LEN; irq++) {
    318 		printf("irq %d:", irq);
    319 		p = irqhandlers[irq];
    320 		for (; p; p = p->ih_next)
    321 			printf("ih_func: 0x%lx, ", (unsigned long)p->ih_func);
    322 		printf("\n");
    323 	}
    324 	return 0;
    325 }
    326 #endif
    327 /* End of irqhandler.c */
    328