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sa11x0_irqhandler.c revision 1.4
      1 /*	$NetBSD: sa11x0_irqhandler.c,v 1.4 2003/07/15 00:24:51 lukem Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to the NetBSD Foundation
      8  * by IWAMOTO Toshihiro.
      9  *
     10  * This code is derived from software contributed to The NetBSD Foundation
     11  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
     12  * Simulation Facility, NASA Ames Research Center.
     13  *
     14  * Redistribution and use in source and binary forms, with or without
     15  * modification, are permitted provided that the following conditions
     16  * are met:
     17  * 1. Redistributions of source code must retain the above copyright
     18  *    notice, this list of conditions and the following disclaimer.
     19  * 2. Redistributions in binary form must reproduce the above copyright
     20  *    notice, this list of conditions and the following disclaimer in the
     21  *    documentation and/or other materials provided with the distribution.
     22  * 3. All advertising materials mentioning features or use of this software
     23  *    must display the following acknowledgement:
     24  *	This product includes software developed by the NetBSD
     25  *	Foundation, Inc. and its contributors.
     26  * 4. Neither the name of The NetBSD Foundation nor the names of its
     27  *    contributors may be used to endorse or promote products derived
     28  *    from this software without specific prior written permission.
     29  *
     30  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     31  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     32  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     33  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     34  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     35  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     36  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     37  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     38  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     39  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     40  * POSSIBILITY OF SUCH DAMAGE.
     41  */
     42 
     43 /*-
     44  * Copyright (c) 1991 The Regents of the University of California.
     45  * All rights reserved.
     46  *
     47  * This code is derived from software contributed to Berkeley by
     48  * William Jolitz.
     49  *
     50  * Redistribution and use in source and binary forms, with or without
     51  * modification, are permitted provided that the following conditions
     52  * are met:
     53  * 1. Redistributions of source code must retain the above copyright
     54  *    notice, this list of conditions and the following disclaimer.
     55  * 2. Redistributions in binary form must reproduce the above copyright
     56  *    notice, this list of conditions and the following disclaimer in the
     57  *    documentation and/or other materials provided with the distribution.
     58  * 3. All advertising materials mentioning features or use of this software
     59  *    must display the following acknowledgement:
     60  *	This product includes software developed by the University of
     61  *	California, Berkeley and its contributors.
     62  * 4. Neither the name of the University nor the names of its contributors
     63  *    may be used to endorse or promote products derived from this software
     64  *    without specific prior written permission.
     65  *
     66  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     67  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     68  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     69  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     70  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     71  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     72  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     73  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     74  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     75  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     76  * SUCH DAMAGE.
     77  *
     78  *	@(#)isa.c	7.2 (Berkeley) 5/13/91
     79  */
     80 
     81 
     82 #include <sys/cdefs.h>
     83 __KERNEL_RCSID(0, "$NetBSD: sa11x0_irqhandler.c,v 1.4 2003/07/15 00:24:51 lukem Exp $");
     84 
     85 #include "opt_irqstats.h"
     86 
     87 #include <sys/param.h>
     88 #include <sys/kernel.h>
     89 #include <sys/systm.h>
     90 #include <sys/syslog.h>
     91 #include <sys/malloc.h>
     92 #include <uvm/uvm_extern.h>
     93 
     94 #include <arm/sa11x0/sa11x0_reg.h>
     95 #include <arm/sa11x0/sa11x0_var.h>
     96 
     97 #include <machine/intr.h>
     98 #include <machine/cpu.h>
     99 
    100 irqhandler_t *irqhandlers[NIRQS];
    101 
    102 int current_intr_depth;
    103 u_int actual_mask;
    104 #ifdef hpcarm
    105 #define IPL_LEVELS (NIPL+1)
    106 u_int imask[NIPL];
    107 #else
    108 u_int spl_mask;
    109 u_int irqmasks[IPL_LEVELS];
    110 #endif
    111 u_int irqblock[NIRQS];
    112 
    113 
    114 extern void set_spl_masks(void);
    115 static int fakeintr(void *);
    116 #ifdef DEBUG
    117 static int dumpirqhandlers(void);
    118 #endif
    119 void intr_calculatemasks(void);
    120 
    121 const struct evcnt *sa11x0_intr_evcnt(sa11x0_chipset_tag_t, int);
    122 void stray_irqhandler(void *);
    123 
    124 /*
    125  * Recalculate the interrupt masks from scratch.
    126  * We could code special registry and deregistry versions of this function that
    127  * would be faster, but the code would be nastier, and we don't expect this to
    128  * happen very much anyway.
    129  */
    130 void
    131 intr_calculatemasks(void)
    132 {
    133 	int irq, level;
    134 	struct irqhandler *q;
    135 	int intrlevel[ICU_LEN];
    136 
    137 	/* First, figure out which levels each IRQ uses. */
    138 	for (irq = 0; irq < ICU_LEN; irq++) {
    139 		int levels = 0;
    140 		for (q = irqhandlers[irq]; q; q = q->ih_next)
    141 			levels |= 1 << q->ih_level;
    142 		intrlevel[irq] = levels;
    143 	}
    144 
    145 	/* Then figure out which IRQs use each level. */
    146 #ifdef hpcarm
    147 	for (level = 0; level < NIPL; level++) {
    148 #else
    149 	for (level = 0; level <= IPL_LEVELS; level++) {
    150 #endif
    151 		int irqs = 0;
    152 		for (irq = 0; irq < ICU_LEN; irq++)
    153 			if (intrlevel[irq] & (1 << level))
    154 				irqs |= 1 << irq;
    155 #ifdef hpcarm
    156 		imask[level] = irqs;
    157 #else
    158 		irqmasks[level] = irqs;
    159 #endif
    160 	}
    161 
    162 	/*
    163 	 * Enforce a hierarchy that gives slow devices a better chance at not
    164 	 * dropping data.
    165 	 */
    166 #ifdef hpcarm
    167 	for (level = NIPL - 1; level > 0; level--)
    168 		imask[level - 1] |= imask[level];
    169 #else
    170 	for (level = IPL_LEVELS; level > 0; level--)
    171 		irqmasks[level - 1] |= irqmasks[level];
    172 #endif
    173 	/*
    174 	 * Calculate irqblock[], which emulates hardware interrupt levels.
    175 	 */
    176 	for (irq = 0; irq < ICU_LEN; irq++) {
    177 		int irqs = 1 << irq;
    178 		for (q = irqhandlers[irq]; q; q = q->ih_next)
    179 #ifdef hpcarm
    180 			irqs |= ~imask[q->ih_level];
    181 #else
    182 			irqs |= ~irqmasks[q->ih_level];
    183 #endif
    184 		irqblock[irq] = irqs;
    185 	}
    186 }
    187 
    188 
    189 const struct evcnt *
    190 sa11x0_intr_evcnt(sa11x0_chipset_tag_t ic, int irq)
    191 {
    192 
    193 	/* XXX for now, no evcnt parent reported */
    194 	return NULL;
    195 }
    196 
    197 void *
    198 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
    199 		      int (*ih_fun)(void *), void *ih_arg)
    200 {
    201 	int saved_cpsr;
    202 	struct irqhandler **p, *q, *ih;
    203 	static struct irqhandler fakehand = {fakeintr};
    204 
    205 	/* no point in sleeping unless someone can free memory. */
    206 	ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
    207 	if (ih == NULL)
    208 		panic("sa11x0_intr_establish: can't malloc handler info");
    209 
    210 	if (irq < 0 || irq >= ICU_LEN || type == IST_NONE)
    211 		panic("intr_establish: bogus irq or type");
    212 
    213 	/* All interrupts are level intrs. */
    214 
    215 	/*
    216 	 * Figure out where to put the handler.
    217 	 * This is O(N^2), but we want to preserve the order, and N is
    218 	 * generally small.
    219 	 */
    220 	for (p = &irqhandlers[irq]; (q = *p) != NULL; p = &q->ih_next)
    221 		;
    222 
    223 	/*
    224 	 * Actually install a fake handler momentarily, since we might be doing
    225 	 * this with interrupts enabled and don't want the real routine called
    226 	 * until masking is set up.
    227 	 */
    228 	fakehand.ih_level = level;
    229 	*p = &fakehand;
    230 
    231 	intr_calculatemasks();
    232 
    233 	/*
    234 	 * Poke the real handler in now.
    235 	 */
    236 	ih->ih_func = ih_fun;
    237 	ih->ih_arg = ih_arg;
    238 #ifdef hpcarm
    239 	ih->ih_count = 0;
    240 #else
    241 	ih->ih_num = 0;
    242 #endif
    243 	ih->ih_next = NULL;
    244 	ih->ih_level = level;
    245 #ifdef hpcarm
    246 	ih->ih_irq = irq;
    247 #endif
    248 	ih->ih_name = NULL; /* XXX */
    249 	*p = ih;
    250 
    251 	saved_cpsr = SetCPSR(I32_bit, I32_bit);
    252 	set_spl_masks();
    253 
    254 	irq_setmasks();
    255 
    256 	SetCPSR(I32_bit, saved_cpsr & I32_bit);
    257 #ifdef DEBUG
    258 	dumpirqhandlers();
    259 #endif
    260 	return (ih);
    261 }
    262 
    263 #ifdef hpcarm
    264 /*
    265  * Deregister an interrupt handler.
    266  */
    267 void
    268 sa11x0_intr_disestablish(sa11x0_chipset_tag_t ic, void *arg)
    269 {
    270 	struct irqhandler *ih = arg;
    271 	int irq = ih->ih_irq;
    272 	int saved_cpsr;
    273 	struct irqhandler **p, *q;
    274 
    275 #if DIAGNOSTIC
    276 	if (irq < 0 || irq >= ICU_LEN)
    277 		panic("intr_disestablish: bogus irq");
    278 #endif
    279 
    280 	/*
    281 	 * Remove the handler from the chain.
    282 	 * This is O(n^2), too.
    283 	 */
    284 	for (p = &irqhandlers[irq]; (q = *p) != NULL && q != ih;
    285 	     p = &q->ih_next)
    286 		;
    287 	if (q)
    288 		*p = q->ih_next;
    289 	else
    290 		panic("intr_disestablish: handler not registered");
    291 	free(ih, M_DEVBUF);
    292 
    293 	intr_calculatemasks();
    294 	saved_cpsr = SetCPSR(I32_bit, I32_bit);
    295 	set_spl_masks();
    296 
    297 	irq_setmasks();
    298 	SetCPSR(I32_bit, saved_cpsr & I32_bit);
    299 
    300 }
    301 #endif
    302 
    303 void
    304 stray_irqhandler(void *p)
    305 {
    306 
    307 	printf("stray interrupt\n");
    308 }
    309 
    310 int
    311 fakeintr(void *p)
    312 {
    313 
    314 	return 0;
    315 }
    316 
    317 #ifdef DEBUG
    318 int
    319 dumpirqhandlers()
    320 {
    321 	int irq;
    322 	struct irqhandler *p;
    323 
    324 	for (irq = 0; irq < ICU_LEN; irq++) {
    325 		printf("irq %d:", irq);
    326 		p = irqhandlers[irq];
    327 		for (; p; p = p->ih_next)
    328 			printf("ih_func: 0x%lx, ", (unsigned long)p->ih_func);
    329 		printf("\n");
    330 	}
    331 	return 0;
    332 }
    333 #endif
    334 /* End of irqhandler.c */
    335