sa11x0_ost.c revision 1.27
1 /* $NetBSD: sa11x0_ost.c,v 1.27 2009/08/01 10:33:58 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by IWAMOTO Toshihiro and Ichiro FUKUHARA. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: sa11x0_ost.c,v 1.27 2009/08/01 10:33:58 kiyohara Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/time.h> 48 #include <sys/timetc.h> 49 #include <sys/device.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <arm/cpufunc.h> 55 56 #include <arm/sa11x0/sa11x0_reg.h> 57 #include <arm/sa11x0/sa11x0_var.h> 58 #include <arm/sa11x0/sa11x0_ostreg.h> 59 60 static int saost_match(device_t, cfdata_t, void *); 61 static void saost_attach(device_t, device_t, void *); 62 63 static void saost_tc_init(void); 64 65 static uint32_t gettick(void); 66 static int clockintr(void *); 67 static int statintr(void *); 68 69 struct saost_softc { 70 device_t sc_dev; 71 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 75 uint32_t sc_clock_count; 76 uint32_t sc_statclock_count; 77 uint32_t sc_statclock_step; 78 }; 79 80 static struct saost_softc *saost_sc = NULL; 81 82 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 83 #include <arm/xscale/pxa2x0cpu.h> 84 static uint32_t freq; 85 #define TIMER_FREQUENCY freq 86 #elif defined(CPU_XSCALE_PXA270) 87 #define TIMER_FREQUENCY 3250000 /* PXA270 uses 3.25MHz */ 88 #else 89 #define TIMER_FREQUENCY 3686400 /* 3.6864MHz */ 90 #endif 91 92 #ifndef STATHZ 93 #define STATHZ 64 94 #endif 95 96 CFATTACH_DECL_NEW(saost, sizeof(struct saost_softc), 97 saost_match, saost_attach, NULL, NULL); 98 99 static int 100 saost_match(device_t parent, cfdata_t match, void *aux) 101 { 102 103 return 1; 104 } 105 106 static void 107 saost_attach(device_t parent, device_t self, void *aux) 108 { 109 struct saost_softc *sc = device_private(self); 110 struct sa11x0_attach_args *sa = aux; 111 112 aprint_normal("\n"); 113 114 sc->sc_dev = self; 115 sc->sc_iot = sa->sa_iot; 116 117 saost_sc = sc; 118 119 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, 120 &sc->sc_ioh)) 121 panic("%s: Cannot map registers", device_xname(self)); 122 123 /* disable all channel and clear interrupt status */ 124 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_IR, 0); 125 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_SR, 0xf); 126 127 aprint_normal_dev(self, "SA-11x0 OS Timer\n"); 128 } 129 130 static int 131 clockintr(void *arg) 132 { 133 struct saost_softc *sc = saost_sc; 134 struct clockframe *frame = arg; 135 uint32_t oscr, nextmatch, oldmatch; 136 int s; 137 138 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_SR, 1); 139 140 /* schedule next clock intr */ 141 oldmatch = sc->sc_clock_count; 142 nextmatch = oldmatch + TIMER_FREQUENCY / hz; 143 144 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_MR0, nextmatch); 145 oscr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAOST_CR); 146 147 if ((nextmatch > oldmatch && 148 (oscr > nextmatch || oscr < oldmatch)) || 149 (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) { 150 /* 151 * we couldn't set the matching register in time. 152 * just set it to some value so that next interrupt happens. 153 * XXX is it possible to compensate lost interrupts? 154 */ 155 156 s = splhigh(); 157 oscr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAOST_CR); 158 nextmatch = oscr + 10; 159 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_MR0, nextmatch); 160 splx(s); 161 } 162 163 sc->sc_clock_count = nextmatch; 164 hardclock(frame); 165 166 return 1; 167 } 168 169 static int 170 statintr(void *arg) 171 { 172 struct saost_softc *sc = saost_sc; 173 struct clockframe *frame = arg; 174 uint32_t oscr, nextmatch, oldmatch; 175 int s; 176 177 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_SR, 2); 178 179 /* schedule next clock intr */ 180 oldmatch = sc->sc_statclock_count; 181 nextmatch = oldmatch + sc->sc_statclock_step; 182 183 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_MR1, nextmatch); 184 oscr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAOST_CR); 185 186 if ((nextmatch > oldmatch && 187 (oscr > nextmatch || oscr < oldmatch)) || 188 (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) { 189 /* 190 * we couldn't set the matching register in time. 191 * just set it to some value so that next interrupt happens. 192 * XXX is it possible to compensate lost interrupts? 193 */ 194 195 s = splhigh(); 196 oscr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAOST_CR); 197 nextmatch = oscr + 10; 198 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_MR1, nextmatch); 199 splx(s); 200 } 201 202 sc->sc_statclock_count = nextmatch; 203 statclock(frame); 204 205 return 1; 206 } 207 208 void 209 setstatclockrate(int schz) 210 { 211 struct saost_softc *sc = saost_sc; 212 uint32_t count; 213 214 sc->sc_statclock_step = TIMER_FREQUENCY / schz; 215 count = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAOST_CR); 216 count += sc->sc_statclock_step; 217 sc->sc_statclock_count = count; 218 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_MR1, count); 219 } 220 221 void 222 cpu_initclocks(void) 223 { 224 struct saost_softc *sc = saost_sc; 225 226 stathz = STATHZ; 227 profhz = stathz; 228 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 229 TIMER_FREQUENCY = (CPU_IS_PXA250) ? 3686400 : 3250000; 230 #endif 231 sc->sc_statclock_step = TIMER_FREQUENCY / stathz; 232 233 aprint_normal("clock: hz=%d stathz=%d\n", hz, stathz); 234 235 /* Use the channels 0 and 1 for hardclock and statclock, respectively */ 236 sc->sc_clock_count = TIMER_FREQUENCY / hz; 237 sc->sc_statclock_count = TIMER_FREQUENCY / stathz; 238 239 sa11x0_intr_establish(0, 26, 1, IPL_CLOCK, clockintr, 0); 240 sa11x0_intr_establish(0, 27, 1, IPL_CLOCK, statintr, 0); 241 242 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_SR, 0xf); 243 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_IR, 3); 244 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_MR0, 245 sc->sc_clock_count); 246 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_MR1, 247 sc->sc_statclock_count); 248 249 /* Zero the counter value */ 250 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAOST_CR, 0); 251 252 saost_tc_init(); 253 } 254 255 static u_int 256 saost_tc_get_timecount(struct timecounter *tc) 257 { 258 return (u_int)gettick(); 259 } 260 261 static void 262 saost_tc_init(void) 263 { 264 static struct timecounter saost_tc = { 265 .tc_get_timecount = saost_tc_get_timecount, 266 .tc_counter_mask = ~0, 267 .tc_name = "saost_count", 268 #if !(defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250)) 269 .tc_frequency = TIMER_FREQUENCY, 270 #endif 271 .tc_quality = 100, 272 }; 273 274 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 275 saost_tc.tc_frequency = TIMER_FREQUENCY, 276 #endif 277 tc_init(&saost_tc); 278 } 279 280 static uint32_t 281 gettick(void) 282 { 283 struct saost_softc *sc = saost_sc; 284 uint32_t counter; 285 u_int saved_ints; 286 287 saved_ints = disable_interrupts(I32_bit); 288 counter = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAOST_CR); 289 restore_interrupts(saved_ints); 290 291 return counter; 292 } 293 294 void 295 delay(u_int usecs) 296 { 297 uint32_t xtick, otick, delta; 298 int csec, usec; 299 300 csec = usecs / 10000; 301 usec = usecs % 10000; 302 303 usecs = (TIMER_FREQUENCY / 100) * csec 304 + (TIMER_FREQUENCY / 100) * usec / 10000; 305 306 if (saost_sc == NULL) { 307 volatile int k; 308 int j; 309 /* clock isn't initialized yet */ 310 for (; usecs > 0; usecs--) 311 for (j = 100; j > 0; j--, k--) 312 continue; 313 return; 314 } 315 316 otick = gettick(); 317 318 while (1) { 319 xtick = gettick(); 320 delta = xtick - otick; 321 if (delta > usecs) 322 break; 323 usecs -= delta; 324 otick = xtick; 325 } 326 } 327
Indexes created Fri Oct 03 02:09:57 GMT 2025