1 1.2 martin /* $NetBSD: sa11x1_pcicreg.h,v 1.2 2008/04/28 20:23:14 martin Exp $ */ 2 1.1 rjs 3 1.1 rjs /*- 4 1.1 rjs * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.1 rjs * All rights reserved. 6 1.1 rjs * 7 1.1 rjs * This code is derived from software contributed to The NetBSD Foundation 8 1.1 rjs * by IWAMOTO Toshihiro. 9 1.1 rjs * 10 1.1 rjs * Redistribution and use in source and binary forms, with or without 11 1.1 rjs * modification, are permitted provided that the following conditions 12 1.1 rjs * are met: 13 1.1 rjs * 1. Redistributions of source code must retain the above copyright 14 1.1 rjs * notice, this list of conditions and the following disclaimer. 15 1.1 rjs * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 rjs * notice, this list of conditions and the following disclaimer in the 17 1.1 rjs * documentation and/or other materials provided with the distribution. 18 1.1 rjs * 19 1.1 rjs * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 rjs * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 rjs * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 rjs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 rjs * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 rjs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 rjs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 rjs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 rjs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 rjs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 rjs * POSSIBILITY OF SUCH DAMAGE. 30 1.1 rjs */ 31 1.1 rjs 32 1.1 rjs /* Register locations */ 33 1.1 rjs #define SACPCIC_CR 0x1800 34 1.1 rjs #define SACPCIC_SSR 0x1804 35 1.1 rjs #define SACPCIC_SR 0x1808 36 1.1 rjs 37 1.1 rjs /* Control register */ 38 1.1 rjs #define CR_S0_RST 0x01 /* 1 = Assert reset */ 39 1.1 rjs #define CR_S1_RST 0x02 40 1.1 rjs #define CR_S0_FLT 0x04 /* 0 = Float all S0 control lines */ 41 1.1 rjs #define CR_S1_FLT 0x08 42 1.1 rjs #define CR_S0_PWAITEN 0x10 /* S0_nPWAIT enable */ 43 1.1 rjs #define CR_S1_PWAITEN 0x20 44 1.1 rjs #define CR_S0_PSE 0x40 /* 0 = 3V card */ 45 1.1 rjs #define CR_S1_PSE 0x80 46 1.1 rjs 47 1.1 rjs /* Sleep state register */ 48 1.1 rjs #define SSR_S0 0x01 49 1.1 rjs #define SSR_S1 0x02 50 1.1 rjs 51 1.1 rjs /* Status register */ 52 1.1 rjs #define SR_S0_READY 0x0001 53 1.1 rjs #define SR_S1_READY 0x0002 54 1.1 rjs #define SR_S0_CARDDETECT 0x0004 55 1.1 rjs #define SR_S1_CARDDETECT 0x0008 56 1.1 rjs #define SR_S0_VS1 0x0010 57 1.1 rjs #define SR_S0_VS2 0x0020 58 1.1 rjs #define SR_S1_VS1 0x0040 59 1.1 rjs #define SR_S1_VS2 0x0080 60 1.1 rjs #define SR_S0_WP 0x0100 61 1.1 rjs #define SR_S1_WP 0x0200 62 1.1 rjs #define SR_S0_BVD1 0x0400 63 1.1 rjs #define SR_S0_BVD2 0x0800 64 1.1 rjs #define SR_S1_BVD1 0x1000 65 1.1 rjs #define SR_S1_BVD2 0x2000 66 1.1 rjs 67 1.1 rjs /* IRQ numbers */ 68 1.1 rjs #define IRQ_S0_READY 49 69 1.1 rjs #define IRQ_S1_READY 50 70 1.1 rjs #define IRQ_S0_CDVALID 51 71 1.1 rjs #define IRQ_S1_CDVALID 52 72 1.1 rjs #define IRQ_S0_BVD1 53 73 1.1 rjs #define IRQ_S1_BVD1 54 74
Indexes created Wed Oct 01 18:09:54 GMT 2025