sa11x1_pcicreg.h revision 1.2
1 /* $NetBSD: sa11x1_pcicreg.h,v 1.2 2008/04/28 20:23:14 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by IWAMOTO Toshihiro. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* Register locations */ 33 #define SACPCIC_CR 0x1800 34 #define SACPCIC_SSR 0x1804 35 #define SACPCIC_SR 0x1808 36 37 /* Control register */ 38 #define CR_S0_RST 0x01 /* 1 = Assert reset */ 39 #define CR_S1_RST 0x02 40 #define CR_S0_FLT 0x04 /* 0 = Float all S0 control lines */ 41 #define CR_S1_FLT 0x08 42 #define CR_S0_PWAITEN 0x10 /* S0_nPWAIT enable */ 43 #define CR_S1_PWAITEN 0x20 44 #define CR_S0_PSE 0x40 /* 0 = 3V card */ 45 #define CR_S1_PSE 0x80 46 47 /* Sleep state register */ 48 #define SSR_S0 0x01 49 #define SSR_S1 0x02 50 51 /* Status register */ 52 #define SR_S0_READY 0x0001 53 #define SR_S1_READY 0x0002 54 #define SR_S0_CARDDETECT 0x0004 55 #define SR_S1_CARDDETECT 0x0008 56 #define SR_S0_VS1 0x0010 57 #define SR_S0_VS2 0x0020 58 #define SR_S1_VS1 0x0040 59 #define SR_S1_VS2 0x0080 60 #define SR_S0_WP 0x0100 61 #define SR_S1_WP 0x0200 62 #define SR_S0_BVD1 0x0400 63 #define SR_S0_BVD2 0x0800 64 #define SR_S1_BVD1 0x1000 65 #define SR_S1_BVD2 0x2000 66 67 /* IRQ numbers */ 68 #define IRQ_S0_READY 49 69 #define IRQ_S1_READY 50 70 #define IRQ_S0_CDVALID 51 71 #define IRQ_S1_CDVALID 52 72 #define IRQ_S0_BVD1 53 73 #define IRQ_S1_BVD1 54 74
Indexes created Tue Oct 07 21:09:53 GMT 2025