exynos4_reg.h revision 1.7.2.2
1 1.7.2.2 tls /* $NetBSD */ 2 1.7.2.2 tls /*- 3 1.7.2.2 tls * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 1.7.2.2 tls * All rights reserved. 5 1.7.2.2 tls * 6 1.7.2.2 tls * This code is derived from software contributed to The NetBSD Foundation 7 1.7.2.2 tls * by Reinoud Zandijk. 8 1.7.2.2 tls * 9 1.7.2.2 tls * Redistribution and use in source and binary forms, with or without 10 1.7.2.2 tls * modification, are permitted provided that the following conditions 11 1.7.2.2 tls * are met: 12 1.7.2.2 tls * 1. Redistributions of source code must retain the above copyright 13 1.7.2.2 tls * notice, this list of conditions and the following disclaimer. 14 1.7.2.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.7.2.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.7.2.2 tls * documentation and/or other materials provided with the distribution. 17 1.7.2.2 tls * 18 1.7.2.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.7.2.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.7.2.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.7.2.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.7.2.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.7.2.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.7.2.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.7.2.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.7.2.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.7.2.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.7.2.2 tls * POSSIBILITY OF SUCH DAMAGE. 29 1.7.2.2 tls */ 30 1.7.2.2 tls 31 1.7.2.2 tls #ifndef _ARM_SAMSUNG_EXYNOS4_REG_H_ 32 1.7.2.2 tls #define _ARM_SAMSUNG_EXYNOS4_REG_H_ 33 1.7.2.2 tls 34 1.7.2.2 tls /* 35 1.7.2.2 tls * Physical memory layout of Exynos SoCs as per documentation 36 1.7.2.2 tls * 37 1.7.2.2 tls * Base Address Limit Address Size Description 38 1.7.2.2 tls * 0x00000000 0x00010000 64 KB iROM 39 1.7.2.2 tls * 0x02000000 0x02010000 64 KB iROM (mirror of 0x0 to 0x10000) 40 1.7.2.2 tls * 0x02020000 0x02060000 256 KB iRAM 41 1.7.2.2 tls * 0x03000000 0x03020000 128 KB Data memory or general purpose of Samsung 42 1.7.2.2 tls * Reconfigurable Processor SRP. 43 1.7.2.2 tls * 0x03020000 0x03030000 64 KB I-cache or general purpose of SRP. 44 1.7.2.2 tls * 0x03030000 0x03039000 36 KB Configuration memory (write only) of SRP 45 1.7.2.2 tls * 0x03810000 0x03830000 AudioSS's SFR region 46 1.7.2.2 tls * 0x04000000 0x05000000 16 MB Bank0 of Static ROM Controller (SMC) 47 1.7.2.2 tls * (16-bit only) 48 1.7.2.2 tls * 0x05000000 0x06000000 16 MB Bank1 of SMC 49 1.7.2.2 tls * 0x06000000 0x07000000 16 MB Bank2 of SMC 50 1.7.2.2 tls * 0x07000000 0x08000000 16 MB Bank3 of SMC 51 1.7.2.2 tls * 0x08000000 0x0C000000 64 MB Reserved 52 1.7.2.2 tls * 0x0C000000 0x0CD00000 Reserved 53 1.7.2.2 tls * 0x0CE00000 0x0D000000 SFR region of Nand Flash Contr. (NFCON) 54 1.7.2.2 tls * 0x10000000 0x14000000 SFR region 55 1.7.2.2 tls * 0x40000000 0xA0000000 1.5 GB Memory of Dynamic Memory Contr. (DMC)-0 56 1.7.2.2 tls * 0xA0000000 0x00000000 1.5 GB Memory of DMC-1 57 1.7.2.2 tls */ 58 1.7.2.2 tls 59 1.7.2.2 tls /* 60 1.7.2.2 tls * 61 1.7.2.2 tls * The exynos can boot from its iROM or from an external Nand memory. Since 62 1.7.2.2 tls * these are normally hardly used they are excluded from the normal register 63 1.7.2.2 tls * space here. 64 1.7.2.2 tls * 65 1.7.2.2 tls * XXX What about the audio subsystem region. Where are the docs? 66 1.7.2.2 tls * 67 1.7.2.2 tls * EXYNOS_CORE_PBASE points to the main SFR region. 68 1.7.2.2 tls * 69 1.7.2.2 tls * Notes: 70 1.7.2.2 tls * 71 1.7.2.2 tls * SFR Special Function Register 72 1.7.2.2 tls * ISP In-System Programming, like a JTAG 73 1.7.2.2 tls * ACP Accelerator Coherency Port 74 1.7.2.2 tls * SSS Security Sub System 75 1.7.2.2 tls * GIC Generic Interurrupt Controller 76 1.7.2.2 tls * PMU Power Management Unit 77 1.7.2.2 tls * DMC 2D Graphics engine 78 1.7.2.2 tls * LEFTBUS Data bus / Peripheral bus 79 1.7.2.2 tls * RIGHTBUS ,, 80 1.7.2.2 tls * G3D 3D Graphics engine 81 1.7.2.2 tls * MFC Multi-Format Codec 82 1.7.2.2 tls * LCD0 LCD display 83 1.7.2.2 tls * MCT Multi Core Timer 84 1.7.2.2 tls * CMU Clock Management Unit 85 1.7.2.2 tls * TMU Thermal Management Unit 86 1.7.2.2 tls * PPMU Pin Parametric Measurement Unit (?) 87 1.7.2.2 tls * MMU Memory Management Unit 88 1.7.2.2 tls * MCTimer ? 89 1.7.2.2 tls * WDT Watch Dog Timer 90 1.7.2.2 tls * RTC Real Time Clock 91 1.7.2.2 tls * KEYIF Keypad interface 92 1.7.2.2 tls * SECKEY ? 93 1.7.2.2 tls * TZPC TrustZone Protection Controller 94 1.7.2.2 tls * UART Universal asynchronous receiver/transmitter 95 1.7.2.2 tls * I2C Inter IC Connect 96 1.7.2.2 tls * SPI Serial Peripheral Interface Bus 97 1.7.2.2 tls * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS 98 1.7.2.2 tls * PCM Pulse-code modulation, audio stream at set fixed rate 99 1.7.2.2 tls * SPDIF Sony/Philips Digital Interface Format 100 1.7.2.2 tls * Slimbus Serial Low-power Inter-chip Media Bus 101 1.7.2.2 tls * SMMU System mmu. No idea as how its programmed (or not) 102 1.7.2.2 tls * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus 103 1.7.2.2 tls * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, 104 1.7.2.2 tls * SECKEY, TZPC 105 1.7.2.2 tls */ 106 1.7.2.2 tls 107 1.7.2.2 tls /* 108 1.7.2.2 tls * Note that this table is not 80-char friendly, this is done to allow more 109 1.7.2.2 tls * elaborate comments to clarify the register offsets use 110 1.7.2.2 tls */ 111 1.7.2.2 tls 112 1.7.2.2 tls /* CORE */ 113 1.7.2.2 tls #define EXYNOS4_CORE_SIZE 0x04000000 114 1.7.2.2 tls #define EXYNOS4_SDRAM_PBASE 0x40000000 115 1.7.2.2 tls 116 1.7.2.2 tls #define EXYNOS4_SYSREG_OFFSET 0x00010000 117 1.7.2.2 tls #define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */ 118 1.7.2.2 tls #define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* XXX unknown XXX */ 119 1.7.2.2 tls #define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* XXX unknown XXX */ 120 1.7.2.2 tls #define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */ 121 1.7.2.2 tls #define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */ 122 1.7.2.2 tls #define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */ 123 1.7.2.2 tls #define EXYNOS4_KEYIF_OFFSET 0x000A0000 /* Keypad interface */ 124 1.7.2.2 tls #define EXYNOS4_HDMI_CEC_OFFSET 0x000B0000 /* HDMI Consumer Electronic Control */ 125 1.7.2.2 tls #define EXYNOS4_TMU_OFFSET 0x000C0000 /* Thermal Managment */ 126 1.7.2.2 tls #define EXYNOS4_SECKEY_OFFSET 0x00100000 /* XXX unknown XXX */ 127 1.7.2.2 tls #define EXYNOS4_TZPC0_OFFSET 0x00110000 /* ARM Trusted Zone Protection Controller */ 128 1.7.2.2 tls #define EXYNOS4_TZPC1_OFFSET 0x00120000 129 1.7.2.2 tls #define EXYNOS4_TZPC2_OFFSET 0x00130000 130 1.7.2.2 tls #define EXYNOS4_TZPC3_OFFSET 0x00140000 131 1.7.2.2 tls #define EXYNOS4_TZPC4_OFFSET 0x00150000 132 1.7.2.2 tls #define EXYNOS4_TZPC5_OFFSET 0x00160000 133 1.7.2.2 tls #define EXYNOS4_INTCOMBINER_OFFSET 0x00440000 /* combines first 32 interrupt sources */ 134 1.7.2.2 tls #define EXYNOS4_GIC_CNTR_OFFSET 0x00480000 /* generic interrupt controller offset */ 135 1.7.2.2 tls #define EXYNOS4_GIC_DISTRIBUTOR_OFFSET 0x00490000 136 1.7.2.2 tls #define EXYNOS4_AP_C2C_OFFSET 0x00540000 /* Chip 2 Chip XXX doc? XXX */ 137 1.7.2.2 tls #define EXYNOS4_CP_C2C_MODEM_OFFSET 0x00580000 138 1.7.2.2 tls #define EXYNOS4_DMC0_OFFSET 0x00600000 /* Dynamic Memory Controller */ 139 1.7.2.2 tls #define EXYNOS4_DMC1_OFFSET 0x00610000 140 1.7.2.2 tls #define EXYNOS4_PPMU_DMC_L_OFFSET 0x006A0000 /* event counters XXX ? */ 141 1.7.2.2 tls #define EXYNOS4_PPMU_DMC_R_OFFSET 0x006B0000 142 1.7.2.2 tls #define EXYNOS4_PPMU_CPU_OFFSET 0x006C0000 143 1.7.2.2 tls #define EXYNOS4_GPIO_C2C_OFFSET 0x006E0000 144 1.7.2.2 tls #define EXYNOS4_TZASC_LR_OFFSET 0x00700000 /* trust zone access control */ 145 1.7.2.2 tls #define EXYNOS4_TZASC_LW_OFFSET 0x00710000 146 1.7.2.2 tls #define EXYNOS4_TZASC_RR_OFFSET 0x00720000 147 1.7.2.2 tls #define EXYNOS4_TZASC_RW_OFFSET 0x00730000 148 1.7.2.2 tls #define EXYNOS4_G2D_ACP_OFFSET 0x00800000 /* 2D graphics engine */ 149 1.7.2.2 tls #define EXYNOS4_SSS_OFFSET 0x00830000 /* Security Sub System */ 150 1.7.2.2 tls #define EXYNOS4_CORESIGHT_1_OFFSET 0x00880000 /* 1st region */ 151 1.7.2.2 tls #define EXYNOS4_CORESIGHT_2_OFFSET 0x00890000 /* 2nd region */ 152 1.7.2.2 tls #define EXYNOS4_CORESIGHT_3_OFFSET 0x008B0000 /* 3rd region */ 153 1.7.2.2 tls #define EXYNOS4_SMMUG2D_ACP_OFFSET 0x00A40000 /* system mmu for 2D graphics engine */ 154 1.7.2.2 tls #define EXYNOS4_SMMUSSS_OFFSET 0x00A50000 /* system mmu for SSS */ 155 1.7.2.2 tls #define EXYNOS4_GPIO_RIGHT_OFFSET 0x01000000 156 1.7.2.2 tls #define EXYNOS4_GPIO_LEFT_OFFSET 0x01400000 157 1.7.2.2 tls #define EXYNOS4_FIMC0_OFFSET 0x01800000 /* image for display */ 158 1.7.2.2 tls #define EXYNOS4_FIMC1_OFFSET 0x01810000 159 1.7.2.2 tls #define EXYNOS4_FIMC2_OFFSET 0x01820000 160 1.7.2.2 tls #define EXYNOS4_FIMC3_OFFSET 0x01830000 161 1.7.2.2 tls #define EXYNOS4_JPEG_OFFSET 0x01840000 /* JPEG Codec */ 162 1.7.2.2 tls #define EXYNOS4_MIPI_CSI0_OFFSET 0x01880000 /* MIPI-Slim bus Interface */ 163 1.7.2.2 tls #define EXYNOS4_MIPI_CSI1_OFFSET 0x01890000 164 1.7.2.2 tls #define EXYNOS4_SMMUFIMC0_OFFSET 0x01A20000 /* system mmus */ 165 1.7.2.2 tls #define EXYNOS4_SMMUFIMC1_OFFSET 0x01A30000 166 1.7.2.2 tls #define EXYNOS4_SMMUFIMC2_OFFSET 0x01A40000 167 1.7.2.2 tls #define EXYNOS4_SMMUFIMC3_OFFSET 0x01A50000 168 1.7.2.2 tls #define EXYNOS4_SMMUJPEG_OFFSET 0x01A60000 169 1.7.2.2 tls #define EXYNOS4_FIMD0_OFFSET 0x01C00000 /* LCD0 */ 170 1.7.2.2 tls #define EXYNOS4_MIPI_DSI0_OFFSET 0x01C80000 /* LCD0 */ 171 1.7.2.2 tls #define EXYNOS4_SMMUFIMD0_OFFSET 0x01E20000 /* system mmus */ 172 1.7.2.2 tls #define EXYNOS4_FIMC_ISP_OFFSET 0x02000000 /* (digital) camera video input */ 173 1.7.2.2 tls #define EXYNOS4_FIMC_DRC_TOP_OFFSET 0x02010000 174 1.7.2.2 tls #define EXYNOS4_FIMC_FD_TOP_OFFSET 0x02040000 175 1.7.2.2 tls #define EXYNOS4_MPWM_ISP_OFFSET 0x02110000 /* (specialised?) PWM */ 176 1.7.2.2 tls #define EXYNOS4_I2C0_ISP_OFFSET 0x02130000 /* I2C bus */ 177 1.7.2.2 tls #define EXYNOS4_I2C1_ISP_OFFSET 0x02140000 178 1.7.2.2 tls #define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */ 179 1.7.2.2 tls #define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */ 180 1.7.2.2 tls #define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */ 181 1.7.2.2 tls #define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX unknown XXX */ 182 1.7.2.2 tls #define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */ 183 1.7.2.2 tls #define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000 184 1.7.2.2 tls #define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000 185 1.7.2.2 tls #define EXYNOS4_GIC_C_ISP_OFFSET 0x021E0000 186 1.7.2.2 tls #define EXYNOS4_GIC_D_ISP_OFFSET 0x021F0000 187 1.7.2.2 tls #define EXYNOS4_SYSMMU_FIMC_ISP_OFFSET 0x02260000 188 1.7.2.2 tls #define EXYNOS4_SYSMMU_FIMC_DRC_OFFSET 0x02270000 189 1.7.2.2 tls #define EXYNOS4_SYSMMU_FIMC_FD_OFFSET 0x022A0000 190 1.7.2.2 tls #define EXYNOS4_SYSMMU_ISPCPU_OFFSET 0x022B0000 191 1.7.2.2 tls #define EXYNOS4_FIMC_LITE0_OFFSET 0x02390000 /* external image input? */ 192 1.7.2.2 tls #define EXYNOS4_FIMC_LITE1_OFFSET 0x023A0000 193 1.7.2.2 tls #define EXYNOS4_SYSMMU_FIMC_LITE0_OFFSET 0x023B0000 194 1.7.2.2 tls #define EXYNOS4_SYSMMU_FIMC_LITE1_OFFSET 0x023C0000 195 1.7.2.2 tls #define EXYNOS4_USBDEV0_OFFSET 0x02480000 /* XXX unknown XXX */ 196 1.7.2.2 tls #define EXYNOS4_USBDEV0_1_OFFSET 0x02480000 197 1.7.2.2 tls #define EXYNOS4_USBDEV0_2_OFFSET 0x02490000 198 1.7.2.2 tls #define EXYNOS4_USBDEV0_3_OFFSET 0x024A0000 199 1.7.2.2 tls #define EXYNOS4_USBDEV0_4_OFFSET 0x024B0000 200 1.7.2.2 tls #define EXYNOS4_TSI_OFFSET 0x02500000 /* Transport Stream Interface */ 201 1.7.2.2 tls #define EXYNOS4_SDMMC0_OFFSET 0x02510000 /* SD card interface */ 202 1.7.2.2 tls #define EXYNOS4_SDMMC1_OFFSET 0x02520000 203 1.7.2.2 tls #define EXYNOS4_SDMMC2_OFFSET 0x02530000 204 1.7.2.2 tls #define EXYNOS4_SDMMC3_OFFSET 0x02540000 205 1.7.2.2 tls #define EXYNOS4_SDMMC4_OFFSET 0x02550000 206 1.7.2.2 tls #define EXYNOS4_MIPI_HSI_OFFSET 0x02560000 /* LCD0 */ 207 1.7.2.2 tls #define EXYNOS4_SROMC_OFFSET 0x02570000 208 1.7.2.2 tls 209 1.7.2.2 tls #define EXYNOS4_USB2HOST_OFFSET 0x02580000 210 1.7.2.2 tls #define EXYNOS4_USBHOST0_OFFSET 0x02580000 /* USB EHCI */ 211 1.7.2.2 tls #define EXYNOS4_USBHOST1_OFFSET 0x02590000 /* USB OHCI companion to EHCI (paired) */ 212 1.7.2.2 tls #define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */ 213 1.7.2.2 tls 214 1.7.2.2 tls #define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */ 215 1.7.2.2 tls #define EXYNOS4_PDMA1_OFFSET 0x02690000 216 1.7.2.2 tls #define EXYNOS4_GADC_OFFSET 0x026C0000 /* General AD Converter */ 217 1.7.2.2 tls #define EXYNOS4_ROTATOR_OFFSET 0x02810000 /* Image rotator for video output */ 218 1.7.2.2 tls #define EXYNOS4_SMDMA_OFFSET 0x02840000 /* (s) Memory DMA */ 219 1.7.2.2 tls #define EXYNOS4_NSMDMA_OFFSET 0x02850000 /* (ns) Memory DMA */ 220 1.7.2.2 tls #define EXYNOS4_SMMUROTATOR_OFFSET 0x02A30000 /* system mmu for rotator */ 221 1.7.2.2 tls #define EXYNOS4_SMMUMDMA_OFFSET 0x02A40000 222 1.7.2.2 tls #define EXYNOS4_VP_OFFSET 0x02C00000 /* Video Processor */ 223 1.7.2.2 tls #define EXYNOS4_MIXER_OFFSET 0x02C10000 /* Video mixer */ 224 1.7.2.2 tls #define EXYNOS4_HDMI0_OFFSET 0x02D00000 225 1.7.2.2 tls #define EXYNOS4_HDMI1_OFFSET 0x02D10000 226 1.7.2.2 tls #define EXYNOS4_HDMI2_OFFSET 0x02D20000 227 1.7.2.2 tls #define EXYNOS4_HDMI3_OFFSET 0x02D30000 228 1.7.2.2 tls #define EXYNOS4_HDMI4_OFFSET 0x02D40000 229 1.7.2.2 tls #define EXYNOS4_HDMI5_OFFSET 0x02D50000 230 1.7.2.2 tls #define EXYNOS4_HDMI6_OFFSET 0x02D60000 231 1.7.2.2 tls #define EXYNOS4_SMMUTV_OFFSET 0x02E20000 232 1.7.2.2 tls #define EXYNOS4_G3D_OFFSET 0x03000000 /* 3D Graphics Accelerator */ 233 1.7.2.2 tls #define EXYNOS4_PPMU_3D_OFFSET 0x03220000 234 1.7.2.2 tls #define EXYNOS4_MFC_OFFSET 0x03400000 /* Multi Format Codec */ 235 1.7.2.2 tls #define EXYNOS4_SMMUMFC_L_OFFSET 0x03620000 236 1.7.2.2 tls #define EXYNOS4_SMMUMFC_R_OFFSET 0x03630000 237 1.7.2.2 tls #define EXYNOS4_PMMU_MFC_L_OFFSET 0x03660000 /* ? */ 238 1.7.2.2 tls #define EXYNOS4_PMMU_MFC_R_OFFSET 0x03670000 /* ? */ 239 1.7.2.2 tls #define EXYNOS4_UART0_OFFSET 0x03800000 /* serial port 0 */ 240 1.7.2.2 tls #define EXYNOS4_UART1_OFFSET 0x03810000 /* serial port 1 */ 241 1.7.2.2 tls #define EXYNOS4_UART2_OFFSET 0x03820000 /* serial port 2 */ 242 1.7.2.2 tls #define EXYNOS4_UART3_OFFSET 0x03830000 /* serial port 3 */ 243 1.7.2.2 tls #define EXYNOS4_UART4_OFFSET 0x03840000 /* serial port 4 */ 244 1.7.2.2 tls #define EXYNOS4_I2C0_OFFSET 0x03860000 /* Inter Integrated Circuit (I2C) */ 245 1.7.2.2 tls #define EXYNOS4_I2C1_OFFSET 0x03870000 /* Inter Integrated Circuit (I2C) */ 246 1.7.2.2 tls #define EXYNOS4_I2C2_OFFSET 0x03880000 /* Inter Integrated Circuit (I2C) */ 247 1.7.2.2 tls #define EXYNOS4_I2C3_OFFSET 0x03890000 /* Inter Integrated Circuit (I2C) */ 248 1.7.2.2 tls #define EXYNOS4_I2C4_OFFSET 0x038A0000 /* Inter Integrated Circuit (I2C) */ 249 1.7.2.2 tls #define EXYNOS4_I2C5_OFFSET 0x038B0000 /* Inter Integrated Circuit (I2C) */ 250 1.7.2.2 tls #define EXYNOS4_I2C6_OFFSET 0x038C0000 /* Inter Integrated Circuit (I2C) */ 251 1.7.2.2 tls #define EXYNOS4_I2C7_OFFSET 0x038D0000 /* Inter Integrated Circuit (I2C) */ 252 1.7.2.2 tls #define EXYNOS4_I2CHDMI_OFFSET 0x038E0000 /* I2C for HDMI */ 253 1.7.2.2 tls #define EXYNOS4_SPI0_OFFSET 0x03920000 /* Serial Peripheral Interface0 */ 254 1.7.2.2 tls #define EXYNOS4_SPI1_OFFSET 0x03930000 /* Serial Peripheral Interface0 */ 255 1.7.2.2 tls #define EXYNOS4_SPI2_OFFSET 0x03940000 /* Serial Peripheral Interface0 */ 256 1.7.2.2 tls #define EXYNOS4_I2S1_OFFSET 0x03960000 /* sound */ 257 1.7.2.2 tls #define EXYNOS4_I2S2_OFFSET 0x03970000 /* sound */ 258 1.7.2.2 tls #define EXYNOS4_PCM1_OFFSET 0x03980000 /* sound */ 259 1.7.2.2 tls #define EXYNOS4_PCM2_OFFSET 0x03990000 /* sound */ 260 1.7.2.2 tls #define EXYNOS4_AC97_OFFSET 0x039A0000 /* AC97 audio codec sound */ 261 1.7.2.2 tls #define EXYNOS4_SPDIF_OFFSET 0x039B0000 /* SPDIF sound */ 262 1.7.2.2 tls #define EXYNOS4_PWMTIMER_OFFSET 0x039D0000 263 1.7.2.2 tls 264 1.7.2.2 tls /* AUDIOCORE */ 265 1.7.2.2 tls #define EXYNOS4_AUDIOCORE_OFFSET 0x04060000 /* on 1Mb L1 chunk */ 266 1.7.2.2 tls #define EXYNOS4_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS4_AUDIOCORE_OFFSET) 267 1.7.2.2 tls #define EXYNOS4_AUDIOCORE_PBASE 0x03860000 /* Audio SFR */ 268 1.7.2.2 tls #define EXYNOS4_AUDIOCORE_SIZE 0x00001000 269 1.7.2.2 tls 270 1.7.2.2 tls #define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00000000) 271 1.7.2.2 tls 272 1.7.2.2 tls 273 1.7.2.2 tls #endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */ 274 1.7.2.2 tls 275
Indexes created Thu Oct 30 16:09:53 GMT 2025