exynos5422_clock.c revision 1.9
1 /* $NetBSD: exynos5422_clock.c,v 1.9 2018/07/03 16:06:41 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.9 2018/07/03 16:06:41 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/atomic.h> 41 42 #include <dev/clk/clk_backend.h> 43 44 #include <arm/samsung/exynos_reg.h> 45 #include <arm/samsung/exynos_var.h> 46 #include <arm/samsung/exynos_clock.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 static struct clk *exynos5422_clock_decode(device_t, const void *, size_t); 51 52 static const struct fdtbus_clock_controller_func exynos5422_car_fdtclock_funcs = { 53 .decode = exynos5422_clock_decode 54 }; 55 56 /* DT clock ID to clock name mappings */ 57 static struct exynos5422_clock_id { 58 u_int id; 59 const char *name; 60 } exynos5422_clock_ids[] = { 61 { 1, "fin_pll" }, 62 { 2, "fout_apll" }, 63 { 3, "fout_cpll" }, 64 { 4, "fout_dpll" }, 65 { 5, "fout_epll" }, 66 { 6, "fout_rpll" }, 67 { 7, "fout_ipll" }, 68 { 8, "fout_spll" }, 69 { 9, "fout_vpll" }, 70 { 10, "fout_mpll" }, 71 { 11, "fout_bpll" }, 72 { 12, "fout_kpll" }, 73 { 128, "sclk_uart0" }, 74 { 129, "sclk_uart1" }, 75 { 130, "sclk_uart2" }, 76 { 131, "sclk_uart3" }, 77 { 132, "sclk_mmc0" }, 78 { 133, "sclk_mmc1" }, 79 { 134, "sclk_mmc2" }, 80 { 135, "sclk_spi0" }, 81 { 136, "sclk_spi1" }, 82 { 137, "sclk_spi2" }, 83 { 138, "sclk_i2s1" }, 84 { 139, "sclk_i2s2" }, 85 { 140, "sclk_pcm1" }, 86 { 141, "sclk_pcm2" }, 87 { 142, "sclk_spdif" }, 88 { 143, "sclk_hdmi" }, 89 { 144, "sclk_pixel" }, 90 { 145, "sclk_dp1" }, 91 { 146, "sclk_mipi1" }, 92 { 147, "sclk_fimd1" }, 93 { 148, "sclk_maudio0" }, 94 { 149, "sclk_maupcm0" }, 95 { 150, "sclk_usbd300" }, 96 { 151, "sclk_usbd301" }, 97 { 152, "sclk_usbphy300" }, 98 { 153, "sclk_usbphy301" }, 99 { 154, "sclk_unipro" }, 100 { 155, "sclk_pwm" }, 101 { 156, "sclk_gscl_wa" }, 102 { 157, "sclk_gscl_wb" }, 103 { 158, "sclk_hdmiphy" }, 104 { 159, "mau_epll" }, 105 { 160, "sclk_hsic_12m" }, 106 { 161, "sclk_mphy_ixtal24" }, 107 { 257, "uart0" }, 108 { 258, "uart1" }, 109 { 259, "uart2" }, 110 { 260, "uart3" }, 111 { 261, "i2c0" }, 112 { 262, "i2c1" }, 113 { 263, "i2c2" }, 114 { 264, "i2c3" }, 115 { 265, "usi0" }, 116 { 266, "usi1" }, 117 { 267, "usi2" }, 118 { 268, "usi3" }, 119 { 269, "i2c_hdmi" }, 120 { 270, "tsadc" }, 121 { 271, "spi0" }, 122 { 272, "spi1" }, 123 { 273, "spi2" }, 124 { 274, "keyif" }, 125 { 275, "i2s1" }, 126 { 276, "i2s2" }, 127 { 277, "pcm1" }, 128 { 278, "pcm2" }, 129 { 279, "pwm" }, 130 { 280, "spdif" }, 131 { 281, "usi4" }, 132 { 282, "usi5" }, 133 { 283, "usi6" }, 134 { 300, "aclk66_psgen" }, 135 { 301, "chipid" }, 136 { 302, "sysreg" }, 137 { 303, "tzpc0" }, 138 { 304, "tzpc1" }, 139 { 305, "tzpc2" }, 140 { 306, "tzpc3" }, 141 { 307, "tzpc4" }, 142 { 308, "tzpc5" }, 143 { 309, "tzpc6" }, 144 { 310, "tzpc7" }, 145 { 311, "tzpc8" }, 146 { 312, "tzpc9" }, 147 { 313, "hdmi_cec" }, 148 { 314, "seckey" }, 149 { 315, "mct" }, 150 { 316, "wdt" }, 151 { 317, "rtc" }, 152 { 318, "tmu" }, 153 { 319, "tmu_gpu" }, 154 { 330, "pclk66_gpio" }, 155 { 350, "aclk200_fsys2" }, 156 { 351, "mout_mmc0" }, 157 { 352, "mout_mmc1" }, 158 { 353, "mout_mmc2" }, 159 { 354, "sromc" }, 160 { 355, "ufs" }, 161 { 360, "aclk200_fsys" }, 162 { 361, "tsi" }, 163 { 362, "pdma0" }, 164 { 363, "pdma1" }, 165 { 364, "rtic" }, 166 { 365, "usbh20" }, 167 { 366, "usbd300" }, 168 { 367, "usbd301" }, 169 { 380, "aclk400_mscl" }, 170 { 381, "mscl0" }, 171 { 382, "mscl1" }, 172 { 383, "mscl2" }, 173 { 384, "smmu_mscl0" }, 174 { 385, "smmu_mscl1" }, 175 { 386, "smmu_mscl2" }, 176 { 400, "aclk333" }, 177 { 401, "mfc" }, 178 { 402, "smmu_mfcl" }, 179 { 403, "smmu_mfcr" }, 180 { 410, "aclk200_disp1" }, 181 { 411, "dsim1" }, 182 { 412, "dp1" }, 183 { 413, "hdmi" }, 184 { 420, "aclk300_disp1" }, 185 { 421, "fimd1" }, 186 { 422, "smmu_fimd1m0" }, 187 { 423, "smmu_fimd1m1" }, 188 { 430, "aclk166" }, 189 { 431, "mixer" }, 190 { 440, "aclk266" }, 191 { 441, "rotator" }, 192 { 442, "mdma1" }, 193 { 443, "smmu_rotator" }, 194 { 444, "smmu_mdma1" }, 195 { 450, "aclk300_jpeg" }, 196 { 451, "jpeg" }, 197 { 452, "jpeg2" }, 198 { 453, "smmu_jpeg" }, 199 { 454, "smmu_jpeg2" }, 200 { 460, "aclk300_gscl" }, 201 { 461, "smmu_gscl0" }, 202 { 462, "smmu_gscl1" }, 203 { 463, "gscl_wa" }, 204 { 464, "gscl_wb" }, 205 { 465, "gscl0" }, 206 { 466, "gscl1" }, 207 { 467, "fimc_3aa" }, 208 { 470, "aclk266_g2d" }, 209 { 471, "sss" }, 210 { 472, "slim_sss" }, 211 { 473, "mdma0" }, 212 { 480, "aclk333_g2d" }, 213 { 481, "g2d" }, 214 { 490, "aclk333_432_gscl" }, 215 { 491, "smmu_3aa" }, 216 { 492, "smmu_fimcl0" }, 217 { 493, "smmu_fimcl1" }, 218 { 494, "smmu_fimcl3" }, 219 { 495, "fimc_lite3" }, 220 { 496, "fimc_lite0" }, 221 { 497, "fimc_lite1" }, 222 { 500, "aclk_g3d" }, 223 { 501, "g3d" }, 224 { 502, "smmu_mixer" }, 225 { 503, "smmu_g2d" }, 226 { 504, "smmu_mdma0" }, 227 { 505, "mc" }, 228 { 506, "top_rtc" }, 229 { 510, "sclk_uart_isp" }, 230 { 511, "sclk_spi0_isp" }, 231 { 512, "sclk_spi1_isp" }, 232 { 513, "sclk_pwm_isp" }, 233 { 514, "sclk_isp_sensor0" }, 234 { 515, "sclk_isp_sensor1" }, 235 { 516, "sclk_isp_sensor2" }, 236 { 517, "aclk432_scaler" }, 237 { 518, "aclk432_cam" }, 238 { 519, "aclk_fl1550_cam" }, 239 { 520, "aclk550_cam" }, 240 { 640, "mout_hdmi" }, 241 { 641, "mout_g3d" }, 242 { 642, "mout_vpll" }, 243 { 643, "mout_maudio0" }, 244 { 644, "mout_user_aclk333" }, 245 { 645, "mout_sw_aclk333" }, 246 { 646, "mout_user_aclk200_disp1" }, 247 { 647, "mout_sw_aclk200" }, 248 { 648, "mout_user_aclk300_disp1" }, 249 { 649, "mout_sw_aclk300" }, 250 { 650, "mout_user_aclk400_disp1" }, 251 { 651, "mout_sw_aclk400" }, 252 { 768, "dout_pixel" }, 253 }; 254 255 static struct clk *exynos5422_clock_get(void *, const char *); 256 static void exynos5422_clock_put(void *, struct clk *); 257 static u_int exynos5422_clock_get_rate(void *, struct clk *); 258 static int exynos5422_clock_set_rate(void *, struct clk *, u_int); 259 static int exynos5422_clock_enable(void *, struct clk *); 260 static int exynos5422_clock_disable(void *, struct clk *); 261 static int exynos5422_clock_set_parent(void *, struct clk *, struct clk *); 262 static struct clk *exynos5422_clock_get_parent(void *, struct clk *); 263 264 static const struct clk_funcs exynos5422_clock_funcs = { 265 .get = exynos5422_clock_get, 266 .put = exynos5422_clock_put, 267 .get_rate = exynos5422_clock_get_rate, 268 .set_rate = exynos5422_clock_set_rate, 269 .enable = exynos5422_clock_enable, 270 .disable = exynos5422_clock_disable, 271 .set_parent = exynos5422_clock_set_parent, 272 .get_parent = exynos5422_clock_get_parent, 273 }; 274 275 #define CLK_FIXED(_name, _rate) { \ 276 .base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \ 277 .u = { .fixed = { .rate = (_rate) } } \ 278 } 279 280 #define CLK_PLL(_name, _parent, _lock, _con0) { \ 281 .base = { .name = (_name) }, .type = EXYNOS_CLK_PLL, \ 282 .parent = (_parent), \ 283 .u = { \ 284 .pll = { \ 285 .lock_reg = (_lock), \ 286 .con0_reg = (_con0), \ 287 } \ 288 } \ 289 } 290 291 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \ 292 .base = { .name = (_name), .flags = (_f) }, \ 293 .type = EXYNOS_CLK_MUX, \ 294 .alias = (_alias), \ 295 .u = { \ 296 .mux = { \ 297 .nparents = __arraycount(_p), \ 298 .parents = (_p), \ 299 .reg = (_reg), \ 300 .bits = (_bits) \ 301 } \ 302 } \ 303 } 304 305 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \ 306 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p) 307 308 #define CLK_MUX(_name, _reg, _bits, _p) \ 309 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p) 310 311 #define CLK_DIV(_name, _parent, _reg, _bits) { \ 312 .base = { .name = (_name) }, .type = EXYNOS_CLK_DIV, \ 313 .parent = (_parent), \ 314 .u = { \ 315 .div = { \ 316 .reg = (_reg), \ 317 .bits = (_bits) \ 318 } \ 319 } \ 320 } 321 322 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \ 323 .base = { .name = (_name), .flags = (_f) }, \ 324 .type = EXYNOS_CLK_GATE, \ 325 .parent = (_parent), \ 326 .u = { \ 327 .gate = { \ 328 .reg = (_reg), \ 329 .bits = (_bits) \ 330 } \ 331 } \ 332 } 333 334 #define EXYNOS5422_APLL_LOCK 0x00000 335 #define EXYNOS5422_APLL_CON0 0x00100 336 #define EXYNOS5422_CPLL_LOCK 0x10020 337 #define EXYNOS5422_DPLL_LOCK 0x10030 338 #define EXYNOS5422_EPLL_LOCK 0x10040 339 #define EXYNOS5422_RPLL_LOCK 0x10050 340 #define EXYNOS5422_IPLL_LOCK 0x10060 341 #define EXYNOS5422_SPLL_LOCK 0x10070 342 #define EXYNOS5422_VPLL_LOCK 0x10080 343 #define EXYNOS5422_MPLL_LOCK 0x10090 344 #define EXYNOS5422_CPLL_CON0 0x10120 345 #define EXYNOS5422_DPLL_CON0 0x10128 346 #define EXYNOS5422_EPLL_CON0 0x10130 347 #define EXYNOS5422_EPLL_CON1 0x10134 348 #define EXYNOS5422_EPLL_CON2 0x10138 349 #define EXYNOS5422_RPLL_CON0 0x10140 350 #define EXYNOS5422_RPLL_CON1 0x10144 351 #define EXYNOS5422_RPLL_CON2 0x10148 352 #define EXYNOS5422_IPLL_CON0 0x10150 353 #define EXYNOS5422_SPLL_CON0 0x10160 354 #define EXYNOS5422_VPLL_CON0 0x10170 355 #define EXYNOS5422_MPLL_CON0 0x10180 356 #define EXYNOS5422_BPLL_LOCK 0x20010 357 #define EXYNOS5422_BPLL_CON0 0x20110 358 #define EXYNOS5422_KPLL_LOCK 0x28000 359 #define EXYNOS5422_KPLL_CON0 0x28100 360 361 #define EXYNOS5422_SRC_CPU 0x00200 362 #define EXYNOS5422_SRC_TOP0 0x10200 363 #define EXYNOS5422_SRC_TOP1 0x10204 364 #define EXYNOS5422_SRC_TOP2 0x10208 365 #define EXYNOS5422_SRC_TOP3 0x1020c 366 #define EXYNOS5422_SRC_TOP4 0x10210 367 #define EXYNOS5422_SRC_TOP5 0x10214 368 #define EXYNOS5422_SRC_TOP6 0x10218 369 #define EXYNOS5422_SRC_TOP7 0x1021c 370 #define EXYNOS5422_SRC_DISP10 0x1022c 371 #define EXYNOS5422_SRC_MAU 0x10240 372 #define EXYNOS5422_SRC_FSYS 0x10244 373 #define EXYNOS5422_SRC_PERIC0 0x10250 374 #define EXYNOS5422_SRC_PERIC1 0x10254 375 #define EXYNOS5422_SRC_ISP 0x10270 376 #define EXYNOS5422_SRC_TOP10 0x10280 377 #define EXYNOS5422_SRC_TOP11 0x10284 378 #define EXYNOS5422_SRC_TOP12 0x10288 379 380 #define EXYNOS5422_DIV_TOP0 0x10500 381 #define EXYNOS5422_DIV_FSYS0 0x10548 382 #define EXYNOS5422_DIV_FSYS1 0x1054c 383 #define EXYNOS5422_DIV_PERIC0 0x10558 384 385 #define EXYNOS5422_GATE_BUS_FSYS0 0x10740 386 #define EXYNOS5422_GATE_TOP_SCLK_FSYS 0x10840 387 #define EXYNOS5422_GATE_TOP_SCLK_PERIC 0x10850 388 #define EXYNOS5422_GATE_IP_FSYS 0x10944 389 390 static const char *mout_cpll_p[] = { "fin_pll", "fout_cpll" }; 391 static const char *mout_dpll_p[] = { "fin_pll", "fout_dpll" }; 392 static const char *mout_mpll_p[] = { "fin_pll", "fout_mpll" }; 393 static const char *mout_spll_p[] = { "fin_pll", "fout_spll" }; 394 static const char *mout_ipll_p[] = { "fin_pll", "fout_ipll" }; 395 static const char *mout_epll_p[] = { "fin_pll", "fout_epll" }; 396 static const char *mout_rpll_p[] = { "fin_pll", "fout_rpll" }; 397 static const char *mout_group1_p[] = 398 { "sclk_cpll", "sclk_dpll", "sclk_mpp" }; 399 static const char *mout_group2_p[] = 400 { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 401 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 402 static const char *mout_user_aclk200_fsys_p[] = 403 { "fin_pll", "mout_sw_aclk200_fsys" }; 404 static const char *mout_user_aclk200_fsys2_p[] = 405 { "fin_pll", "mout_sw_aclk200_fsys2" }; 406 static const char *mout_sw_aclk200_fsys_p[] = 407 { "dout_aclk200_fsys", "sclk_spll" }; 408 static const char *mout_sw_aclk200_fsys2_p[] = 409 { "dout_aclk200_fsys2", "sclk_spll" }; 410 411 static struct exynos_clk exynos5422_clocks[] = { 412 CLK_FIXED("fin_pll", EXYNOS_F_IN_FREQ), 413 414 CLK_PLL("fout_apll", "fin_pll", EXYNOS5422_APLL_LOCK, 415 EXYNOS5422_APLL_CON0), 416 CLK_PLL("fout_cpll", "fin_pll", EXYNOS5422_CPLL_LOCK, 417 EXYNOS5422_CPLL_CON0), 418 CLK_PLL("fout_dpll", "fin_pll", EXYNOS5422_DPLL_LOCK, 419 EXYNOS5422_DPLL_CON0), 420 CLK_PLL("fout_epll", "fin_pll", EXYNOS5422_EPLL_LOCK, 421 EXYNOS5422_EPLL_CON0), 422 CLK_PLL("fout_rpll", "fin_pll", EXYNOS5422_RPLL_LOCK, 423 EXYNOS5422_RPLL_CON0), 424 CLK_PLL("fout_ipll", "fin_pll", EXYNOS5422_IPLL_LOCK, 425 EXYNOS5422_IPLL_CON0), 426 CLK_PLL("fout_spll", "fin_pll", EXYNOS5422_SPLL_LOCK, 427 EXYNOS5422_SPLL_CON0), 428 CLK_PLL("fout_vpll", "fin_pll", EXYNOS5422_VPLL_LOCK, 429 EXYNOS5422_VPLL_CON0), 430 CLK_PLL("fout_mpll", "fin_pll", EXYNOS5422_MPLL_LOCK, 431 EXYNOS5422_MPLL_CON0), 432 CLK_PLL("fout_bpll", "fin_pll", EXYNOS5422_BPLL_LOCK, 433 EXYNOS5422_BPLL_CON0), 434 CLK_PLL("fout_kpll", "fin_pll", EXYNOS5422_KPLL_LOCK, 435 EXYNOS5422_KPLL_CON0), 436 437 CLK_MUXA("sclk_cpll", "mout_cpll", EXYNOS5422_SRC_TOP6, __BIT(28), 438 mout_cpll_p), 439 CLK_MUXA("sclk_dpll", "mout_dpll", EXYNOS5422_SRC_TOP6, __BIT(24), 440 mout_dpll_p), 441 CLK_MUXA("sclk_mpll", "mout_mpll", EXYNOS5422_SRC_TOP6, __BIT(0), 442 mout_mpll_p), 443 CLK_MUXA("sclk_spll", "mout_spll", EXYNOS5422_SRC_TOP6, __BIT(8), 444 mout_spll_p), 445 CLK_MUXA("sclk_ipll", "mout_ipll", EXYNOS5422_SRC_TOP6, __BIT(12), 446 mout_ipll_p), 447 CLK_MUXF("sclk_epll", "mout_epll", EXYNOS5422_SRC_TOP6, __BIT(20), 448 CLK_SET_RATE_PARENT, mout_epll_p), 449 CLK_MUXF("sclk_rpll", "mout_rpll", EXYNOS5422_SRC_TOP6, __BIT(16), 450 CLK_SET_RATE_PARENT, mout_rpll_p), 451 452 CLK_MUX("mout_sw_aclk200_fsys", EXYNOS5422_SRC_TOP10, __BIT(24), 453 mout_sw_aclk200_fsys_p), 454 CLK_MUX("mout_sw_aclk200_fsys2", EXYNOS5422_SRC_TOP10, __BIT(12), 455 mout_sw_aclk200_fsys2_p), 456 CLK_MUX("mout_user_aclk200_fsys", EXYNOS5422_SRC_TOP3, __BIT(28), 457 mout_user_aclk200_fsys_p), 458 CLK_MUX("mout_user_aclk200_fsys2", EXYNOS5422_SRC_TOP3, __BIT(12), 459 mout_user_aclk200_fsys2_p), 460 CLK_MUX("mout_aclk200_fsys", EXYNOS5422_SRC_TOP0, __BITS(25,24), 461 mout_group1_p), 462 CLK_MUX("mout_aclk200_fsys2", EXYNOS5422_SRC_TOP0, __BITS(13,12), 463 mout_group1_p), 464 465 CLK_MUX("mout_usbd301", EXYNOS5422_SRC_FSYS, __BITS(6,4), 466 mout_group2_p), 467 CLK_MUX("mout_usbd300", EXYNOS5422_SRC_FSYS, __BITS(22,20), 468 mout_group2_p), 469 CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8), 470 mout_group2_p), 471 CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12), 472 mout_group2_p), 473 CLK_MUX("mout_mmc2", EXYNOS5422_SRC_FSYS, __BITS(18,16), 474 mout_group2_p), 475 CLK_MUX("mout_uart0", EXYNOS5422_SRC_PERIC0, __BITS(6,4), 476 mout_group2_p), 477 CLK_MUX("mout_uart1", EXYNOS5422_SRC_PERIC0, __BITS(10,8), 478 mout_group2_p), 479 CLK_MUX("mout_uart2", EXYNOS5422_SRC_PERIC0, __BITS(14,12), 480 mout_group2_p), 481 CLK_MUX("mout_uart3", EXYNOS5422_SRC_PERIC0, __BITS(18,16), 482 mout_group2_p), 483 484 CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)), 485 CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)), 486 487 CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(15,12)), 488 CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(19,16)), 489 CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(23,20)), 490 CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(27,24)), 491 CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)), 492 CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)), 493 CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)), 494 CLK_DIV("dout_uart0", "mout_uart0", EXYNOS5422_DIV_PERIC0, 495 __BITS(11,8)), 496 CLK_DIV("dout_uart1", "mout_uart1", EXYNOS5422_DIV_PERIC0, 497 __BITS(15,12)), 498 CLK_DIV("dout_uart2", "mout_uart2", EXYNOS5422_DIV_PERIC0, 499 __BITS(19,16)), 500 CLK_DIV("dout_uart3", "mout_uart3", EXYNOS5422_DIV_PERIC0, 501 __BITS(23,20)), 502 503 CLK_GATE("aclk200_fsys", "mout_user_aclk200_fsys", EXYNOS5422_GATE_BUS_FSYS0, 504 __BIT(9), CLK_SET_RATE_PARENT), 505 CLK_GATE("aclk200_fsys2", "mout_user_aclk200_fsys2", EXYNOS5422_GATE_BUS_FSYS0, 506 __BIT(10), CLK_SET_RATE_PARENT), 507 508 CLK_GATE("sclk_mmc0", "dout_mmc0", EXYNOS5422_GATE_TOP_SCLK_FSYS, 509 __BIT(0), CLK_SET_RATE_PARENT), 510 CLK_GATE("sclk_mmc1", "dout_mmc1", EXYNOS5422_GATE_TOP_SCLK_FSYS, 511 __BIT(1), CLK_SET_RATE_PARENT), 512 CLK_GATE("sclk_mmc2", "dout_mmc2", EXYNOS5422_GATE_TOP_SCLK_FSYS, 513 __BIT(2), CLK_SET_RATE_PARENT), 514 CLK_GATE("sclk_usbphy301", "dout_usbphy301", EXYNOS5422_GATE_TOP_SCLK_FSYS, 515 __BIT(7), CLK_SET_RATE_PARENT), 516 CLK_GATE("sclk_usbphy300", "dout_usbphy300", EXYNOS5422_GATE_TOP_SCLK_FSYS, 517 __BIT(8), CLK_SET_RATE_PARENT), 518 CLK_GATE("sclk_usbd300", "dout_usbd300", EXYNOS5422_GATE_TOP_SCLK_FSYS, 519 __BIT(9), CLK_SET_RATE_PARENT), 520 CLK_GATE("sclk_usbd301", "dout_usbd301", EXYNOS5422_GATE_TOP_SCLK_FSYS, 521 __BIT(10), CLK_SET_RATE_PARENT), 522 CLK_GATE("sclk_uart0", "dout_uart0", EXYNOS5422_GATE_TOP_SCLK_PERIC, 523 __BIT(0), CLK_SET_RATE_PARENT), 524 CLK_GATE("sclk_uart1", "dout_uart1", EXYNOS5422_GATE_TOP_SCLK_PERIC, 525 __BIT(1), CLK_SET_RATE_PARENT), 526 CLK_GATE("sclk_uart2", "dout_uart2", EXYNOS5422_GATE_TOP_SCLK_PERIC, 527 __BIT(2), CLK_SET_RATE_PARENT), 528 CLK_GATE("sclk_uart3", "dout_uart3", EXYNOS5422_GATE_TOP_SCLK_PERIC, 529 __BIT(3), CLK_SET_RATE_PARENT), 530 531 CLK_GATE("mmc0", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS, 532 __BIT(12), CLK_SET_RATE_PARENT), 533 CLK_GATE("mmc1", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS, 534 __BIT(13), CLK_SET_RATE_PARENT), 535 CLK_GATE("mmc2", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS, 536 __BIT(14), CLK_SET_RATE_PARENT), 537 CLK_GATE("usbh20", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS, 538 __BIT(18), CLK_SET_RATE_PARENT), 539 CLK_GATE("usbd300", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS, 540 __BIT(19), CLK_SET_RATE_PARENT), 541 CLK_GATE("usbd301", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS, 542 __BIT(20), CLK_SET_RATE_PARENT), 543 }; 544 545 static int exynos5422_clock_match(device_t, cfdata_t, void *); 546 static void exynos5422_clock_attach(device_t, device_t, void *); 547 548 struct exynos5422_clock_softc { 549 device_t sc_dev; 550 bus_space_tag_t sc_bst; 551 bus_space_handle_t sc_bsh; 552 553 struct clk_domain sc_clkdom; 554 }; 555 556 static void exynos5422_clock_print_header(void); 557 static void exynos5422_clock_print(struct exynos5422_clock_softc *, 558 struct exynos_clk *); 559 560 CFATTACH_DECL_NEW(exynos5422_clock, sizeof(struct exynos5422_clock_softc), 561 exynos5422_clock_match, exynos5422_clock_attach, NULL, NULL); 562 563 #define CLOCK_READ(sc, reg) \ 564 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 565 #define CLOCK_WRITE(sc, reg, val) \ 566 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 567 568 static int 569 exynos5422_clock_match(device_t parent, cfdata_t cf, void *aux) 570 { 571 const char * const compatible[] = { "samsung,exynos5800-clock", NULL }; 572 struct fdt_attach_args * const faa = aux; 573 574 return of_match_compatible(faa->faa_phandle, compatible); 575 } 576 577 static void 578 exynos5422_clock_attach(device_t parent, device_t self, void *aux) 579 { 580 struct exynos5422_clock_softc * const sc = device_private(self); 581 struct fdt_attach_args * const faa = aux; 582 bus_addr_t addr; 583 bus_size_t size; 584 int error; 585 586 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 587 aprint_error(": couldn't get registers\n"); 588 return; 589 } 590 591 sc->sc_dev = self; 592 sc->sc_bst = faa->faa_bst; 593 594 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 595 if (error) { 596 aprint_error(": couldn't map %#llx: %d", 597 (uint64_t)addr, error); 598 return; 599 } 600 601 aprint_naive("\n"); 602 aprint_normal(": Exynos5422 Clock Controller\n"); 603 604 sc->sc_clkdom.funcs = &exynos5422_clock_funcs; 605 sc->sc_clkdom.priv = sc; 606 for (u_int n = 0; n < __arraycount(exynos5422_clocks); n++) { 607 exynos5422_clocks[n].base.domain = &sc->sc_clkdom; 608 } 609 610 fdtbus_register_clock_controller(self, faa->faa_phandle, 611 &exynos5422_car_fdtclock_funcs); 612 613 exynos5422_clock_print_header(); 614 for (u_int n = 0; n < __arraycount(exynos5422_clocks); n++) { 615 exynos5422_clock_print(sc, &exynos5422_clocks[n]); 616 } 617 } 618 619 static struct exynos_clk * 620 exynos5422_clock_find(const char *name) 621 { 622 u_int n; 623 624 for (n = 0; n < __arraycount(exynos5422_clocks); n++) { 625 if (strcmp(exynos5422_clocks[n].base.name, name) == 0) { 626 return &exynos5422_clocks[n]; 627 } 628 } 629 630 return NULL; 631 } 632 633 static struct exynos_clk * 634 exynos5422_clock_find_by_id(u_int clock_id) 635 { 636 u_int n; 637 638 for (n = 0; n < __arraycount(exynos5422_clock_ids); n++) { 639 if (exynos5422_clock_ids[n].id == clock_id) { 640 const char *name = exynos5422_clock_ids[n].name; 641 return exynos5422_clock_find(name); 642 } 643 } 644 645 return NULL; 646 } 647 648 static void 649 exynos5422_clock_print_header(void) 650 { 651 printf(" %-10s %2s %-10s %-5s %10s\n", 652 "clock", "", "parent", "type", "rate"); 653 printf(" %-10s %2s %-10s %-5s %10s\n", 654 "=====", "", "======", "====", "===="); 655 } 656 657 static void 658 exynos5422_clock_print(struct exynos5422_clock_softc *sc, 659 struct exynos_clk *eclk) 660 { 661 struct exynos_clk *eclk_parent; 662 struct clk *clk_parent; 663 const char *type = "?"; 664 665 switch (eclk->type) { 666 case EXYNOS_CLK_FIXED: 667 type = "fixed"; 668 break; 669 case EXYNOS_CLK_PLL: 670 type = "pll"; 671 break; 672 case EXYNOS_CLK_MUX: 673 type = "mux"; 674 break; 675 case EXYNOS_CLK_DIV: 676 type = "div"; 677 break; 678 case EXYNOS_CLK_GATE: 679 type = "gate"; 680 break; 681 } 682 683 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base); 684 eclk_parent = (struct exynos_clk *)clk_parent; 685 686 printf(" %-10s %2s %-10s %-5s %10d Hz\n", 687 eclk->base.name, 688 eclk_parent ? "<-" : "", 689 eclk_parent ? eclk_parent->base.name : "", 690 type, clk_get_rate(&eclk->base)); 691 } 692 693 static struct clk * 694 exynos5422_clock_decode(device_t dev, const void *data, size_t len) 695 { 696 struct exynos_clk *eclk; 697 698 /* #clock-cells should be 1 */ 699 if (len != 4) { 700 return NULL; 701 } 702 703 const u_int clock_id = be32dec(data); 704 705 eclk = exynos5422_clock_find_by_id(clock_id); 706 if (eclk) 707 return &eclk->base; 708 709 return NULL; 710 } 711 712 static u_int 713 exynos5422_clock_get_rate_pll(struct exynos5422_clock_softc *sc, 714 struct exynos_clk *eclk) 715 { 716 struct exynos_pll_clk *epll = &eclk->u.pll; 717 struct exynos_clk *clk_parent; 718 719 KASSERT(eclk->type == EXYNOS_CLK_PLL); 720 721 clk_parent = exynos5422_clock_find(eclk->parent); 722 KASSERT(clk_parent != NULL); 723 const u_int rate_parent = exynos5422_clock_get_rate(sc, 724 &clk_parent->base); 725 726 const uint32_t v = CLOCK_READ(sc, epll->con0_reg); 727 728 return PLL_FREQ(rate_parent, v); 729 } 730 731 static int 732 exynos5422_clock_set_rate_pll(struct exynos5422_clock_softc *sc, 733 struct exynos_clk *eclk, u_int rate) 734 { 735 /* TODO */ 736 return EOPNOTSUPP; 737 } 738 739 static int 740 exynos5422_clock_set_parent_mux(struct exynos5422_clock_softc *sc, 741 struct exynos_clk *eclk, struct exynos_clk *eclk_parent) 742 { 743 struct exynos_mux_clk *emux = &eclk->u.mux; 744 const char *pname = eclk_parent->base.name; 745 u_int sel; 746 747 KASSERT(eclk->type == EXYNOS_CLK_MUX); 748 749 for (sel = 0; sel < emux->nparents; sel++) { 750 if (strcmp(pname, emux->parents[sel]) == 0) { 751 break; 752 } 753 } 754 if (sel == emux->nparents) { 755 return EINVAL; 756 } 757 758 uint32_t v = CLOCK_READ(sc, emux->reg); 759 v &= ~emux->bits; 760 v |= __SHIFTIN(sel, emux->bits); 761 CLOCK_WRITE(sc, emux->reg, v); 762 763 return 0; 764 } 765 766 static struct exynos_clk * 767 exynos5422_clock_get_parent_mux(struct exynos5422_clock_softc *sc, 768 struct exynos_clk *eclk) 769 { 770 struct exynos_mux_clk *emux = &eclk->u.mux; 771 772 KASSERT(eclk->type == EXYNOS_CLK_MUX); 773 774 const uint32_t v = CLOCK_READ(sc, emux->reg); 775 const u_int sel = __SHIFTOUT(v, emux->bits); 776 777 KASSERT(sel < emux->nparents); 778 779 return exynos5422_clock_find(emux->parents[sel]); 780 } 781 782 static u_int 783 exynos5422_clock_get_rate_div(struct exynos5422_clock_softc *sc, 784 struct exynos_clk *eclk) 785 { 786 struct exynos_div_clk *ediv = &eclk->u.div; 787 struct clk *clk_parent; 788 789 KASSERT(eclk->type == EXYNOS_CLK_DIV); 790 791 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base); 792 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); 793 794 const uint32_t v = CLOCK_READ(sc, ediv->reg); 795 const u_int div = __SHIFTOUT(v, ediv->bits); 796 797 return parent_rate / (div + 1); 798 } 799 800 static int 801 exynos5422_clock_set_rate_div(struct exynos5422_clock_softc *sc, 802 struct exynos_clk *eclk, u_int rate) 803 { 804 struct exynos_div_clk *ediv = &eclk->u.div; 805 struct clk *clk_parent; 806 int tmp_div, new_div = -1; 807 u_int tmp_rate; 808 809 KASSERT(eclk->type == EXYNOS_CLK_DIV); 810 811 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base); 812 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); 813 814 for (tmp_div = 0; tmp_div < __SHIFTOUT_MASK(ediv->bits); tmp_div++) { 815 tmp_rate = parent_rate / (tmp_div + 1); 816 if (tmp_rate <= rate) { 817 new_div = tmp_div; 818 break; 819 } 820 } 821 if (new_div == -1) 822 return EINVAL; 823 824 uint32_t v = CLOCK_READ(sc, ediv->reg); 825 v &= ~ediv->bits; 826 v |= __SHIFTIN(new_div, ediv->bits); 827 CLOCK_WRITE(sc, ediv->reg, v); 828 829 return 0; 830 } 831 832 static int 833 exynos5422_clock_enable_gate(struct exynos5422_clock_softc *sc, 834 struct exynos_clk *eclk, bool enable) 835 { 836 struct exynos_gate_clk *egate = &eclk->u.gate; 837 838 KASSERT(eclk->type == EXYNOS_CLK_GATE); 839 840 uint32_t v = CLOCK_READ(sc, egate->reg); 841 if (enable) { 842 v |= egate->bits; 843 } else { 844 v &= ~egate->bits; 845 } 846 CLOCK_WRITE(sc, egate->reg, v); 847 848 return 0; 849 } 850 851 /* 852 * clk api 853 */ 854 855 static struct clk * 856 exynos5422_clock_get(void *priv, const char *name) 857 { 858 struct exynos_clk *eclk; 859 860 eclk = exynos5422_clock_find(name); 861 if (eclk == NULL) 862 return NULL; 863 864 atomic_inc_uint(&eclk->refcnt); 865 866 return &eclk->base; 867 } 868 869 static void 870 exynos5422_clock_put(void *priv, struct clk *clk) 871 { 872 struct exynos_clk *eclk = (struct exynos_clk *)clk; 873 874 KASSERT(eclk->refcnt > 0); 875 876 atomic_dec_uint(&eclk->refcnt); 877 } 878 879 static u_int 880 exynos5422_clock_get_rate(void *priv, struct clk *clk) 881 { 882 struct exynos_clk *eclk = (struct exynos_clk *)clk; 883 struct clk *clk_parent; 884 885 switch (eclk->type) { 886 case EXYNOS_CLK_FIXED: 887 return eclk->u.fixed.rate; 888 case EXYNOS_CLK_PLL: 889 return exynos5422_clock_get_rate_pll(priv, eclk); 890 case EXYNOS_CLK_MUX: 891 case EXYNOS_CLK_GATE: 892 clk_parent = exynos5422_clock_get_parent(priv, clk); 893 return exynos5422_clock_get_rate(priv, clk_parent); 894 case EXYNOS_CLK_DIV: 895 return exynos5422_clock_get_rate_div(priv, eclk); 896 default: 897 panic("exynos5422: unknown eclk type %d", eclk->type); 898 } 899 } 900 901 static int 902 exynos5422_clock_set_rate(void *priv, struct clk *clk, u_int rate) 903 { 904 struct exynos_clk *eclk = (struct exynos_clk *)clk; 905 906 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0); 907 908 switch (eclk->type) { 909 case EXYNOS_CLK_FIXED: 910 return EIO; 911 case EXYNOS_CLK_PLL: 912 return exynos5422_clock_set_rate_pll(priv, eclk, rate); 913 case EXYNOS_CLK_MUX: 914 return EIO; 915 case EXYNOS_CLK_DIV: 916 return exynos5422_clock_set_rate_div(priv, eclk, rate); 917 case EXYNOS_CLK_GATE: 918 return EINVAL; 919 default: 920 panic("exynos5422: unknown eclk type %d", eclk->type); 921 } 922 } 923 924 static int 925 exynos5422_clock_enable(void *priv, struct clk *clk) 926 { 927 struct exynos_clk *eclk = (struct exynos_clk *)clk; 928 929 switch (eclk->type) { 930 case EXYNOS_CLK_FIXED: 931 return 0; /* always on */ 932 case EXYNOS_CLK_PLL: 933 return 0; /* XXX */ 934 case EXYNOS_CLK_MUX: 935 case EXYNOS_CLK_DIV: 936 return 0; 937 case EXYNOS_CLK_GATE: 938 return exynos5422_clock_enable_gate(priv, eclk, true); 939 default: 940 panic("exynos5422: unknown eclk type %d", eclk->type); 941 } 942 } 943 944 static int 945 exynos5422_clock_disable(void *priv, struct clk *clk) 946 { 947 struct exynos_clk *eclk = (struct exynos_clk *)clk; 948 949 switch (eclk->type) { 950 case EXYNOS_CLK_FIXED: 951 return EINVAL; /* always on */ 952 case EXYNOS_CLK_PLL: 953 return EINVAL; /* XXX */ 954 case EXYNOS_CLK_MUX: 955 case EXYNOS_CLK_DIV: 956 return EINVAL; 957 case EXYNOS_CLK_GATE: 958 return exynos5422_clock_enable_gate(priv, eclk, false); 959 default: 960 panic("exynos5422: unknown eclk type %d", eclk->type); 961 } 962 } 963 964 static int 965 exynos5422_clock_set_parent(void *priv, struct clk *clk, struct clk *clk_parent) 966 { 967 struct exynos_clk *eclk = (struct exynos_clk *)clk; 968 struct exynos_clk *eclk_parent = (struct exynos_clk *)clk_parent; 969 970 switch (eclk->type) { 971 case EXYNOS_CLK_FIXED: 972 case EXYNOS_CLK_PLL: 973 case EXYNOS_CLK_DIV: 974 case EXYNOS_CLK_GATE: 975 return EINVAL; 976 case EXYNOS_CLK_MUX: 977 return exynos5422_clock_set_parent_mux(priv, eclk, eclk_parent); 978 default: 979 panic("exynos5422: unknown eclk type %d", eclk->type); 980 } 981 } 982 983 static struct clk * 984 exynos5422_clock_get_parent(void *priv, struct clk *clk) 985 { 986 struct exynos_clk *eclk = (struct exynos_clk *)clk; 987 struct exynos_clk *eclk_parent = NULL; 988 989 switch (eclk->type) { 990 case EXYNOS_CLK_FIXED: 991 case EXYNOS_CLK_PLL: 992 case EXYNOS_CLK_DIV: 993 case EXYNOS_CLK_GATE: 994 if (eclk->parent != NULL) { 995 eclk_parent = exynos5422_clock_find(eclk->parent); 996 } 997 break; 998 case EXYNOS_CLK_MUX: 999 eclk_parent = exynos5422_clock_get_parent_mux(priv, eclk); 1000 break; 1001 default: 1002 panic("exynos5422: unknown eclk type %d", eclk->type); 1003 } 1004 1005 return (struct clk *)eclk_parent; 1006 } 1007
Indexes created Tue Sep 30 17:09:57 GMT 2025