exynos5_reg.h revision 1.6
1 1.6 reinoud /* $NetBSD: exynos5_reg.h,v 1.6 2014/06/06 14:25:19 reinoud Exp $ */ 2 1.1 matt 3 1.1 matt /*- 4 1.1 matt * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 1.1 matt * All rights reserved. 6 1.1 matt * 7 1.1 matt * This code is derived from software contributed to The NetBSD Foundation 8 1.1 matt * by Nick Hudson. 9 1.1 matt * 10 1.1 matt * Redistribution and use in source and binary forms, with or without 11 1.1 matt * modification, are permitted provided that the following conditions 12 1.1 matt * are met: 13 1.1 matt * 1. Redistributions of source code must retain the above copyright 14 1.1 matt * notice, this list of conditions and the following disclaimer. 15 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 matt * notice, this list of conditions and the following disclaimer in the 17 1.1 matt * documentation and/or other materials provided with the distribution. 18 1.1 matt * 19 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 matt * POSSIBILITY OF SUCH DAMAGE. 30 1.1 matt */ 31 1.1 matt 32 1.1 matt #ifndef _ARM_SAMSUNG_EXYNOS5_REG_H_ 33 1.1 matt #define _ARM_SAMSUNG_EXYNOS5_REG_H_ 34 1.1 matt 35 1.1 matt /* 36 1.1 matt * Physical memory layout of Exynos5 SoCs as per documentation 37 1.1 matt * 38 1.1 matt * Base Address Limit Address Size Description 39 1.1 matt * 0x00000000 0x0000FFFF 64 KB iROM/iRAM/SROM 40 1.1 matt * 0x02000000 0x0200FFFF 64 KB iROM (mirror of 0x0 to 0xFFFF) 41 1.1 matt * 0x02020000 0x02077FFF 352 KB iRAM 42 1.1 matt * 0x03000000 0x03027FFF 160 KB Data memory of SRP 43 1.1 matt * 0x03028000 0x0303FFFF 96 KB I-cache of SRP 44 1.1 matt * 0x03040000 0x03048FFF 36 KB Configuration memory of SRP (write-only) 45 1.1 matt * 0x03800000 0x0386FFFF SFR region of AudioSS 46 1.1 matt * 0x04000000 0x04020000 128 KB SROMC's Bank 0 47 1.1 matt * 0x05000000 0x05020000 128 KB SROMC's Bank 1 48 1.1 matt * 0x06000000 0x06020000 128 KB SROMC's Bank 2 49 1.1 matt * 0x07000000 0x07020000 128 KB SROMC's Bank 3 50 1.1 matt * 0x10000000 0x1FFFFFFF SFR region 51 1.1 matt * 0x20000000 0xFFFFFFFF DRAM 52 1.1 matt */ 53 1.1 matt 54 1.3 reinoud /* CORE */ 55 1.1 matt #define EXYNOS5_CORE_SIZE 0x10000000 56 1.1 matt #define EXYNOS5_SDRAM_PBASE 0x20000000 57 1.1 matt 58 1.3 reinoud #define EXYNOS5_CMU_COREPART_OFFSET 0x00010000 59 1.1 matt #define EXYNOS5_CMU_TOPPART_OFFSET 0x00020000 60 1.1 matt #define EXYNOS5_CMU_MEMPART_OFFSET 0x00030000 61 1.1 matt #define EXYNOS5_ALIVE_OFFSET 0x00040000 62 1.1 matt #define EXYNOS5_SYSREG_OFFSET 0x00050000 63 1.1 matt #define EXYNOS5_TMU_OFFSET 0x00060000 64 1.1 matt #define EXYNOS5_MONOTONIC_CNT_OFFSET 0x000C0000 65 1.1 matt 66 1.1 matt #define EXYNOS5_HDMI_CEC_OFFSET 0x001B0000 67 1.1 matt #define EXYNOS5_MCT_OFFSET 0x001C0000 68 1.1 matt #define EXYNOS5_WDT_OFFSET 0x001D0000 69 1.1 matt #define EXYNOS5_RTC_OFFSET 0x001E0000 70 1.1 matt 71 1.1 matt #define EXYNOS5_INT_COMB_CPU_OFFSET 0x00440000 72 1.1 matt #define EXYNOS5_INT_COMB_IOP_OFFSET 0x00450000 73 1.1 matt #define EXYNOS5_GIC_CPU_OFFSET 0x00480000 74 1.2 reinoud #define EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET 0x00481000 75 1.2 reinoud #define EXYNOS5_GIC_IOP_CONTROLLER_OFFSET 0x00482000 76 1.1 matt #define EXYNOS5_MPCORE PRIVATE REGION_OFFSET 0x00500000 77 1.1 matt #define EXYNOS5_NS MDMA0 0x00800000 78 1.1 matt #define EXYNOS5_SSS_OFFSET 0x00830000 79 1.1 matt #define EXYNOS5_SSS_KEY_OFFSET 0x00840000 80 1.1 matt #define EXYNOS5_2D_OFFSET 0x00850000 81 1.1 matt #define EXYNOS5_CSSYS_OFFSET 0x00880000 82 1.1 matt #if 0 83 1.1 matt #define EXYNOS5_A15 (EAGLE) 0x00890000 84 1.1 matt #define EXYNOS5_A5 (IOP) 0x008A0000 85 1.1 matt #define EXYNOS5_A5 (ISP) 0x008B0000 86 1.1 matt #endif 87 1.1 matt #define EXYNOS5_SYSMMU_MDMA_OFFSET 0x00A40000 88 1.1 matt #define EXYNOS5_SYSMMU_SSS_OFFSET 0x00A50000 89 1.1 matt #define EXYNOS5_SYSMMU_2D_OFFSET 0x00A60000 90 1.1 matt #define EXYNOS5_DREXII_PHY0_OFFSET 0x00C00000 91 1.1 matt #define EXYNOS5_DREXII_PHY1_OFFSET 0x00C10000 92 1.1 matt #define EXYNOS5_AS_A_3D_OFFSET 0x00CC0000 93 1.1 matt #define EXYNOS5_AS_A_C2C_OFFSET 0x00CD0000 94 1.1 matt #define EXYNOS5_AS_A_LEFT_BUS_OFFSET 0x00CE0000 95 1.1 matt #define EXYNOS5_AS_A_RIGHT0_BUS_OFFSET 0x00CF0000 96 1.1 matt #define EXYNOS5_AS_A_DISP1_BUS_OFFSET 0x00D00000 97 1.1 matt #define EXYNOS5_C2C_GPIO_OFFSET 0x00D10000 98 1.1 matt #define EXYNOS5_DREXII_OFFSET 0x00DD0000 99 1.1 matt #define EXYNOS5_AS_A_EFCON_OFFSET 0x00DE0000 100 1.1 matt #define EXYNOS5_AP_C2C_OFFSET 0x00E00000 101 1.1 matt #define EXYNOS5_CP_C2C_OFFSET 0x00E40000 102 1.1 matt #define EXYNOS5_AS_A_ACP_BLK_OFFSET 0x00E80000 103 1.1 matt #define EXYNOS5_AS_A_CPU_P_BLK_OFFSET 0x00E90000 104 1.1 matt #define EXYNOS5_AS_A_LBX_BUS_OFFSET 0x00F00000 105 1.1 matt #define EXYNOS5_AS_A_R1BX_BUS_OFFSET 0x00F10000 106 1.1 matt #define EXYNOS5_AS_A_R0BX_BUS_OFFSET 0x00F20000 107 1.1 matt #define EXYNOS5_AS_A_CPU_OFFSET 0x00F30000 108 1.1 matt #define EXYNOS5_MFC_OFFSET 0x01000000 109 1.1 matt #define EXYNOS5_SYSMMU_MFC0_R 0x01200000 110 1.1 matt #define EXYNOS5_SYSMMU_MFC1_L 0x01210000 111 1.1 matt #define EXYNOS5_GPIO_LEFT_OFFSET 0x01400000 112 1.1 matt #define EXYNOS5_AS_A_MFC_OFFSET 0x01680000 113 1.1 matt #define EXYNOS5_AS_A_GENX_OFFSET 0x016A0000 114 1.1 matt #define EXYNOS5_3D ENGINE_OFFSET 0x01800000 115 1.1 matt #define EXYNOS5_ROTATOR_OFFSET 0x01C00000 116 1.1 matt #define EXYNOS5_NS_MDMA1 0x01C10000 117 1.1 matt #define EXYNOS5_SYSMMU_ROTATOR_OFFSET 0x01D40000 118 1.1 matt #define EXYNOS5_SYSMMU_MDMA1 0x01D50000 119 1.1 matt #define EXYNOS5_AS_A_FILE_OFFSET 0x01DA0000 120 1.1 matt #define EXYNOS5_AS_A_GPS_OFFSET 0x01DB0000 121 1.1 matt #define EXYNOS5_AS_A_JPEG_OFFSET 0x01DC0000 122 1.1 matt #define EXYNOS5_JPEG_OFFSET 0x01E00000 123 1.1 matt #define EXYNOS5_SYSMMU_JPEG_OFFSET 0x01F20000 124 1.6 reinoud 125 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET00 0x02000000 126 1.6 reinoud #define EXYNOS5_USB3_XHCI0_OFFSET 0x02100000 127 1.6 reinoud #if 0 128 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET01 0x02010000 129 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET02 0x02020000 130 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET03 0x02030000 131 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET04 0x02040000 132 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET05 0x02050000 133 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET06 0x02060000 134 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET07 0x02070000 135 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET08 0x02080000 136 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET09 0x02090000 137 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET10 0x020A0000 138 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET11 0x020B0000 139 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET12 0x020C0000 140 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET13 0x020D0000 141 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET14 0x020E0000 142 1.4 reinoud #define EXYNOS5_USB3_DEVICE_LINK_OFFSET15 0x020F0000 143 1.1 matt #define EXYNOS5_USB3_DEVICE_CTRL_OFFSET 0x02100000 144 1.6 reinoud #endif 145 1.6 reinoud #define EXYNOS5_USB3_PHY0_OFFSET 0x02100000 146 1.1 matt #define EXYNOS5_USB2_HOST_EHCI_OFFSET 0x02110000 147 1.1 matt #define EXYNOS5_USB2_HOST_OHCI_OFFSET 0x02120000 148 1.1 matt #define EXYNOS5_USB2_HOST_CTRL_OFFSET 0x02130000 149 1.1 matt #define EXYNOS5_USB2_DEVICE_LINK_OFFSET 0x02140000 150 1.1 matt #define EXYNOS5_MIPI_HSI_OFFSET 0x02160000 151 1.1 matt #define EXYNOS5_SATA PHY CONTROL_OFFSET 0x02170000 152 1.5 reinoud #define EXYNOS5_MCUCTL_IOP_OFFSET 0x02180000 /* XXX unknown XXX */ 153 1.1 matt #define EXYNOS5_WDT_IOP_OFFSET 0x02190000 154 1.1 matt #define EXYNOS5_PDMA0 0x021A0000 155 1.1 matt #define EXYNOS5_PDMA1 0x021B0000 156 1.1 matt #define EXYNOS5_RTIC_OFFSET 0x021C0000 157 1.1 matt #define EXYNOS5_SATA_I2C_PHY_CONTROL_OFFSET 0x021D0000 158 1.1 matt #define EXYNOS5_MSH0 0x02200000 159 1.1 matt #define EXYNOS5_MSH1 0x02210000 160 1.1 matt #define EXYNOS5_MSH2 0x02220000 161 1.1 matt #define EXYNOS5_MSH3 0x02230000 162 1.1 matt #define EXYNOS5_SROMC_OFFSET 0x02250000 163 1.1 matt #define EXYNOS5_SATA_OFFSET 0x022F0000 164 1.1 matt #if 0 165 1.1 matt #define EXYNOS5_AXI_FILE_D64 (GPV) 0x02300000 166 1.1 matt #define EXYNOS5_AXI_FILE_D64 (GPV) 0x02310000 167 1.1 matt #endif 168 1.1 matt #define EXYNOS5_AXI_USB_SATA_D64 0x02320000 169 1.1 matt #if 0 170 1.1 matt #define EXYNOS5_AXI_USB_SATA_D64 0x02330000 171 1.1 matt #endif 172 1.1 matt #define EXYNOS5_SYSMMU_IOPROCESSOR_OFFSET 0x02360000 173 1.1 matt #define EXYNOS5_SYSMMU_RTIC_OFFSET 0x02370000 174 1.1 matt #define EXYNOS5_AS_A_IOP_FD64X_OFFSET 0x02380000 175 1.1 matt #define EXYNOS5_AS_A_AUDIO_OFFSET 0x02390000 176 1.6 reinoud 177 1.6 reinoud #define EXYNOS5_USB3_XHCI1_OFFSET 0x02100000 178 1.6 reinoud #define EXYNOS5_USB3_PHY1_OFFSET 0x02500000 179 1.6 reinoud 180 1.1 matt #if 0 181 1.1 matt #define EXYNOS5_AXI_GPS (GPV) 0x02600000 182 1.1 matt #define EXYNOS5_AXI_GPS (GPV) 0x02610000 183 1.1 matt #endif 184 1.1 matt #define EXYNOS5_AS_A_GPSCPU_OFFSET 0x02620000 185 1.1 matt #define EXYNOS5_SYSMMU_GPS_OFFSET 0x02630000 186 1.1 matt #define EXYNOS5_UART0_OFFSET 0x02C00000 187 1.1 matt #define EXYNOS5_UART1_OFFSET 0x02C10000 188 1.1 matt #define EXYNOS5_UART2_OFFSET 0x02C20000 189 1.1 matt #define EXYNOS5_UART3_OFFSET 0x02C30000 190 1.1 matt #define EXYNOS5_USI0_OFFSET 0x02C50000 191 1.1 matt #define EXYNOS5_I2C0_OFFSET 0x02C60000 192 1.1 matt #define EXYNOS5_I2C1_OFFSET 0x02C70000 193 1.1 matt #define EXYNOS5_I2C2_OFFSET 0x02C80000 194 1.1 matt #define EXYNOS5_I2C3_OFFSET 0x02C90000 195 1.1 matt #define EXYNOS5_I2C4_OFFSET 0x02CA0000 196 1.1 matt #define EXYNOS5_I2C5_OFFSET 0x02CB0000 197 1.1 matt #define EXYNOS5_I2C6_OFFSET 0x02CC0000 198 1.1 matt #define EXYNOS5_I2C7_OFFSET 0x02CD0000 199 1.1 matt #define EXYNOS5_I2C_HDMI_OFFSET 0x02CE0000 200 1.1 matt #define EXYNOS5_USI_OFFSET 0x02D00000 201 1.1 matt #define EXYNOS5_TSADC_OFFSET 0x02D10000 202 1.1 matt #define EXYNOS5_SPI0_OFFSET 0x02D20000 203 1.3 reinoud #define EXYNOS5_SPI1_OFFSET 0x02D30000 204 1.3 reinoud #define EXYNOS5_SPI2_OFFSET 0x02D40000 205 1.3 reinoud #define EXYNOS5_USI2_OFFSET 0x02D50000 206 1.3 reinoud #define EXYNOS5_I2S1_OFFSET 0x02D60000 207 1.3 reinoud #define EXYNOS5_I2S2_OFFSET 0x02D70000 208 1.3 reinoud #define EXYNOS5_PCM1_OFFSET 0x02D80000 209 1.3 reinoud #define EXYNOS5_PCM2_OFFSET 0x02D90000 210 1.3 reinoud #define EXYNOS5_AC97_OFFSET 0x02DA0000 211 1.3 reinoud #define EXYNOS5_SPDIF_OFFSET 0x02DB0000 212 1.3 reinoud #define EXYNOS5_PWM_OFFSET 0x02DD0000 213 1.3 reinoud #define EXYNOS5_USI3_OFFSET 0x02DE0000 214 1.3 reinoud #define EXYNOS5_FIMC_ISP_OFFSET 0x03000000 215 1.3 reinoud #define EXYNOS5_FIMC_DRC_TOP_OFFSET 0x03010000 216 1.3 reinoud #define EXYNOS5_FIMC_SCALERC_OFFSET 0x03020000 217 1.3 reinoud #define EXYNOS5_FIMC_SCALERP_OFFSET 0x03030000 218 1.3 reinoud #define EXYNOS5_FIMC_FD_TOP_OFFSET 0x03040000 219 1.1 matt #define EXYNOS5_FIMC_ODC_OFFSET 0x03050000 220 1.1 matt #define EXYNOS5_FIMC_DIS_OFFSET 0x03060000 221 1.1 matt #define EXYNOS5_FIMC_3DNR_OFFSET 0x03070000 222 1.1 matt #define EXYNOS5_ASYNC_AXI_M_OFFSET 0x030F0000 223 1.1 matt #define EXYNOS5_MPWM_ISP_OFFSET 0x03110000 224 1.1 matt #define EXYNOS5_I2C2_ISP_OFFSET 0x03120000 225 1.1 matt #define EXYNOS5_I2C0_ISP_OFFSET 0x03130000 226 1.1 matt #define EXYNOS5_I2C1_ISP_OFFSET 0x03140000 227 1.1 matt #define EXYNOS5_MTCADC_ISP_OFFSET 0x03150000 228 1.1 matt #define EXYNOS5_PWM_ISP_OFFSET 0x03160000 229 1.1 matt #define EXYNOS5_WDT_ISP_OFFSET 0x03170000 230 1.1 matt #define EXYNOS5_MCUCTL_ISP_OFFSET 0x03180000 231 1.1 matt #define EXYNOS5_UART_ISP_OFFSET 0x03190000 232 1.1 matt #define EXYNOS5_SPI0_ISP_OFFSET 0x031A0000 233 1.1 matt #define EXYNOS5_SPI1_ISP_OFFSET 0x031B0000 234 1.1 matt #define EXYNOS5_GIC_C_ISP_OFFSET 0x031E0000 235 1.1 matt #define EXYNOS5_GIC_D_ISP_OFFSET 0x031F0000 236 1.1 matt #define EXYNOS5_SYSMMU_FIMC_ISP_OFFSET 0x03260000 237 1.1 matt #define EXYNOS5_SYSMMU_FIMC_DRC_OFFSET 0x03270000 238 1.1 matt #define EXYNOS5_SYSMMU_FIMC_SCALERC_OFFSET 0x03280000 239 1.1 matt #define EXYNOS5_SYSMMU_FIMC_SCALERP_OFFSET 0x03290000 240 1.1 matt #define EXYNOS5_SYSMMU_FIMC_FD_OFFSET 0x032A0000 241 1.1 matt #define EXYNOS5_SYSMMU_ISPCPU_OFFSET 0x032B0000 242 1.1 matt #define EXYNOS5_SYSMMU_FIMC_ODC_OFFSET 0x032C0000 243 1.1 matt #define EXYNOS5_SYSMMU_FIMC_DIS0 0x032D0000 244 1.1 matt #define EXYNOS5_SYSMMU_FIMC_DIS1 0x032E0000 245 1.1 matt #define EXYNOS5_SYSMMU_FIMC_3DNR_OFFSET 0x032F0000 246 1.1 matt #define EXYNOS5_GPIO_RIGHT_OFFSET 0x03400000 247 1.1 matt #define EXYNOS5_AS_A_MFC0_OFFSET 0x03620000 248 1.1 matt #define EXYNOS5_AS_A_ISP0_OFFSET 0x03640000 249 1.1 matt #define EXYNOS5_AS_A_ISP1_OFFSET 0x03650000 250 1.1 matt #define EXYNOS5_AS_A_RIGHT1_OFFSET 0x03670000 251 1.1 matt #define EXYNOS5_FIMC_LITE0_OFFSET 0x03C00000 252 1.1 matt #define EXYNOS5_FIMC_LITE1_OFFSET 0x03C10000 253 1.1 matt #define EXYNOS5_MIPI_CSI0_OFFSET 0x03C20000 254 1.1 matt #define EXYNOS5_MIPI_CSI1_OFFSET 0x03C30000 255 1.1 matt #define EXYNOS5_SYSMMU_FIMC_LITE0_OFFSET 0x03C40000 256 1.1 matt #define EXYNOS5_SYSMMU_FIMC_LITE1_OFFSET 0x03C50000 257 1.1 matt #define EXYNOS5_FIMC_LITE2_OFFSET 0x03C90000 258 1.1 matt #define EXYNOS5_SYSMMU_FIMC_LITE2_OFFSET 0x03CA0000 259 1.1 matt #define EXYNOS5_GSCALER0_OFFSET 0x03E00000 260 1.1 matt #define EXYNOS5_GSCALER1_OFFSET 0x03E10000 261 1.1 matt #define EXYNOS5_GSCALER2_OFFSET 0x03E20000 262 1.1 matt #define EXYNOS5_GSCALER3_OFFSET 0x03E30000 263 1.1 matt #define EXYNOS5_AS_A_GS0_OFFSET 0x03E40000 264 1.1 matt #define EXYNOS5_AS_A_GS1_OFFSET 0x03E50000 265 1.1 matt #define EXYNOS5_AS_A_GS2_OFFSET 0x03E60000 266 1.1 matt #define EXYNOS5_AS_A_GS3_OFFSET 0x03E70000 267 1.1 matt #define EXYNOS5_SYSMMU_GSCALER0_OFFSET 0x03E80000 268 1.1 matt #define EXYNOS5_SYSMMU_GSCALER1_OFFSET 0x03E90000 269 1.1 matt #define EXYNOS5_SYSMMU_GSCALER2_OFFSET 0x03EA0000 270 1.1 matt #define EXYNOS5_SYSMMU_GSCALER3_OFFSET 0x03EB0000 271 1.1 matt #define EXYNOS5_AS_A_GSCALER_OFFSET 0x04220000 272 1.1 matt #define EXYNOS5_DISP1_MIX_OFFSET 0x04400000 273 1.1 matt #define EXYNOS5_DISP1_ENH_OFFSET 0x04410000 274 1.1 matt #define EXYNOS5_DISP1_CTRL_OFFSET 0x04420000 275 1.1 matt #define EXYNOS5_MIE_OFFSET 0x04430000 276 1.1 matt #define EXYNOS5_TV_MIXER_OFFSET 0x04450000 277 1.1 matt #define EXYNOS5_MIPI_DSI1_OFFSET 0x04500000 278 1.1 matt #define EXYNOS5_DP1_OFFSET 0x04510000 279 1.1 matt #define EXYNOS5_HDMI_0_OFFSET 0x04530000 280 1.1 matt #define EXYNOS5_HDMI_1_OFFSET 0x04540000 281 1.1 matt #define EXYNOS5_HDMI_2_OFFSET 0x04550000 282 1.1 matt #define EXYNOS5_HDMI_3_OFFSET 0x04560000 283 1.1 matt #define EXYNOS5_HDMI_4_OFFSET 0x04570000 284 1.1 matt #define EXYNOS5_HDMI_5_OFFSET 0x04580000 285 1.1 matt #define EXYNOS5_HDMI_6_OFFSET 0x04590000 286 1.1 matt #define EXYNOS5_DP1_1_OFFSET 0x045B0000 287 1.1 matt #define EXYNOS5_SYSMMU_DISP1_OFFSET 0x04640000 288 1.1 matt #define EXYNOS5_SYSMMU_TV_OFFSET 0x04650000 289 1.1 matt #define EXYNOS5_AS_A_TV_OFFSET 0x046D0000 290 1.1 matt #if 0 291 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08000000 292 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08010000 293 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08020000 294 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08030000 295 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08040000 296 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08050000 297 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08060000 298 1.1 matt #define EXYNOS5_AES0&EF0 (NEW) 0x08070000 299 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x08080000 300 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x08090000 301 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x080A0000 302 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x080B0000 303 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x080C0000 304 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x080D0000 305 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x080E0000 306 1.1 matt #define EXYNOS5_AES0&EF0 (NER) 0x080F0000 307 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08100000 308 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08110000 309 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08120000 310 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08130000 311 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08140000 312 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08150000 313 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08160000 314 1.1 matt #define EXYNOS5_AES0&EF0 (EW) 0x08170000 315 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x08180000 316 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x08190000 317 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x081A0000 318 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x081B0000 319 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x081C0000 320 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x081D0000 321 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x081E0000 322 1.1 matt #define EXYNOS5_AES0&EF0 (ER) 0x081F0000 323 1.3 reinoud #define EXYNOS5_EFCON0_OFFSET 0x08200000 324 1.1 matt #define EXYNOS5_AES0 SFR_OFFSET 0x08300000 325 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08400000 326 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08410000 327 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08420000 328 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08430000 329 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08440000 330 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08450000 331 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08460000 332 1.1 matt #define EXYNOS5_AES1&EF1 (NEW) 0x08470000 333 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x08480000 334 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x08490000 335 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x084A0000 336 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x084B0000 337 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x084C0000 338 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x084D0000 339 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x084E0000 340 1.1 matt #define EXYNOS5_AES1&EF1 (NER) 0x084F0000 341 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08500000 342 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08510000 343 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08520000 344 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08530000 345 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08540000 346 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08550000 347 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08560000 348 1.1 matt #define EXYNOS5_AES1&EF1 (EW) 0x08570000 349 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x08580000 350 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x08590000 351 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x085A0000 352 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x085B0000 353 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x085C0000 354 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x085D0000 355 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x085E0000 356 1.1 matt #define EXYNOS5_AES1&EF1 (ER) 0x085F0000 357 1.1 matt #endif 358 1.3 reinoud #define EXYNOS5_EFCON1_OFFSET 0x08600000 359 1.1 matt #define EXYNOS5_NS_NDMA_OFFSET 0x08680000 360 1.1 matt #define EXYNOS5_S_NDMA_OFFSET 0x08690000 361 1.3 reinoud #define EXYNOS5_AES1_OFFSET 0x08700000 362 1.3 reinoud 363 1.3 reinoud /* AUDIOCORE */ 364 1.3 reinoud #define EXYNOS5_AUDIOCORE_OFFSET 0x10000000 365 1.3 reinoud #define EXYNOS5_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS5_AUDIOCORE_OFFSET) 366 1.3 reinoud #define EXYNOS5_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */ 367 1.3 reinoud #define EXYNOS5_AUDIOCORE_SIZE 0x00070000 368 1.3 reinoud 369 1.1 matt 370 1.1 matt #endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */ 371
Indexes created Thu Oct 02 14:10:14 GMT 2025